1 // Copyright (C) 2022 Beken Corporation
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #include "bk_arch.h"
16 #include "platform.h"
17 #include "boot.h"
18 #include "cache.h"
19
20
21 extern void reset_vector(void);
22 extern unsigned int g_sram_addr_map[SRAM_BLOCK_COUNT];
23
24 /* This must be a leaf function, no child function */
25 void __platform_init (void) __attribute__((naked));
__platform_init(void)26 void __platform_init(void)
27 {
28 /* Do your platform low-level initial */
29
30 __asm("ret");
31 }
32
c_startup(void)33 void c_startup(void)
34 {
35 #define MEMCPY(des, src, n) __builtin_memcpy ((des), (src), (n))
36 #define MEMSET(s, c, n) __builtin_memset ((s), (c), (n))
37 /* Data section initialization */
38 extern char _edata, _end;
39 unsigned int size;
40
41 #if !CONFIG_SLAVE_CORE
42 int i = 0;
43
44 /* Init all sram block */
45 for(i = 0; i < SRAM_BLOCK_COUNT; i++)
46 {
47 MEMSET((void *)g_sram_addr_map[i], 0x0, SRAM_BLOCK_SIZE);
48 }
49 #endif
50
51 #ifdef CFG_XIP
52 extern char _data_lmastart, _data_start;
53 extern char _itcm_lma_start, _itcm_ema_start, _itcm_lma_end;
54 extern char _dtcm_lma_start, _dtcm_ema_start, _dtcm_lma_end;
55 extern char _dtcm_bss_start, _dtcm_bss_end;
56
57 /*Copy ITCM section from LMA to VMA*/
58
59 size = &_itcm_lma_end - &_itcm_lma_start;
60 if(size!=0)
61 {
62 MEMCPY(&_itcm_ema_start, &_itcm_lma_start, size);
63 }
64 /*Copy DTCM section from LMA to VMA*/
65 size = &_dtcm_lma_end - &_dtcm_lma_start;
66 if(size!=0)
67 {
68 MEMCPY(&_dtcm_ema_start, &_dtcm_lma_start, size);
69 }
70
71 /* Clear DTCM bss section */
72 size = &_dtcm_bss_end - &_dtcm_bss_start;
73 if(size!=0)
74 {
75 MEMSET(&_dtcm_bss_start, 0, size);
76 }
77 #endif
78
79 /* Copy data section from LMA to VMA */
80 size = &_edata - &_data_start;
81 MEMCPY(&_data_start, &_data_lmastart, size);
82
83 /* Clear bss section */
84 size = &_end - &_edata;
85 MEMSET(&_edata, 0, size);
86
87 #if CONFIG_SAVE_BOOT_TIME_POINT
88 save_mtime_point(CPU_INIT_MEM_TIME);
89 #endif
90 }
91
system_init(void)92 void system_init(void)
93 {
94 /*
95 * Do your system reset handling here
96 */
97 /* Reset the CPU reset vector for this program. */
98 MCUIP_SMU->RESET_VECTOR = (unsigned int)(long)reset_vector;
99
100 /* Enable PLIC features */
101 if (read_csr(NDS_MMISC_CTL) & (1 << 1)) {
102 /* External PLIC interrupt is vectored */
103 __nds__plic_set_feature(NDS_PLIC_FEATURE_PREEMPT | NDS_PLIC_FEATURE_VECTORED);
104 } else {
105 /* External PLIC interrupt is NOT vectored */
106 __nds__plic_set_feature(NDS_PLIC_FEATURE_PREEMPT);
107 }
108
109 /* Enable misaligned access and non-blocking load. */
110 set_csr(NDS_MMISC_CTL, (1 << 8) | (1 << 6));
111 }
112
arch_init(void)113 void arch_init(void)
114 {
115 //arch_enable_align_fault();
116 }
117