1 /****************************************************************************** 2 * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK") 3 * All rights reserved. 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 *****************************************************************************/ 18 #ifndef ADC_REG_H 19 #define ADC_REG_H 20 #include "../sys.h" 21 22 #define areg_adc_clk_setting 0x82 23 enum { 24 FLD_CLK_24M_TO_SAR_EN = BIT(6), 25 }; 26 27 #define areg_adc_vref 0xea 28 enum { 29 FLD_ADC_VREF_CHN_M = BIT_RNG(0, 1), 30 }; 31 #define areg_adc_ain_chn_misc 0xeb 32 enum { 33 FLD_ADC_AIN_NEGATIVE = BIT_RNG(0, 3), 34 FLD_ADC_AIN_POSITIVE = BIT_RNG(4, 7), 35 }; 36 #define areg_adc_res_m 0xec 37 enum { 38 FLD_ADC_RES_M = BIT_RNG(0, 1), 39 FLD_ADC_EN_DIFF_CHN_M = BIT(6), 40 }; 41 #define areg_adc_tsmaple_m 0xee 42 enum { 43 FLD_ADC_TSAMPLE_CYCLE_CHN_M = BIT_RNG(0, 3), 44 }; 45 #define areg_r_max_mc 0xef 46 enum { 47 FLD_R_MAX_MC0 = BIT_RNG(0, 7), // 0xef<7:0> r_max_mc[7:0] 48 }; 49 #define areg_r_max_s 0xf1 50 enum { 51 FLD_R_MAX_S = BIT_RNG(0, 3), // 0xf1<3:0> r_max_s 52 FLD_R_MAX_MC1 = BIT_RNG(6, 7), // 0xf1<7:6> r_max_mc[9:8] 53 }; 54 #define areg_adc_chn_en 0xf2 55 enum { 56 FLD_ADC_CHN_EN_M = BIT(2), 57 FLD_ADC_MAX_SCNT = BIT_RNG(4, 5), 58 }; 59 #define areg_adc_data_sample_control 0xf3 60 enum { 61 FLD_NOT_SAMPLE_ADC_DATA = BIT(0), 62 }; 63 #define areg_adc_sample_clk_div 0xf4 64 enum { 65 FLD_ADC_SAMPLE_CLK_DIV = BIT_RNG(0, 2), 66 }; 67 #define areg_adc_misc_l 0xf7 68 #define areg_adc_misc_h 0xf8 69 #define areg_adc_vref_vbat_div 0xf9 70 enum { 71 FLD_ADC_VREF_VBAT_DIV = BIT_RNG(2, 3), 72 }; 73 #define areg_ain_scale 0xfa 74 enum { 75 FLD_ADC_ITRIM_PREAMP = BIT_RNG(0, 1), 76 FLD_ADC_ITRIM_VREFBUF = BIT_RNG(2, 3), 77 FLD_ADC_ITRIM_VCMBUF = BIT_RNG(4, 5), 78 FLD_SEL_AIN_SCALE = BIT_RNG(6, 7), 79 }; 80 #define areg_adc_pga_ctrl 0xfc 81 enum { 82 FLD_SAR_ADC_POWER_DOWN = BIT(5), 83 }; 84 #define areg_temp_sensor_ctrl 0x00 85 enum { 86 FLD_TEMP_SENSOR_POWER_DOWN = BIT(4), 87 }; 88 #endif 89