1 // Copyright (C) 2022 Beken Corporation 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #pragma once 16 17 #ifdef __cplusplus 18 extern "C" { 19 #endif 20 21 typedef volatile struct { 22 //reg00 23 union { 24 struct { 25 uint32_t uart1: 1; /**< bit[0], UART1 clock select, 1-CLK_26M, 0-DCO Divided clk_mux */ 26 uint32_t uart2: 1; /**< bit[1], UART2 clock select, 1-CLK_26M, 0-DCO Divided clk_mux */ 27 uint32_t i2c1: 1; /**< bit[2], I2C1 clock select, 1-CLK_26M, 0-DCO Divided clk_mux */ 28 uint32_t irda: 1; /**< bit[3], IRDA clock select, 1-CLK_26M, 0-DCO Divided clk_mux */ 29 uint32_t i2c2: 1; /**< bit[4], I2C2 clock select, 1-CLK_26M, 0-DCO Divided clk_mux */ 30 uint32_t saradc: 1; /**< bit[5], SARADC clock select, 1-CLK_26M, 0-DCO Divided clk_mux */ 31 uint32_t spi: 1; /**< bit[6], SPI clock select, 1-CLK_26M, 0-DCO Divided clk_mux */ 32 uint32_t pwms: 1; /**< bit[7], PWMS clock select, 1-CLK_26M, 0-DCO Divided clk_mux */ 33 uint32_t sdio: 1; /**< bit[8], SDIO clock select, 1-CLK_26M, 0-DCO Divided clk_mux */ 34 uint32_t efuse: 1; /**< bit[9], SARADC clock select Audio PLL, if saradc is 0 */ 35 #if CONFIG_SOC_BK7231N || (CONFIG_SOC_BK7256XX) 36 uint32_t reserved_1: 8; /**< bit[10:17] */ 37 #else 38 uint32_t reserved_1: 6; /**< bit[10:15] */ 39 uint32_t jpeg: 2; /**< bit[16:17] */ 40 #endif 41 uint32_t dco_clk_div: 2; /**< bit[18:19] DCO clock division, 0: 1-div, 1: 2-div, 2: 4-div, 3: 8-div */ 42 uint32_t reserved_2: 12; /**< bit[20:31] */ 43 }; 44 uint32_t v; 45 } peri_clk_mux; 46 47 //reg01 Clock select of pwms 48 union { 49 struct { 50 uint32_t chan0: 1; /**< bit[0], PWM chan0 clock select, 1: LPO_CLK, 0: use clk_mux_pwms */ 51 uint32_t chan1: 1; /**< bit[1], PWM chan0 clock select, 1: LPO_CLK, 0: use clk_mux_pwms */ 52 uint32_t chan2: 1; /**< bit[2], PWM chan0 clock select, 1: LPO_CLK, 0: use clk_mux_pwms */ 53 uint32_t chan3: 1; /**< bit[3], PWM chan0 clock select, 1: LPO_CLK, 0: use clk_mux_pwms */ 54 uint32_t chan4: 1; /**< bit[4], PWM chan0 clock select, 1: LPO_CLK, 0: use clk_mux_pwms */ 55 uint32_t chan5: 1; /**< bit[5], PWM chan0 clock select, 1: LPO_CLK, 0: use clk_mux_pwms */ 56 uint32_t reserved: 26; /**< bit[6:21] */ 57 }; 58 uint32_t v; 59 } pwm_chan_clk_mux; 60 61 //reg02 clock power down for periphral unit 62 union { 63 struct { 64 uint32_t uart1: 1; /**< bit[0], UART1 */ 65 uint32_t uart2: 1; /**< bit[1], UART2 */ 66 uint32_t i2c1: 1; /**< bit[2], I2C1 */ 67 uint32_t irda: 1; /**< bit[3], IRDA */ 68 uint32_t reserved_1: 1; /**< bit[4] */ 69 uint32_t i2c2: 1; /**< bit[5], I2C2 */ 70 uint32_t spi: 1; /**< bit[6], SPI */ 71 uint32_t saradc: 1; /**< bit[7], SARADC */ 72 uint32_t arm_watchdog: 1; /**< bit[8], ARM watchdog */ 73 uint32_t pwm0: 1; /**< bit[9], PWM 0 */ 74 uint32_t pwm1: 1; /**< bit[10], PWM 1 */ 75 uint32_t pwm2: 1; /**< bit[11], PWM 2 */ 76 uint32_t pwm3: 1; /**< bit[12], PWM 3 */ 77 uint32_t pwm4: 1; /**< bit[13], PWM 4 */ 78 uint32_t pwm5: 1; /**< bit[14], PWM 5 */ 79 uint32_t security: 1; /**< bit[15], Security */ 80 uint32_t reserved_2: 1; /**< bit[16] */ 81 uint32_t sdio: 1; /**< bit[17], SDIO */ 82 uint32_t reserved_3: 2; /**< bit[18:19] */ 83 uint32_t timers: 2; /**< bit[20:21], timers */ 84 #if CONFIG_SOC_BK7231N || (CONFIG_SOC_BK7256XX) 85 uint32_t reserved_4: 10; /**< bit[22:31] */ 86 #else 87 uint32_t jpeg: 1; /**< bit[22] jpeg*/ 88 uint32_t reserved_4: 9; /**< bit[23:31] */ 89 #endif 90 }; 91 uint32_t v; 92 } clk_pwr_down; 93 94 //reg03 AHB/APB clock gating disable for periphral unit 95 union { 96 struct { 97 uint32_t icu: 1; /**< bit[0], ICU apb clock gate disable */ 98 uint32_t uart1: 1; /**< bit[1], UART1 apb clock gate disable */ 99 uint32_t uart2: 1; /**< bit[2], UART2 apb clock gate disable */ 100 uint32_t i2c1: 1; /**< bit[3], I2C1 apb clock gate disable */ 101 uint32_t irda: 1; /**< bit[4], IRDA apb clock gate disable */ 102 uint32_t i2s_pcm: 1; /**< bit[5], I2S/PCM apb clock gate disable */ 103 uint32_t i2c2: 1; /**< bit[6], I2C2 apb clock gate disable */ 104 uint32_t spi: 1; /**< bit[7], SPI apb clock gate disable */ 105 uint32_t gpio: 1; /**< bit[8], GPIO apb clock gate disable */ 106 uint32_t watchdog: 1; /**< bit[9], watchdog apb clock gate disable */ 107 uint32_t timers: 1; /**< bit[10], Timers apb clock gate disable */ 108 uint32_t pwms: 1; /**< bit[11], PWMS apb clock gate disable */ 109 uint32_t saradc: 1; /**< bit[12], SARADC apb clock gate disable */ 110 uint32_t sdio: 1; /**< bit[13], SDIO apb clock gate disable */ 111 uint32_t reserved_1: 2; /**< bit[14:15] */ 112 uint32_t mac: 1; /**< bit[16], MAC apb clock gate disable */ 113 114 uint32_t reserved_2: 15; /**< bit[17:31] */ 115 }; 116 uint32_t v; 117 } peri_clk_gate_disable; 118 119 //reg04 120 union { 121 struct { 122 uint32_t reserved_1: 1; /**< bit[0] */ 123 uint32_t ble: 1; /**< bit[1] BLE clock power down */ 124 uint32_t reserved_2: 30; 125 }; 126 uint32_t v; 127 } clk_pwr_down_2; 128 129 //reg05 130 union { 131 struct { 132 uint32_t factor: 2; /**< bit[0:1] 26M clock division factor, 0: 1 division, 1: 2 division, 2: 4 division, 3: 8 division */ 133 uint32_t reserved: 30; 134 }; 135 uint32_t v; 136 } clk26m_div_factor; 137 138 //reg07~reg15 139 uint32_t reserved[16 - 5 - 1]; 140 141 #if CONFIG_SOC_BK7231N || (CONFIG_SOC_BK7256XX) 142 //reg16 143 union { 144 struct { 145 146 //IRQ interrupt enable 147 uint32_t irq_uart1: 1; /**< bit[0] UART1 interrupt */ 148 uint32_t irq_uart2: 1; /**< bit[1] UART2 interrupt */ 149 uint32_t irq_i2c1: 1; /**< bit[2] I2C1 interrupt */ 150 uint32_t irq_irda: 1; /**< bit[3] IRDA interrupt */ 151 uint32_t reserved_1: 1; /**< bit[4] */ 152 uint32_t irq_i2c2: 1; /**< bit[5] I2C2 interrupt */ 153 uint32_t irq_spi: 1; /**< bit[6] GPIO interrupt */ 154 uint32_t irq_gpio: 1; /**< bit[7] GPIO interrupt */ 155 uint32_t irq_timer: 1; /**< bit[8] TIMER interrupt */ 156 uint32_t irq_pwm: 1; /**< bit[9] PWM interrupt */ 157 uint32_t reserved_2: 1; /**< bit[10] */ 158 uint32_t irq_saradc: 1; /**< bit[11] SARADC interrupt */ 159 uint32_t irq_sdio: 1; /**< bit[12] SDIO interrupt */ 160 uint32_t irq_security: 1; /**< bit[13] Security interrupt */ 161 uint32_t irq_la: 1; /**< bit[14] LA interrupt */ 162 uint32_t irq_general_dma: 1; /**< bit[15] general DMA interrupt */ 163 164 //FIQ interrupt enable 165 uint32_t fiq_modem: 1; /**< bit[16] MODEM interrupt */ 166 uint32_t fiq_mac_txrx_timer: 1; /**< bit[17] MAC tx&rx timer interrupt */ 167 uint32_t fiq_mac_txrx_misc: 1; /**< bit[18] MAC tx&rx misc interrupt */ 168 uint32_t fiq_mac_rx_trigger: 1; /**< bit[19] MAC rx trigger interrupt */ 169 uint32_t fiq_mac_tx_trigger: 1; /**< bit[20] MAC tx trigger interrupt */ 170 uint32_t fiq_mac_prot_trigger: 1; /**< bit[21] MAC prot tigger interrupt */ 171 uint32_t fiq_mac_general: 1; /**< bit[22] MAC general interrupt */ 172 uint32_t reserved_3: 3; /**< bit[23:25] */ 173 uint32_t fiq_mac_wakeup: 1; /**< bit[26] MAC wakeup interrupt */ 174 uint32_t reserved_4: 1; /**< bit[27] */ 175 uint32_t fiq_pll_unlock: 1; /**< bit[28] PLL unlock interrupt */ 176 uint32_t fiq_btdm: 1; /**< bit[29] BTDM interrupt */ 177 uint32_t fiq_ble: 1; /**< bit[30] BLE interrupt */ 178 uint32_t fiq_bt: 1; /**< bit[31] BT interrupt */ 179 }; 180 uint32_t v; 181 } int_en; 182 #else 183 //reg16 184 union { 185 struct { 186 187 //IRQ interrupt enable 188 uint32_t irq_uart1: 1; /**< bit[0] UART1 interrupt */ 189 uint32_t irq_uart2: 1; /**< bit[1] UART2 interrupt */ 190 uint32_t irq_i2c1: 1; /**< bit[2] I2C1 interrupt */ 191 uint32_t irq_irda: 1; /**< bit[3] IRDA interrupt */ 192 uint32_t reserved_1: 1; /**< bit[4] */ 193 uint32_t irq_i2c2: 1; /**< bit[5] I2C2 interrupt */ 194 uint32_t irq_spi: 1; /**< bit[6] GPIO interrupt */ 195 uint32_t irq_gpio: 1; /**< bit[7] GPIO interrupt */ 196 uint32_t irq_timer: 1; /**< bit[8] TIMER interrupt */ 197 uint32_t irq_pwm: 1; /**< bit[9] PWM interrupt */ 198 uint32_t irq_jpeg: 1; /**< bit[10] */ 199 uint32_t irq_saradc: 1; /**< bit[11] SARADC interrupt */ 200 uint32_t irq_sdio: 1; /**< bit[12] SDIO interrupt */ 201 uint32_t irq_security: 1; /**< bit[13] Security interrupt */ 202 uint32_t irq_la: 1; /**< bit[14] LA interrupt */ 203 uint32_t irq_general_dma: 1; /**< bit[15] general DMA interrupt */ 204 205 //FIQ interrupt enable 206 uint32_t fiq_modem_rc: 1; /**< bit[16] bk7236 MODEM RC interrupt */ 207 uint32_t fiq_modem: 1; /**< bit[17] MODEM interrupt */ 208 uint32_t fiq_mac_txrx_timer: 1; /**< bit[18] MAC tx&rx timer interrupt */ 209 uint32_t fiq_mac_txrx_misc: 1; /**< bit[19] MAC tx&rx misc interrupt */ 210 uint32_t fiq_mac_rx_trigger: 1; /**< bit[20] MAC rx trigger interrupt */ 211 uint32_t fiq_mac_tx_trigger: 1; /**< bit[221] MAC tx trigger interrupt */ 212 uint32_t fiq_mac_prot_trigger: 1; /**< bit[22] MAC prot tigger interrupt */ 213 uint32_t fiq_mac_general: 1; /**< bit[23] MAC general interrupt */ 214 uint32_t fiq_mac_hsu: 1; /**< bit[24] MAC hsu interrupt */ 215 uint32_t reserved_2: 1; /**< bit[25] */ 216 uint32_t fiq_mac_wakeup: 1; /**< bit[26] MAC wakeup interrupt */ 217 uint32_t reserved_4: 1; /**< bit[27] */ 218 uint32_t fiq_pll_unlock: 1; /**< bit[28] PLL unlock interrupt */ 219 uint32_t fiq_btdm: 1; /**< bit[29] BTDM interrupt */ 220 uint32_t fiq_ble: 1; /**< bit[30] BLE interrupt */ 221 uint32_t fiq_bt: 1; /**< bit[31] BT interrupt */ 222 }; 223 uint32_t v; 224 } int_en; 225 226 #endif 227 //reg17 228 union { 229 struct { 230 uint32_t irq_en: 1; /**< bit[0] IRQ global enable */ 231 uint32_t fiq_en: 1; /**< bit[1] FIQ global enable */ 232 233 uint32_t reserved: 30; 234 }; 235 uint32_t v; 236 } int_global_en; 237 238 #if CONFIG_SOC_BK7231N || (CONFIG_SOC_BK7256XX) 239 //reg18 interrupt status (before mask) 240 union { 241 struct { 242 //IRQ interrupt status 243 uint32_t irq_uart1: 1; /**< bit[0] UART1 interrupt */ 244 uint32_t irq_uart2: 1; /**< bit[1] UART2 interrupt */ 245 uint32_t irq_i2c1: 1; /**< bit[2] I2C1 interrupt */ 246 uint32_t irq_irda: 1; /**< bit[3] IRDA interrupt */ 247 uint32_t reserved_1: 1; /**< bit[4] */ 248 uint32_t irq_i2c2: 1; /**< bit[5] I2C2 interrupt */ 249 uint32_t irq_spi: 1; /**< bit[6] GPIO interrupt */ 250 uint32_t irq_gpio: 1; /**< bit[7] GPIO interrupt */ 251 uint32_t irq_timer: 1; /**< bit[8] TIMER interrupt */ 252 uint32_t irq_pwm: 1; /**< bit[9] PWM interrupt */ 253 uint32_t reserved_2: 1; /**< bit[10] */ 254 uint32_t irq_saradc: 1; /**< bit[11] SARADC interrupt */ 255 uint32_t irq_sdio: 1; /**< bit[12] SDIO interrupt */ 256 uint32_t irq_security: 1; /**< bit[13] Security interrupt */ 257 uint32_t irq_la: 1; /**< bit[14] LA interrupt */ 258 uint32_t irq_general_dma: 1; /**< bit[15] general DMA interrupt */ 259 260 //FIQ interrupt enable 261 uint32_t fiq_modem: 1; /**< bit[16] MODEM interrupt */ 262 uint32_t fiq_mac_txrx_timer: 1; /**< bit[17] MAC tx&rx timer interrupt */ 263 uint32_t fiq_mac_txrx_misc: 1; /**< bit[18] MAC tx&rx misc interrupt */ 264 uint32_t fiq_mac_rx_trigger: 1; /**< bit[19] MAC rx trigger interrupt */ 265 uint32_t fiq_mac_tx_trigger: 1; /**< bit[20] MAC tx trigger interrupt */ 266 uint32_t fiq_mac_prot_trigger: 1; /**< bit[21] MAC prot tigger interrupt */ 267 uint32_t fiq_mac_general: 1; /**< bit[22] MAC general interrupt */ 268 uint32_t reserved_3: 3; /**< bit[23:25] */ 269 uint32_t fiq_mac_wakeup: 1; /**< bit[26] MAC wakeup interrupt */ 270 uint32_t reserved_4: 1; /**< bit[27] */ 271 uint32_t fiq_pll_unlock: 1; /**< bit[28] PLL unlock interrupt */ 272 uint32_t fiq_btdm: 1; /**< bit[29] BTDM interrupt */ 273 uint32_t fiq_ble: 1; /**< bit[30] BLE interrupt */ 274 uint32_t fiq_bt: 1; /**< bit[31] BT interrupt */ 275 276 }; 277 278 uint32_t v; 279 } int_raw_status; 280 281 //reg19 interrupt status (after mask) 282 union { 283 struct { 284 //interrupt status 285 uint32_t irq_uart1: 1; /**< bit[0] UART1 interrupt */ 286 uint32_t irq_uart2: 1; /**< bit[1] UART2 interrupt */ 287 uint32_t irq_i2c1: 1; /**< bit[2] I2C1 interrupt */ 288 uint32_t irq_irda: 1; /**< bit[3] IRDA interrupt */ 289 uint32_t reserved_1: 1; /**< bit[4] */ 290 uint32_t irq_i2c2: 1; /**< bit[5] I2C2 interrupt */ 291 uint32_t irq_spi: 1; /**< bit[6] GPIO interrupt */ 292 uint32_t irq_gpio: 1; /**< bit[7] GPIO interrupt */ 293 uint32_t irq_timer: 1; /**< bit[8] TIMER interrupt */ 294 uint32_t irq_pwm: 1; /**< bit[9] PWM interrupt */ 295 uint32_t reserved_2: 1; /**< bit[10] */ 296 uint32_t irq_saradc: 1; /**< bit[11] SARADC interrupt */ 297 uint32_t irq_sdio: 1; /**< bit[12] SDIO interrupt */ 298 uint32_t irq_security: 1; /**< bit[13] Security interrupt */ 299 uint32_t irq_la: 1; /**< bit[14] LA interrupt */ 300 uint32_t irq_general_dma: 1; /**< bit[15] general DMA interrupt */ 301 302 //FIQ interrupt enable 303 uint32_t fiq_modem: 1; /**< bit[16] MODEM interrupt */ 304 uint32_t fiq_mac_txrx_timer: 1; /**< bit[17] MAC tx&rx timer interrupt */ 305 uint32_t fiq_mac_txrx_misc: 1; /**< bit[18] MAC tx&rx misc interrupt */ 306 uint32_t fiq_mac_rx_trigger: 1; /**< bit[19] MAC rx trigger interrupt */ 307 uint32_t fiq_mac_tx_trigger: 1; /**< bit[20] MAC tx trigger interrupt */ 308 uint32_t fiq_mac_prot_trigger: 1; /**< bit[21] MAC prot tigger interrupt */ 309 uint32_t fiq_mac_general: 1; /**< bit[22] MAC general interrupt */ 310 uint32_t reserved_3: 3; /**< bit[23:25] */ 311 uint32_t fiq_mac_wakeup: 1; /**< bit[26] MAC wakeup interrupt */ 312 uint32_t reserved_4: 1; /**< bit[27] */ 313 uint32_t fiq_pll_unlock: 1; /**< bit[28] PLL unlock interrupt */ 314 uint32_t fiq_btdm: 1; /**< bit[29] BTDM interrupt */ 315 uint32_t fiq_ble: 1; /**< bit[30] BLE interrupt */ 316 uint32_t fiq_bt: 1; /**< bit[31] BT interrupt */ 317 }; 318 319 uint32_t v; 320 } int_status; 321 322 #else 323 //reg18 interrupt status (before mask) 324 union { 325 struct { 326 //IRQ interrupt status 327 uint32_t irq_uart1: 1; /**< bit[0] UART1 interrupt */ 328 uint32_t irq_uart2: 1; /**< bit[1] UART2 interrupt */ 329 uint32_t irq_i2c1: 1; /**< bit[2] I2C1 interrupt */ 330 uint32_t irq_irda: 1; /**< bit[3] IRDA interrupt */ 331 uint32_t reserved_1: 1; /**< bit[4] */ 332 uint32_t irq_i2c2: 1; /**< bit[5] I2C2 interrupt */ 333 uint32_t irq_spi: 1; /**< bit[6] GPIO interrupt */ 334 uint32_t irq_gpio: 1; /**< bit[7] GPIO interrupt */ 335 uint32_t irq_timer: 1; /**< bit[8] TIMER interrupt */ 336 uint32_t irq_pwm: 1; /**< bit[9] PWM interrupt */ 337 uint32_t irq_jpeg: 1; /**< bit[10] */ 338 uint32_t irq_saradc: 1; /**< bit[11] SARADC interrupt */ 339 uint32_t irq_sdio: 1; /**< bit[12] SDIO interrupt */ 340 uint32_t irq_security: 1; /**< bit[13] Security interrupt */ 341 uint32_t irq_la: 1; /**< bit[14] LA interrupt */ 342 uint32_t irq_general_dma: 1; /**< bit[15] general DMA interrupt */ 343 344 //FIQ interrupt enable 345 uint32_t fiq_modem_rc: 1; /**< bit[16] bk7236 MODEM RC interrupt */ 346 uint32_t fiq_modem: 1; /**< bit[17] MODEM interrupt */ 347 uint32_t fiq_mac_txrx_timer: 1; /**< bit[18] MAC tx&rx timer interrupt */ 348 uint32_t fiq_mac_txrx_misc: 1; /**< bit[19] MAC tx&rx misc interrupt */ 349 uint32_t fiq_mac_rx_trigger: 1; /**< bit[20] MAC rx trigger interrupt */ 350 uint32_t fiq_mac_tx_trigger: 1; /**< bit[221] MAC tx trigger interrupt */ 351 uint32_t fiq_mac_prot_trigger: 1; /**< bit[22] MAC prot tigger interrupt */ 352 uint32_t fiq_mac_general: 1; /**< bit[23] MAC general interrupt */ 353 uint32_t fiq_mac_hsu: 1; /**< bit[24] MAC hsu interrupt */ 354 uint32_t reserved_2: 1; /**< bit[25] */ 355 uint32_t fiq_mac_wakeup: 1; /**< bit[26] MAC wakeup interrupt */ 356 uint32_t reserved_4: 1; /**< bit[27] */ 357 uint32_t fiq_pll_unlock: 1; /**< bit[28] PLL unlock interrupt */ 358 uint32_t fiq_btdm: 1; /**< bit[29] BTDM interrupt */ 359 uint32_t fiq_ble: 1; /**< bit[30] BLE interrupt */ 360 uint32_t fiq_bt: 1; /**< bit[31] BT interrupt */ 361 }; 362 363 uint32_t v; 364 } int_raw_status; 365 366 //reg19 interrupt status (after mask) 367 union { 368 struct { 369 //interrupt status 370 uint32_t irq_uart1: 1; /**< bit[0] UART1 interrupt */ 371 uint32_t irq_uart2: 1; /**< bit[1] UART2 interrupt */ 372 uint32_t irq_i2c1: 1; /**< bit[2] I2C1 interrupt */ 373 uint32_t irq_irda: 1; /**< bit[3] IRDA interrupt */ 374 uint32_t reserved_1: 1; /**< bit[4] */ 375 uint32_t irq_i2c2: 1; /**< bit[5] I2C2 interrupt */ 376 uint32_t irq_spi: 1; /**< bit[6] GPIO interrupt */ 377 uint32_t irq_gpio: 1; /**< bit[7] GPIO interrupt */ 378 uint32_t irq_timer: 1; /**< bit[8] TIMER interrupt */ 379 uint32_t irq_pwm: 1; /**< bit[9] PWM interrupt */ 380 uint32_t irq_jpeg: 1; /**< bit[10] */ 381 uint32_t irq_saradc: 1; /**< bit[11] SARADC interrupt */ 382 uint32_t irq_sdio: 1; /**< bit[12] SDIO interrupt */ 383 uint32_t irq_security: 1; /**< bit[13] Security interrupt */ 384 uint32_t irq_la: 1; /**< bit[14] LA interrupt */ 385 uint32_t irq_general_dma: 1; /**< bit[15] general DMA interrupt */ 386 387 //FIQ interrupt enable 388 uint32_t fiq_modem_rc: 1; /**< bit[16] bk7236 MODEM RC interrupt */ 389 uint32_t fiq_modem: 1; /**< bit[17] MODEM interrupt */ 390 uint32_t fiq_mac_txrx_timer: 1; /**< bit[18] MAC tx&rx timer interrupt */ 391 uint32_t fiq_mac_txrx_misc: 1; /**< bit[19] MAC tx&rx misc interrupt */ 392 uint32_t fiq_mac_rx_trigger: 1; /**< bit[20] MAC rx trigger interrupt */ 393 uint32_t fiq_mac_tx_trigger: 1; /**< bit[221] MAC tx trigger interrupt */ 394 uint32_t fiq_mac_prot_trigger: 1; /**< bit[22] MAC prot tigger interrupt */ 395 uint32_t fiq_mac_general: 1; /**< bit[23] MAC general interrupt */ 396 uint32_t fiq_mac_hsu: 1; /**< bit[24] MAC hsu interrupt */ 397 uint32_t reserved_2: 1; /**< bit[25] */ 398 uint32_t fiq_mac_wakeup: 1; /**< bit[26] MAC wakeup interrupt */ 399 uint32_t reserved_4: 1; /**< bit[27] */ 400 uint32_t fiq_pll_unlock: 1; /**< bit[28] PLL unlock interrupt */ 401 uint32_t fiq_btdm: 1; /**< bit[29] BTDM interrupt */ 402 uint32_t fiq_ble: 1; /**< bit[30] BLE interrupt */ 403 uint32_t fiq_bt: 1; /**< bit[31] BT interrupt */ 404 }; 405 406 uint32_t v; 407 } int_status; 408 #endif 409 //reg20 ARM wakeup enable 410 union { 411 struct { 412 uint32_t uart1: 1; /**<bit[0], UART1 wakeup */ 413 uint32_t uart2: 1; /**<bit[1], UART2 wakeup */ 414 uint32_t i2c1: 1; /**<bit[2], I2C1 wakeup */ 415 uint32_t irda: 1; /**<bit[3], IRDA wakeup */ 416 uint32_t reserved_1: 1; /**<bit[4] */ 417 uint32_t i2c2: 1; /**<bit[5], I2C2 wakeup */ 418 uint32_t spi: 1; /**<bit[6], SPI wakeup */ 419 uint32_t gpio: 1; /**<bit[7], GPIO wakeup */ 420 uint32_t timer: 1; /**<bit[8], TIMER wakeup */ 421 uint32_t pwm: 1; /**<bit[9], PWM wakeup */ 422 uint32_t reserved_2: 1; /**<bit[10] */ 423 uint32_t saradc: 1; /**<bit[11], SARADC wakeup */ 424 uint32_t sdio: 1; /**<bit[12], SDIO wakeup */ 425 uint32_t security: 1; /**<bit[13], Security wakeup */ 426 uint32_t la: 1; /**<bit[14], LA wakeup */ 427 uint32_t general_dma: 1; /**<bit[15], general DMA wakeup */ 428 uint32_t modem: 1; /**<bit[16], modem wakeup */ 429 uint32_t mac_tx_rx_timer: 1; /**<bit[17], MAC tx&rx timer wakeup */ 430 uint32_t mac_tx_rx_misc: 1; /**<bit[18], MAC tx&rx misc wakeup */ 431 uint32_t mac_rx_trigger: 1; /**<bit[19], MAC rx trigger wakeup */ 432 uint32_t mac_tx_trigger: 1; /**<bit[20], MAC TX trigger wakeup */ 433 uint32_t mac_prot_trigger: 1; /**<bit[21], MAC prot trigger wakeup */ 434 uint32_t mac_general: 1; /**<bit[22], MAC general wakeup */ 435 uint32_t reserved_3: 3; /**<bit[23:25] */ 436 uint32_t mac: 1; /**<bit[26], MAC wakeup */ 437 uint32_t reserved_4: 1; /**<bit[27] */ 438 uint32_t pll_unlock: 1; /**<bit[28], PLL unlock wakeup */ 439 uint32_t btdm: 1; /**<bit[29], BTDM general wakeup */ 440 uint32_t ble: 1; /**<bit[30], BLE wakeup */ 441 uint32_t bt: 1; /**<bit[31], BT wakeup */ 442 }; 443 uint32_t v; 444 } arm_wakeup_en; 445 } icu_hw_t; 446 447 #ifdef __cplusplus 448 } 449 #endif 450