1 /*
2 *
3 * SPDX-License-Identifier: GPL-2.0
4 *
5 * Copyright (C) 2011-2018 ARM or its affiliates
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
17 *
18 */
19
20 #include <linux/version.h>
21 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 19, 0))
22 #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 12, 0))
23 #ifndef CONFIG_SET_FS
24 #define CONFIG_SET_FS 1
25 #endif
26 #endif
27 #ifndef CONFIG_THREAD_INFO_IN_TASK
28 #define CONFIG_THREAD_INFO_IN_TASK 1
29 #endif
30 #include <linux/thread_info.h>
31 #include <linux/sched.h>
32 #endif
33
34 #include <linux/kernel.h>
35 #include <asm/uaccess.h>
36 #include <linux/gfp.h>
37 #include <linux/cdev.h>
38 #include <linux/slab.h>
39 #include <asm/types.h>
40 #include <asm/io.h>
41 #include <linux/time.h>
42 #include <linux/delay.h>
43 #include "acamera_types.h"
44 #include "acamera_logger.h"
45 #include "system_autowrite.h"
46
47 static void *p_hw_fr_base = NULL;
48 static void *p_hw_ds1_base = NULL;
49 static void *p_hw_ds2_base = NULL;
50
auto_cap_init(void)51 void auto_cap_init(void)
52 {
53 p_hw_fr_base = ioremap(FR_AUTO_WRITE_BASE, 0x80);
54 p_hw_ds1_base = ioremap(DS1_AUTO_WRITE_BASE, 0x80);
55 p_hw_ds2_base = ioremap(DS2_AUTO_WRITE_BASE, 0x80);
56 }
57
auto_cap_deinit(void)58 void auto_cap_deinit(void)
59 {
60 iounmap( p_hw_fr_base );
61 iounmap( p_hw_ds1_base );
62 iounmap( p_hw_ds2_base );
63 }
64
autowrite_fr_ping_start(void)65 uint32_t autowrite_fr_ping_start( void )
66 {
67 uint32_t result = 0;
68
69 if ( p_hw_fr_base != NULL ) {
70 result = ioread32( p_hw_fr_base + MIPI_BL_PING_ADDR0_ST );
71 }
72
73 return result;
74 }
75
autowrite_fr_pong_start(void)76 uint32_t autowrite_fr_pong_start( void )
77 {
78 uint32_t result = 0;
79
80 if ( p_hw_fr_base != NULL ) {
81 result = ioread32( p_hw_fr_base + MIPI_BL_PONG_ADDR0_ST );
82 }
83
84 return result;
85 }
86
autowrite_fr_image_buffer_stride_read(void)87 uint32_t autowrite_fr_image_buffer_stride_read( void )
88 {
89 uint32_t result = 0;
90
91 if ( p_hw_fr_base != NULL ) {
92 result = ioread32( p_hw_fr_base + MIPI_BL_FRAME_SIZE0 );
93 }
94
95 return result;
96 }
97
autowrite_fr_image_buffer_stride_read1(void)98 uint32_t autowrite_fr_image_buffer_stride_read1( void )
99 {
100 uint32_t result = 0;
101
102 if ( p_hw_fr_base != NULL ) {
103 result = ioread32( p_hw_fr_base + MIPI_BL_FRAME_SIZE1 );
104 }
105
106 return result;
107 }
108
autowrite_fr_writer_frame_wcount_read(void)109 uint32_t autowrite_fr_writer_frame_wcount_read( void )
110 {
111 uint32_t result = 0;
112
113 if ( p_hw_fr_base != NULL ) {
114 result = ioread32( p_hw_fr_base + MIPI_BL_COUNT );
115 }
116
117 return result;
118 }
119
autowrite_fr_writer_memsize_read(void)120 uint32_t autowrite_fr_writer_memsize_read( void )
121 {
122 uint32_t result = 0;
123
124 if ( p_hw_fr_base != NULL ) {
125 result = ioread32( p_hw_fr_base + MIPI_BL_FRAME_BUF_SIZE0 );
126 }
127
128 return result;
129 }
130
autowrite_fr_writer_memsize_read1(void)131 uint32_t autowrite_fr_writer_memsize_read1( void )
132 {
133 uint32_t result = 0;
134
135 if ( p_hw_fr_base != NULL ) {
136 result = ioread32( p_hw_fr_base + MIPI_BL_FRAME_BUF_SIZE1 );
137 }
138
139 return result;
140 }
141
autowrite_fr_drop_jump_read(void)142 uint32_t autowrite_fr_drop_jump_read( void )
143 {
144 uint32_t result = 0;
145
146 if ( p_hw_fr_base != NULL ) {
147 result = (ioread32( p_hw_fr_base + MIPI_BL_CTRL1 ) & 0xFF0000) >> 16;
148 }
149
150 return result;
151 }
152
autowrite_fr_drop_write_read(void)153 uint32_t autowrite_fr_drop_write_read( void )
154 {
155 uint32_t result = 0;
156
157 if ( p_hw_fr_base != NULL ) {
158 result = (ioread32( p_hw_fr_base + MIPI_BL_CTRL1 ) & 0xFF00) >> 8;
159 }
160
161 return result;
162 }
163
autowrite_fr_drop_mode_status(void)164 uint32_t autowrite_fr_drop_mode_status( void )
165 {
166 uint32_t result = 0;
167
168 if ( p_hw_fr_base != NULL ) {
169 result = (ioread32( p_hw_fr_base + MIPI_BL_CTRL0 ) & (1 << 5));
170 }
171
172 return result;
173 }
174
autowrite_ds1_ping_start(void)175 uint32_t autowrite_ds1_ping_start( void )
176 {
177 uint32_t result = 0;
178
179 if ( p_hw_ds1_base != NULL ) {
180 result = ioread32( p_hw_ds1_base + MIPI_BL_PING_ADDR0_ST );
181 }
182
183 return result;
184 }
185
autowrite_ds1_pong_start(void)186 uint32_t autowrite_ds1_pong_start( void )
187 {
188 uint32_t result = 0;
189
190 if ( p_hw_ds1_base != NULL ) {
191 result = ioread32( p_hw_ds1_base + MIPI_BL_PONG_ADDR0_ST );
192 }
193
194 return result;
195 }
196
autowrite_ds1_image_buffer_stride_read(void)197 uint32_t autowrite_ds1_image_buffer_stride_read( void )
198 {
199 uint32_t result = 0;
200
201 if ( p_hw_ds1_base != NULL ) {
202 result = ioread32( p_hw_ds1_base + MIPI_BL_FRAME_SIZE0 );
203 }
204
205 return result;
206 }
207
autowrite_ds1_image_buffer_stride_read1(void)208 uint32_t autowrite_ds1_image_buffer_stride_read1( void )
209 {
210 uint32_t result = 0;
211
212 if ( p_hw_ds1_base != NULL ) {
213 result = ioread32( p_hw_ds1_base + MIPI_BL_FRAME_SIZE1 );
214 }
215
216 return result;
217 }
218
autowrite_ds1_writer_frame_wcount_read(void)219 uint32_t autowrite_ds1_writer_frame_wcount_read( void )
220 {
221 uint32_t result = 0;
222
223 if ( p_hw_ds1_base != NULL ) {
224 result = ioread32( p_hw_ds1_base + MIPI_BL_COUNT );
225 }
226
227 return result;
228 }
229
autowrite_ds1_writer_memsize_read(void)230 uint32_t autowrite_ds1_writer_memsize_read( void )
231 {
232 uint32_t result = 0;
233
234 if ( p_hw_ds1_base != NULL ) {
235 result = ioread32( p_hw_ds1_base + MIPI_BL_FRAME_BUF_SIZE0 );
236 }
237
238 return result;
239 }
240
autowrite_ds1_writer_memsize_read1(void)241 uint32_t autowrite_ds1_writer_memsize_read1( void )
242 {
243 uint32_t result = 0;
244
245 if ( p_hw_ds1_base != NULL ) {
246 result = ioread32( p_hw_ds1_base + MIPI_BL_FRAME_BUF_SIZE1 );
247 }
248
249 return result;
250 }
251
autowrite_ds1_drop_jump_read(void)252 uint32_t autowrite_ds1_drop_jump_read( void )
253 {
254 uint32_t result = 0;
255
256 if ( p_hw_ds1_base != NULL ) {
257 result = (ioread32( p_hw_ds1_base + MIPI_BL_CTRL1 ) & 0xFF0000) >> 16;
258 }
259
260 return result;
261 }
262
autowrite_ds1_drop_write_read(void)263 uint32_t autowrite_ds1_drop_write_read( void )
264 {
265 uint32_t result = 0;
266
267 if ( p_hw_ds1_base != NULL ) {
268 result = (ioread32( p_hw_ds1_base + MIPI_BL_CTRL1 ) & 0xFF00) >> 8;
269 }
270
271 return result;
272 }
273
autowrite_ds1_drop_mode_status(void)274 uint32_t autowrite_ds1_drop_mode_status( void )
275 {
276 uint32_t result = 0;
277
278 if ( p_hw_ds1_base != NULL ) {
279 result = (ioread32( p_hw_ds1_base + MIPI_BL_CTRL0 ) & (1 << 5));
280 }
281
282 return result;
283 }
284
autowrite_ds2_ping_start(void)285 uint32_t autowrite_ds2_ping_start( void )
286 {
287 uint32_t result = 0;
288
289 if ( p_hw_ds2_base != NULL ) {
290 result = ioread32( p_hw_ds2_base + MIPI_BL_PING_ADDR0_ST );
291 }
292
293 return result;
294 }
295
autowrite_ds2_pong_start(void)296 uint32_t autowrite_ds2_pong_start( void )
297 {
298 uint32_t result = 0;
299
300 if ( p_hw_ds2_base != NULL ) {
301 result = ioread32( p_hw_ds2_base + MIPI_BL_PONG_ADDR0_ST );
302 }
303
304 return result;
305 }
306
autowrite_ds2_image_buffer_stride_read(void)307 uint32_t autowrite_ds2_image_buffer_stride_read( void )
308 {
309 uint32_t result = 0;
310
311 if ( p_hw_ds2_base != NULL ) {
312 result = ioread32( p_hw_ds2_base + MIPI_BL_FRAME_SIZE0 );
313 }
314
315 return result;
316 }
317
autowrite_ds2_image_buffer_stride_read1(void)318 uint32_t autowrite_ds2_image_buffer_stride_read1( void )
319 {
320 uint32_t result = 0;
321
322 if ( p_hw_ds2_base != NULL ) {
323 result = ioread32( p_hw_ds2_base + MIPI_BL_FRAME_SIZE1 );
324 }
325
326 return result;
327 }
328
autowrite_ds2_writer_frame_wcount_read(void)329 uint32_t autowrite_ds2_writer_frame_wcount_read( void )
330 {
331 uint32_t result = 0;
332
333 if ( p_hw_ds2_base != NULL ) {
334 result = ioread32( p_hw_ds2_base + MIPI_BL_COUNT );
335 }
336
337 return result;
338 }
339
autowrite_ds2_writer_memsize_read(void)340 uint32_t autowrite_ds2_writer_memsize_read( void )
341 {
342 uint32_t result = 0;
343
344 if ( p_hw_ds2_base != NULL ) {
345 result = ioread32( p_hw_ds2_base + MIPI_BL_FRAME_BUF_SIZE0 );
346 }
347
348 return result;
349 }
350
autowrite_ds2_writer_memsize_read1(void)351 uint32_t autowrite_ds2_writer_memsize_read1( void )
352 {
353 uint32_t result = 0;
354
355 if ( p_hw_ds2_base != NULL ) {
356 result = ioread32( p_hw_ds2_base + MIPI_BL_FRAME_BUF_SIZE1 );
357 }
358
359 return result;
360 }
361
autowrite_ds2_drop_jump_read(void)362 uint32_t autowrite_ds2_drop_jump_read( void )
363 {
364 uint32_t result = 0;
365
366 if ( p_hw_ds2_base != NULL ) {
367 result = (ioread32( p_hw_ds2_base + MIPI_BL_CTRL1 ) & 0xFF0000) >> 16;
368 }
369
370 return result;
371 }
372
autowrite_ds2_drop_write_read(void)373 uint32_t autowrite_ds2_drop_write_read( void )
374 {
375 uint32_t result = 0;
376
377 if ( p_hw_ds2_base != NULL ) {
378 result = (ioread32( p_hw_ds2_base + MIPI_BL_CTRL1 ) & 0xFF00) >> 8;
379 }
380
381 return result;
382 }
383
autowrite_ds2_drop_mode_status(void)384 uint32_t autowrite_ds2_drop_mode_status( void )
385 {
386 uint32_t result = 0;
387
388 if ( p_hw_ds2_base != NULL ) {
389 result = (ioread32( p_hw_ds2_base + MIPI_BL_CTRL0 ) & (1 << 5));
390 }
391
392 return result;
393 }
394
autowrite_fr_start_address_read(void)395 uint32_t autowrite_fr_start_address_read( void )
396 {
397 uint32_t result = 0;
398
399 if ( p_hw_fr_base != NULL ) {
400 result = ioread32( p_hw_fr_base + MIPI_BL_FRAME_BUFFER_START_ADDR0 );
401 }
402
403 return result;
404 }
405
autowrite_ds1_start_address_read(void)406 uint32_t autowrite_ds1_start_address_read( void )
407 {
408 uint32_t result = 0;
409
410 if ( p_hw_ds1_base != NULL ) {
411 result = ioread32( p_hw_ds1_base + MIPI_BL_FRAME_BUFFER_START_ADDR0 );
412 }
413
414 return result;
415 }
416
autowrite_ds2_start_address_read(void)417 uint32_t autowrite_ds2_start_address_read( void )
418 {
419 uint32_t result = 0;
420
421 if ( p_hw_ds2_base != NULL ) {
422 result = ioread32( p_hw_ds2_base + MIPI_BL_FRAME_BUFFER_START_ADDR0 );
423 }
424
425 return result;
426 }
427
autowrite_fr_stop(void)428 uint32_t autowrite_fr_stop( void )
429 {
430 uint32_t result = 0;
431 uint32_t val = 0;
432
433 if ( p_hw_fr_base != NULL ) {
434 val = ioread32( p_hw_fr_base + MIPI_BL_CTRL0);
435 val = val | (0x1 << 4);
436 void *ptr = (void *)( p_hw_fr_base + MIPI_BL_CTRL0 );
437 iowrite32(val, ptr); // ladder stop next frame
438
439 //val = read_reg(base_addr + MIPI_BL_CTRL0);
440 //val = val & (~(1 << 13)) & (~(1 << 0));
441 //write_reg(val, base_addr + MIPI_BL_CTRL0); // ladder disable
442 }
443
444 return result;
445 }
446
autowrite_ds1_stop(void)447 uint32_t autowrite_ds1_stop( void )
448 {
449 uint32_t result = 0;
450 uint32_t val = 0;
451
452 if ( p_hw_ds1_base != NULL ) {
453 val = ioread32( p_hw_ds1_base + MIPI_BL_CTRL0);
454 val = val | (0x1 << 4);
455 void *ptr = (void *)( p_hw_ds1_base + MIPI_BL_CTRL0 );
456 iowrite32(val, ptr); // ladder stop next frame
457
458 //val = read_reg(base_addr + MIPI_BL_CTRL0);
459 //val = val & (~(1 << 13)) & (~(1 << 0));
460 //write_reg(val, base_addr + MIPI_BL_CTRL0); // ladder disable
461 }
462
463 return result;
464 }
465
autowrite_ds2_stop(void)466 uint32_t autowrite_ds2_stop( void )
467 {
468 uint32_t result = 0;
469 uint32_t val = 0;
470
471 if ( p_hw_ds2_base != NULL ) {
472 val = ioread32( p_hw_ds2_base + MIPI_BL_CTRL0);
473 val = val | (0x1 << 4);
474 void *ptr = (void *)( p_hw_ds2_base + MIPI_BL_CTRL0 );
475 iowrite32(val, ptr); // ladder stop next frame
476
477 //val = read_reg(base_addr + MIPI_BL_CTRL0);
478 //val = val & (~(1 << 13)) & (~(1 << 0));
479 //write_reg(val, base_addr + MIPI_BL_CTRL0); // ladder disable
480 }
481
482 return result;
483 }
484
485 /*****************************************************************/
auto_write_fr_cfg_buff(void * cfg)486 static void auto_write_fr_cfg_buff(void *cfg)
487 {
488 auto_write_cfg_t *a_cfg = NULL;
489
490 if (cfg == NULL) {
491 LOG(LOG_ERR, "Error input param");
492 return;
493 }
494
495 a_cfg = cfg;
496
497 iowrite32(0x00000000, p_hw_fr_base + MIPI_BL_FRAME_TH);
498 iowrite32(a_cfg->frame_buffer_start0, p_hw_fr_base + MIPI_BL_FRAME_BUFFER_START_ADDR0P);
499 iowrite32(a_cfg->frame_buffer_start0, p_hw_fr_base + MIPI_BL_FRAME_BUFFER_START_ADDR0);
500 iowrite32(a_cfg->frame_size0, p_hw_fr_base + MIPI_BL_FRAME_SIZE0);
501 iowrite32(a_cfg->frame_buffer_size0, p_hw_fr_base + MIPI_BL_FRAME_BUF_SIZE0);
502 iowrite32(a_cfg->frame_buffer_start1, p_hw_fr_base + MIPI_BL_FRAME_BUFFER_START_ADDR1);
503 iowrite32(a_cfg->frame_size1, p_hw_fr_base + MIPI_BL_FRAME_SIZE1);
504 iowrite32(a_cfg->frame_buffer_size1, p_hw_fr_base + MIPI_BL_FRAME_BUF_SIZE1);
505 }
506
auto_write_ds1_cfg_buff(void * cfg)507 static void auto_write_ds1_cfg_buff(void *cfg)
508 {
509 auto_write_cfg_t *a_cfg = NULL;
510
511 if (cfg == NULL) {
512 LOG(LOG_ERR, "Error input param");
513 return;
514 }
515
516 a_cfg = cfg;
517
518 iowrite32(0x00000000, p_hw_ds1_base + MIPI_BL_FRAME_TH);
519 iowrite32(a_cfg->frame_buffer_start0, p_hw_ds1_base + MIPI_BL_FRAME_BUFFER_START_ADDR0P);
520 iowrite32(a_cfg->frame_buffer_start0, p_hw_ds1_base + MIPI_BL_FRAME_BUFFER_START_ADDR0);
521 iowrite32(a_cfg->frame_size0, p_hw_ds1_base + MIPI_BL_FRAME_SIZE0);
522 iowrite32(a_cfg->frame_buffer_size0, p_hw_ds1_base + MIPI_BL_FRAME_BUF_SIZE0);
523 iowrite32(a_cfg->frame_buffer_start1, p_hw_ds1_base + MIPI_BL_FRAME_BUFFER_START_ADDR1);
524 iowrite32(a_cfg->frame_size1, p_hw_ds1_base + MIPI_BL_FRAME_SIZE1);
525 iowrite32(a_cfg->frame_buffer_size1, p_hw_ds1_base + MIPI_BL_FRAME_BUF_SIZE1);
526 }
527
auto_write_ds2_cfg_buff(void * cfg)528 static void auto_write_ds2_cfg_buff(void *cfg)
529 {
530 auto_write_cfg_t *a_cfg = NULL;
531
532 if (cfg == NULL) {
533 LOG(LOG_ERR, "Error input param");
534 return;
535 }
536
537 a_cfg = cfg;
538
539 iowrite32(0x00000000, p_hw_ds2_base + MIPI_BL_FRAME_TH);
540 iowrite32(a_cfg->frame_buffer_start0, p_hw_ds2_base + MIPI_BL_FRAME_BUFFER_START_ADDR0P);
541 iowrite32(a_cfg->frame_buffer_start0, p_hw_ds2_base + MIPI_BL_FRAME_BUFFER_START_ADDR0);
542 iowrite32(a_cfg->frame_size0, p_hw_ds2_base + MIPI_BL_FRAME_SIZE0);
543 iowrite32(a_cfg->frame_buffer_size0, p_hw_ds2_base + MIPI_BL_FRAME_BUF_SIZE0);
544 iowrite32(a_cfg->frame_buffer_start1, p_hw_ds2_base + MIPI_BL_FRAME_BUFFER_START_ADDR1);
545 iowrite32(a_cfg->frame_size1, p_hw_ds2_base + MIPI_BL_FRAME_SIZE1);
546 iowrite32(a_cfg->frame_buffer_size1, p_hw_ds2_base + MIPI_BL_FRAME_BUF_SIZE1);
547 }
548
auto_write_fr_reset(uint32_t p_type)549 static void auto_write_fr_reset(uint32_t p_type)
550 {
551 iowrite32(1 << 15, p_hw_fr_base + MIPI_BL_CTRL0);
552 mdelay(1);
553 iowrite32(0 << 15, p_hw_fr_base + MIPI_BL_CTRL0);
554 }
555
auto_write_ds1_reset(uint32_t p_type)556 static void auto_write_ds1_reset(uint32_t p_type)
557 {
558 iowrite32(1 << 15, p_hw_ds1_base + MIPI_BL_CTRL0);
559 mdelay(1);
560 iowrite32(0 << 15, p_hw_ds1_base + MIPI_BL_CTRL0);
561 }
562
auto_write_ds2_reset(uint32_t p_type)563 static void auto_write_ds2_reset(uint32_t p_type)
564 {
565 iowrite32(1 << 15, p_hw_ds2_base + MIPI_BL_CTRL0);
566 mdelay(1);
567 iowrite32(0 << 15, p_hw_ds2_base + MIPI_BL_CTRL0);
568 }
569
autowrite_path_reset(void)570 void autowrite_path_reset(void)
571 {
572 auto_write_fr_reset(0);
573 auto_write_ds1_reset(0);
574 auto_write_ds2_reset(0);
575 }
576
auto_write_fr_cfg_drop(void * cfg)577 static void auto_write_fr_cfg_drop(void *cfg)
578 {
579 auto_write_cfg_t *a_cfg = NULL;
580 uint32_t val = 0;
581
582 if (cfg == NULL) {
583 LOG(LOG_ERR, "Error input param");
584 return;
585 }
586
587 a_cfg = cfg;
588
589 val = (a_cfg->wreay_delay & 0xf) << 28 | (a_cfg->bvalid_delay & 0xf) << 24 |
590 (a_cfg->drop_jump & 0xff) << 16 | (a_cfg->drop_write & 0xff) << 8 |
591 (a_cfg->drop_skip & 0xff);
592
593 iowrite32(val, p_hw_fr_base + MIPI_BL_CTRL1);
594 }
595
auto_write_ds1_cfg_drop(void * cfg)596 static void auto_write_ds1_cfg_drop(void *cfg)
597 {
598 auto_write_cfg_t *a_cfg = NULL;
599 uint32_t val = 0;
600
601 if (cfg == NULL) {
602 LOG(LOG_ERR, "Error input param");
603 return;
604 }
605
606 a_cfg = cfg;
607
608 val = (a_cfg->wreay_delay & 0xf) << 28 | (a_cfg->bvalid_delay & 0xf) << 24 |
609 (a_cfg->drop_jump & 0xff) << 16 | (a_cfg->drop_write & 0xff) << 8 |
610 (a_cfg->drop_skip & 0xff);
611
612 iowrite32(val, p_hw_ds1_base + MIPI_BL_CTRL1);
613 }
614
auto_write_ds2_cfg_drop(void * cfg)615 static void auto_write_ds2_cfg_drop(void *cfg)
616 {
617 auto_write_cfg_t *a_cfg = NULL;
618 uint32_t val = 0;
619
620 if (cfg == NULL) {
621 LOG(LOG_ERR, "Error input param");
622 return;
623 }
624
625 a_cfg = cfg;
626
627 val = (a_cfg->wreay_delay & 0xf) << 28 | (a_cfg->bvalid_delay & 0xf) << 24 |
628 (a_cfg->drop_jump & 0xff) << 16 | (a_cfg->drop_write & 0xff) << 8 |
629 (a_cfg->drop_skip & 0xff);
630
631 iowrite32(val, p_hw_ds2_base + MIPI_BL_CTRL1);
632 }
633
auto_write_cfg_fr_ping_pong(void * cfg)634 void auto_write_cfg_fr_ping_pong(void *cfg)
635 {
636 auto_write_cfg_t *a_cfg = NULL;
637
638 if (cfg == NULL) {
639 LOG(LOG_ERR, "Error input param");
640 return;
641 }
642
643 a_cfg = cfg;
644
645 iowrite32(a_cfg->ping_st0, p_hw_fr_base + MIPI_BL_PING_ADDR0_ST);
646 iowrite32(a_cfg->ping_ed0, p_hw_fr_base + MIPI_BL_PING_ADDR0_ED);
647 iowrite32(a_cfg->pong_st0, p_hw_fr_base + MIPI_BL_PONG_ADDR0_ST);
648 iowrite32(a_cfg->pong_ed0, p_hw_fr_base + MIPI_BL_PONG_ADDR0_ED);
649 iowrite32(a_cfg->ping_st1, p_hw_fr_base + MIPI_BL_PING_ADDR1_ST);
650 iowrite32(a_cfg->ping_ed1, p_hw_fr_base + MIPI_BL_PING_ADDR1_ED);
651 iowrite32(a_cfg->pong_st1, p_hw_fr_base + MIPI_BL_PONG_ADDR1_ST);
652 iowrite32(a_cfg->pong_ed1, p_hw_fr_base + MIPI_BL_PONG_ADDR1_ED);
653
654 LOG(LOG_CRIT, "%d channel finished cfg ping pong.\n", ((auto_write_cfg_t*)cfg)->p_type);
655 }
656
auto_write_cfg_ds1_ping_pong(void * cfg)657 void auto_write_cfg_ds1_ping_pong(void *cfg)
658 {
659 auto_write_cfg_t *a_cfg = NULL;
660
661 if (cfg == NULL) {
662 LOG(LOG_ERR, "Error input param");
663 return;
664 }
665
666 a_cfg = cfg;
667
668 iowrite32(a_cfg->ping_st0, p_hw_ds1_base + MIPI_BL_PING_ADDR0_ST);
669 iowrite32(a_cfg->ping_ed0, p_hw_ds1_base + MIPI_BL_PING_ADDR0_ED);
670 iowrite32(a_cfg->pong_st0, p_hw_ds1_base + MIPI_BL_PONG_ADDR0_ST);
671 iowrite32(a_cfg->pong_ed0, p_hw_ds1_base + MIPI_BL_PONG_ADDR0_ED);
672 iowrite32(a_cfg->ping_st1, p_hw_ds1_base + MIPI_BL_PING_ADDR1_ST);
673 iowrite32(a_cfg->ping_ed1, p_hw_ds1_base + MIPI_BL_PING_ADDR1_ED);
674 iowrite32(a_cfg->pong_st1, p_hw_ds1_base + MIPI_BL_PONG_ADDR1_ST);
675 iowrite32(a_cfg->pong_ed1, p_hw_ds1_base + MIPI_BL_PONG_ADDR1_ED);
676
677 LOG(LOG_CRIT, "%d channel finished cfg ping pong.\n", ((auto_write_cfg_t*)cfg)->p_type);
678 }
679
auto_write_cfg_ds2_ping_pong(void * cfg)680 void auto_write_cfg_ds2_ping_pong(void *cfg)
681 {
682 auto_write_cfg_t *a_cfg = NULL;
683
684 if (cfg == NULL) {
685 LOG(LOG_ERR, "Error input param");
686 return;
687 }
688
689 LOG(LOG_CRIT, "%d channel start cfg ping pong.\n", ((auto_write_cfg_t*)cfg)->p_type);
690
691 a_cfg = cfg;
692
693 iowrite32(a_cfg->ping_st0, p_hw_ds2_base + MIPI_BL_PING_ADDR0_ST);
694 iowrite32(a_cfg->ping_ed0, p_hw_ds2_base + MIPI_BL_PING_ADDR0_ED);
695 iowrite32(a_cfg->pong_st0, p_hw_ds2_base + MIPI_BL_PONG_ADDR0_ST);
696 iowrite32(a_cfg->pong_ed0, p_hw_ds2_base + MIPI_BL_PONG_ADDR0_ED);
697 iowrite32(a_cfg->ping_st1, p_hw_ds2_base + MIPI_BL_PING_ADDR1_ST);
698 iowrite32(a_cfg->ping_ed1, p_hw_ds2_base + MIPI_BL_PING_ADDR1_ED);
699 iowrite32(a_cfg->pong_st1, p_hw_ds2_base + MIPI_BL_PONG_ADDR1_ST);
700 iowrite32(a_cfg->pong_ed1, p_hw_ds2_base + MIPI_BL_PONG_ADDR1_ED);
701
702 LOG(LOG_CRIT, "%d channel finished cfg ping pong.\n", ((auto_write_cfg_t*)cfg)->p_type);
703 }
704
auto_write_fr_init(void * cfg)705 void auto_write_fr_init(void *cfg)
706 {
707 auto_write_cfg_t *a_cfg = NULL;
708
709 if (cfg == NULL) {
710 LOG(LOG_ERR, "Error input param");
711 return;
712 }
713
714 a_cfg = cfg;
715
716 auto_write_cfg_fr_ping_pong(cfg);
717
718 auto_write_fr_reset(a_cfg->p_type);
719
720 auto_write_fr_cfg_buff(cfg);
721
722 auto_write_fr_cfg_drop(cfg);
723 }
724
auto_write_ds1_init(void * cfg)725 void auto_write_ds1_init(void *cfg)
726 {
727 auto_write_cfg_t *a_cfg = NULL;
728
729 if (cfg == NULL) {
730 LOG(LOG_ERR, "Error input param");
731 return;
732 }
733
734 a_cfg = cfg;
735
736 auto_write_cfg_ds1_ping_pong(cfg);
737
738 auto_write_ds1_reset(a_cfg->p_type);
739
740 auto_write_ds1_cfg_buff(cfg);
741
742 auto_write_ds1_cfg_drop(cfg);
743 }
744
auto_write_ds2_init(void * cfg)745 void auto_write_ds2_init(void *cfg)
746 {
747 auto_write_cfg_t *a_cfg = NULL;
748
749 if (cfg == NULL) {
750 LOG(LOG_ERR, "Error input param");
751 return;
752 }
753
754 a_cfg = cfg;
755
756 auto_write_cfg_ds2_ping_pong(cfg);
757
758 auto_write_ds2_reset(a_cfg->p_type);
759
760 auto_write_ds2_cfg_buff(cfg);
761
762 auto_write_ds2_cfg_drop(cfg);
763 }
764
auto_write_fr_start(void * cfg)765 void auto_write_fr_start(void *cfg)
766 {
767 auto_write_cfg_t *a_cfg = NULL;
768 uint32_t val = 0;
769
770 if (cfg == NULL) {
771 LOG(LOG_ERR, "Error input param");
772 return;
773 }
774
775 a_cfg = cfg;
776
777 val = ioread32(p_hw_fr_base + MIPI_BL_CTRL0);
778 val = val | 0x2;
779 iowrite32(val, p_hw_fr_base + MIPI_BL_CTRL0);// reset based addr
780
781 val = ioread32(p_hw_fr_base + MIPI_BL_CTRL0);
782 val = val & (~0x2);
783 iowrite32(val, p_hw_fr_base + MIPI_BL_CTRL0);// reset based addr
784
785 val = ioread32(p_hw_fr_base + MIPI_BL_CTRL0);
786
787 val = ioread32(p_hw_fr_base + MIPI_BL_CTRL0);
788 val = val | ((a_cfg->drop_enable & 0x1) << 5);
789 iowrite32(val, p_hw_fr_base + MIPI_BL_CTRL0); // ladder enable drop mode
790
791 val = val | (1 << 13) | (1 << 0);
792 iowrite32(val, p_hw_fr_base + MIPI_BL_CTRL0);// ladder enable
793
794 LOG(LOG_CRIT, "%d channel write finished.\n", ((auto_write_cfg_t*)cfg)->p_type);
795 }
796
auto_write_ds1_start(void * cfg)797 void auto_write_ds1_start(void *cfg)
798 {
799 auto_write_cfg_t *a_cfg = NULL;
800 uint32_t val = 0;
801
802 if (cfg == NULL) {
803 LOG(LOG_ERR, "Error input param");
804 return;
805 }
806
807 a_cfg = cfg;
808
809 val = ioread32(p_hw_ds1_base + MIPI_BL_CTRL0);
810 val = val | 0x2;
811 iowrite32(val, p_hw_ds1_base + MIPI_BL_CTRL0);// reset based addr
812
813 val = ioread32(p_hw_ds1_base + MIPI_BL_CTRL0);
814 val = val & (~0x2);
815 iowrite32(val, p_hw_ds1_base + MIPI_BL_CTRL0);// reset based addr
816
817 val = ioread32(p_hw_ds1_base + MIPI_BL_CTRL0);
818
819 val = ioread32(p_hw_ds1_base + MIPI_BL_CTRL0);
820 val = val | ((a_cfg->drop_enable & 0x1) << 5);
821 iowrite32(val, p_hw_ds1_base + MIPI_BL_CTRL0); // ladder enable drop mode
822
823 val = val | (1 << 13) | (1 << 0);
824 iowrite32(val, p_hw_ds1_base + MIPI_BL_CTRL0);// ladder enable
825
826 LOG(LOG_CRIT, "%d channel write finished.\n", ((auto_write_cfg_t*)cfg)->p_type);
827 }
828
auto_write_ds2_start(void * cfg)829 void auto_write_ds2_start(void *cfg)
830 {
831 auto_write_cfg_t *a_cfg = NULL;
832 uint32_t val = 0;
833
834 if (cfg == NULL) {
835 LOG(LOG_ERR, "Error input param");
836 return;
837 }
838
839 a_cfg = cfg;
840
841 val = ioread32(p_hw_ds2_base + MIPI_BL_CTRL0);
842 val = val | 0x2;
843 iowrite32(val, p_hw_ds2_base + MIPI_BL_CTRL0);// reset based addr
844
845 val = ioread32(p_hw_ds2_base + MIPI_BL_CTRL0);
846 val = val & (~0x2);
847 iowrite32(val, p_hw_ds2_base + MIPI_BL_CTRL0);// reset based addr
848
849 val = ioread32(p_hw_ds2_base + MIPI_BL_CTRL0);
850
851 val = ioread32(p_hw_ds2_base + MIPI_BL_CTRL0);
852 val = val | ((a_cfg->drop_enable & 0x1) << 5);
853 iowrite32(val, p_hw_ds2_base + MIPI_BL_CTRL0); // ladder enable drop mode
854
855 val = val | (1 << 13) | (1 << 0);
856 iowrite32(val, p_hw_ds2_base + MIPI_BL_CTRL0);// ladder enable
857
858 LOG(LOG_CRIT, "%d channel write finished.\n", ((auto_write_cfg_t*)cfg)->p_type);
859 }
860
auto_write_stop(void * cfg)861 void auto_write_stop(void *cfg)
862 {
863 auto_write_cfg_t *a_cfg = NULL;
864 uint32_t val = 0;
865
866 if (cfg == NULL) {
867 LOG(LOG_ERR, "Error input param");
868 return;
869 }
870
871 a_cfg = cfg;
872
873 val = ioread32(p_hw_fr_base + MIPI_BL_CTRL0);
874 val = val | (0x1 << 4);
875 iowrite32(val, p_hw_fr_base + MIPI_BL_CTRL0); // ladder stop next frame
876
877 //val = read_reg(base_addr + MIPI_BL_CTRL0);
878 //val = val & (~(1 << 13)) & (~(1 << 0));
879 //write_reg(val, base_addr + MIPI_BL_CTRL0); // ladder disable
880 }
881
882
883
884