1 // Copyright (C) 2022 Beken Corporation
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #include <driver/gpio.h>
16 #include <driver/int.h>
17 #include <driver/i2c.h>
18 #include "clock_driver.h"
19 #include "gpio_driver.h"
20 #include "icu_driver.h"
21 #include <os/mem.h>
22 #include "power_driver.h"
23 #include <os/os.h>
24 #include "i2c_hw.h"
25 #include "i2c_driver.h"
26 #include "i2c_hal.h"
27 #include "i2c_statis.h"
28 #include "sys_driver.h"
29
30 typedef enum {
31 I2C_IDLE = 0,
32 I2C_START,
33 I2C_TX_DEV_ADDR,
34 I2C_RX_DEV_ADDR,
35 I2C_TX_MEM_ADDR_HIGH_8BIT,
36 I2C_TX_MEM_ADDR_LOW_8BIT,
37 I2C_TX_DATA,
38 I2C_RX_DATA,
39 I2C_STOP,
40 I2C_GET_ACK,
41 } i2c_master_status_t;
42
43 typedef struct {
44 i2c_hal_t hal;
45 uint8_t id_init_bits;
46 i2c_work_mode_t work_mode;
47 i2c_addr_mode_t addr_mode;
48 bool is_addr_tx_done;
49 bool is_with_mem_addr;
50 uint8_t *data_ptr;
51 uint32_t data_size;
52 uint32_t data_offset;
53 uint16_t dev_addr;
54 uint32_t mem_addr;
55 i2c_mem_addr_size_t mem_addr_size;
56 i2c_master_status_t master_status;
57 beken_semaphore_t tx_sema;
58 beken_semaphore_t rx_sema;
59 uint32_t int_status;
60 } i2c_driver_t;
61
62 typedef struct {
63 i2c_isr_t callback;
64 void *param;
65 } i2c_callback_t;
66
67 typedef struct bkTimerCallback{
68 beken2_timer_t* i2ctimer;
69 int callbackflag;
70 int asyncflag;
71 uint8_t transtate;
72 }bkTimercb_t;
73
74
75 #define I2C_RETURN_ON_NOT_INIT() do {\
76 if (!s_i2c_driver_is_init) {\
77 I2C_LOGE("i2c driver not init\r\n");\
78 return BK_ERR_I2C_NOT_INIT;\
79 }\
80 } while(0)
81
82 #define I2C_RETURN_ON_ID_NOT_INIT(id) do {\
83 if (!(s_i2c[id].id_init_bits & BIT((id)))) {\
84 I2C_LOGE("i2c id number(%d) is not init\r\n", (id));\
85 return BK_ERR_I2C_ID_NOT_INIT;\
86 }\
87 } while(0)
88
89 #define I2C_SET_PIN(id) do {\
90 i2c_hal_set_pin(&s_i2c[id].hal);\
91 gpio_dev_unmap(I2C##id##_LL_SDA_PIN);\
92 gpio_dev_unmap(I2C##id##_LL_SCL_PIN);\
93 gpio_dev_map(I2C##id##_LL_SCL_PIN, GPIO_DEV_I2C##id##_SCL);\
94 gpio_dev_map(I2C##id##_LL_SDA_PIN, GPIO_DEV_I2C##id##_SDA);\
95 bk_gpio_pull_up(I2C##id##_LL_SCL_PIN);\
96 bk_gpio_pull_up(I2C##id##_LL_SDA_PIN);\
97 } while(0)
98
99 static bkTimercb_t i2ccallback[SOC_I2C_UNIT_NUM] ={0};
100 static i2c_driver_t s_i2c[SOC_I2C_UNIT_NUM] = {0};
101 static bool s_i2c_driver_is_init = false;
102
103 static void i2c0_isr(void);
104 #if (SOC_I2C_UNIT_NUM > 1)
105 static void i2c1_isr(void);
106 #endif
107 #if (SOC_I2C_UNIT_NUM > 2)
108 static void i2c2_isr(void);
109 #endif
110
i2c_init_gpio(i2c_id_t id)111 static void i2c_init_gpio(i2c_id_t id)
112 {
113 switch(id) {
114 case I2C_ID_0:
115 I2C_SET_PIN(0);
116 break;
117 #if (SOC_I2C_UNIT_NUM > 1)
118 case I2C_ID_1:
119 I2C_SET_PIN(1);
120 break;
121 #endif
122 #if (SOC_I2C_UNIT_NUM > 2)
123 case I2C_ID_2:
124 I2C_SET_PIN(2);
125 break;
126 #endif
127 default:
128 break;
129 }
130 }
131
132
133 #if (CONFIG_SYSTEM_CTRL)
i2c_clock_enable(i2c_id_t id)134 static void i2c_clock_enable(i2c_id_t id)
135 {
136 switch(id)
137 {
138 case I2C_ID_0:
139 sys_drv_dev_clk_pwr_up(CLK_PWR_ID_I2C1, CLK_PWR_CTRL_PWR_UP);
140 break;
141
142 #if (SOC_I2C_UNIT_NUM > 1)
143 case I2C_ID_1:
144 sys_drv_dev_clk_pwr_up(CLK_PWR_ID_I2C2, CLK_PWR_CTRL_PWR_UP);
145 break;
146 #endif
147 default:
148 break;
149 }
150 }
151
i2c_clock_disable(i2c_id_t id)152 static void i2c_clock_disable(i2c_id_t id)
153 {
154 switch(id)
155 {
156 case I2C_ID_0:
157 sys_drv_dev_clk_pwr_up(CLK_PWR_ID_I2C1, CLK_PWR_CTRL_PWR_DOWN);
158 break;
159 #if (SOC_I2C_UNIT_NUM > 1)
160 case I2C_ID_1:
161 sys_drv_dev_clk_pwr_up(CLK_PWR_ID_I2C2, CLK_PWR_CTRL_PWR_DOWN);
162 break;
163 #endif
164 default:
165 break;
166 }
167 }
168
i2c_interrupt_enable(i2c_id_t id)169 static void i2c_interrupt_enable(i2c_id_t id)
170 {
171 switch(id)
172 {
173 case I2C_ID_0:
174 sys_drv_int_enable(I2C_INTERRUPT_CTRL_BIT);
175 break;
176 #if (SOC_I2C_UNIT_NUM > 1)
177 case I2C_ID_1:
178 sys_drv_int_enable(I2C1_INTERRUPT_CTRL_BIT);
179 break;
180 #endif
181 default:
182 break;
183 }
184 }
185
i2c_interrupt_disable(i2c_id_t id)186 static void i2c_interrupt_disable(i2c_id_t id)
187 {
188 switch(id)
189 {
190 case I2C_ID_0:
191 sys_drv_int_disable(I2C_INTERRUPT_CTRL_BIT);
192 break;
193 #if (SOC_I2C_UNIT_NUM > 1)
194 case I2C_ID_1:
195 sys_drv_int_disable(I2C1_INTERRUPT_CTRL_BIT);
196 break;
197 #endif
198 default:
199 break;
200 }
201 }
202 #endif
203
204
205 /* 1. power up i2c
206 * 2. set clk
207 * 3. icu enable interrupt
208 * 4. set gpio as i2c
209 */
i2c_id_init_common(i2c_id_t id)210 static void i2c_id_init_common(i2c_id_t id)
211 {
212 bk_err_t ret = 0;
213
214 #if (CONFIG_SYSTEM_CTRL)
215 i2c_clock_enable(id);
216 i2c_interrupt_enable(id);
217 #else
218 power_i2c_pwr_up(id);
219 clk_set_i2c_clk_26m(id);
220 icu_enable_i2c_interrupt(id);
221 #endif
222 i2c_init_gpio(id);
223
224 if (s_i2c[id].tx_sema == NULL) {
225 ret = rtos_init_semaphore(&(s_i2c[id].tx_sema), 1);
226 BK_ASSERT(kNoErr == ret);
227 }
228
229 if (s_i2c[id].rx_sema == NULL) {
230 ret = rtos_init_semaphore(&(s_i2c[id].rx_sema), 1);
231 BK_ASSERT(kNoErr == ret);
232 }
233
234 s_i2c[id].id_init_bits |= BIT(id);
235 }
236
i2c_id_deinit_common(i2c_id_t id)237 static void i2c_id_deinit_common(i2c_id_t id)
238 {
239 i2c_hal_stop_common(&s_i2c[id].hal);
240 i2c_hal_reset_config_to_default(&s_i2c[id].hal);
241
242 #if (CONFIG_SYSTEM_CTRL)
243 i2c_clock_disable(id);
244 i2c_interrupt_disable(id);
245 #else
246 icu_disable_i2c_interrupt(id);
247 power_i2c_pwr_down(id);
248 #endif
249
250 s_i2c[id].addr_mode = 0;
251 rtos_deinit_semaphore(&(s_i2c[id].tx_sema));
252 rtos_deinit_semaphore(&(s_i2c[id].rx_sema));
253 s_i2c[id].tx_sema = NULL;
254 s_i2c[id].rx_sema = NULL;
255 s_i2c[id].id_init_bits &= ~BIT(id);
256 }
257
i2c_wait_sm_bus_idle(i2c_id_t id,uint32_t timeout_ms)258 static bk_err_t i2c_wait_sm_bus_idle(i2c_id_t id, uint32_t timeout_ms)
259 {
260 uint32_t start_tick = 0;
261 uint32_t cur_tick = 0;
262 uint32_t tick_offset = 0;
263
264 start_tick = rtos_get_time();
265 while (i2c_hal_is_busy(&s_i2c[id].hal)) {
266 cur_tick = rtos_get_time();
267 tick_offset = (cur_tick >= start_tick) ? (cur_tick - start_tick) : (0xffffffff - start_tick + cur_tick);
268 if (tick_offset > timeout_ms) {
269 I2C_LOGW("i2c sm bus is busy\r\n");
270 return BK_ERR_I2C_SM_BUS_BUSY;
271 }
272 }
273
274 return BK_OK;
275 }
276
i2c_transtate_reset(int id)277 static void i2c_transtate_reset (int id)
278 {
279 i2ccallback[id].transtate = 0;
280 }
281
i2c_transtate_set(int id)282 static void i2c_transtate_set (int id)
283 {
284 i2ccallback[id].transtate = 1;
285 }
286
i2c_timer_start(int id)287 static void i2c_timer_start ( int id )
288 {
289 if ((i2ccallback[id].asyncflag == 1)&&(i2ccallback[id].callbackflag == 1)) {
290 if (i2ccallback[id].i2ctimer!= NULL) {
291 rtos_start_oneshot_timer( i2ccallback[id].i2ctimer) ;
292 }
293 i2ccallback[id].asyncflag = 0;
294 }
295 }
296
i2c_master_start(i2c_id_t id)297 static bk_err_t i2c_master_start(i2c_id_t id)
298 {
299 i2c_hal_disable_stop(&s_i2c[id].hal);
300 i2c_hal_set_tx_mode(&s_i2c[id].hal);
301 s_i2c[id].master_status = I2C_TX_DEV_ADDR;
302 i2c_transtate_reset(id);
303 return BK_OK;
304 }
305
i2c_master_stop(i2c_id_t id)306 static bk_err_t i2c_master_stop(i2c_id_t id)
307 {
308 i2c_hal_enable_stop(&s_i2c[id].hal);
309 s_i2c[id].int_status |= I2C1_F_STOP;
310 s_i2c[id].master_status = I2C_IDLE;
311 i2c_timer_start(id);
312 return BK_OK;
313 }
314
i2c_master_set_write_dev_addr(i2c_id_t id,uint16_t dev_addr)315 static bk_err_t i2c_master_set_write_dev_addr(i2c_id_t id, uint16_t dev_addr)
316 {
317 /* write slave_addr first,then enable start bit,
318 * otherwise the slave_addr written will be zero
319 */
320 i2c_hal_write_byte(&s_i2c[id].hal, dev_addr << 1 & (~0x01));
321 i2c_hal_enable_start(&s_i2c[id].hal);
322
323 if (!s_i2c[id].is_with_mem_addr) {
324 s_i2c[id].master_status = I2C_TX_DATA;
325 return BK_OK;
326 }
327
328 if (s_i2c[id].mem_addr_size == I2C_MEM_ADDR_SIZE_16BIT) {
329 s_i2c[id].master_status = I2C_TX_MEM_ADDR_HIGH_8BIT;
330 } else {
331 s_i2c[id].master_status = I2C_TX_MEM_ADDR_LOW_8BIT;
332 }
333 return BK_OK;
334 }
335
i2c_master_set_read_dev_addr(i2c_id_t id,uint16_t dev_addr)336 static bk_err_t i2c_master_set_read_dev_addr(i2c_id_t id, uint16_t dev_addr)
337 {
338 i2c_hal_write_byte(&s_i2c[id].hal, dev_addr << 1 | 0x01);
339 i2c_hal_enable_start(&s_i2c[id].hal);
340 s_i2c[id].int_status |= I2C1_F_START;
341 s_i2c[id].master_status = I2C_RX_DATA;
342 return BK_OK;
343 }
344
i2c_master_write_mem_addr_high_8bit(i2c_id_t id,uint16_t mem_addr)345 static bk_err_t i2c_master_write_mem_addr_high_8bit(i2c_id_t id, uint16_t mem_addr)
346 {
347 i2c_hal_write_byte(&s_i2c[id].hal, mem_addr >> 8 & 0xff);
348 s_i2c[id].master_status = I2C_TX_MEM_ADDR_LOW_8BIT;
349 return BK_OK;
350 }
351
i2c_master_write_mem_addr_low_8bit(i2c_id_t id,uint16_t mem_addr)352 static bk_err_t i2c_master_write_mem_addr_low_8bit(i2c_id_t id, uint16_t mem_addr)
353 {
354 i2c_hal_write_byte(&s_i2c[id].hal, mem_addr & 0xff);
355 if (s_i2c[id].work_mode == I2C_MASTER_WRITE) {
356 s_i2c[id].master_status = I2C_TX_DATA;
357 } else if (s_i2c[id].work_mode == I2C_MASTER_READ) {
358 s_i2c[id].master_status = I2C_RX_DEV_ADDR;
359 }
360 return BK_OK;
361 }
362
i2c_master_write_byte(i2c_id_t id,uint8_t data)363 static bk_err_t i2c_master_write_byte(i2c_id_t id, uint8_t data)
364 {
365 i2c_hal_write_byte(&s_i2c[id].hal, data);
366 return BK_OK;
367 }
368
369 #if (CONFIG_FM_I2C)
i2c_master_read_byte(i2c_id_t id)370 static uint8_t i2c_master_read_byte(i2c_id_t id)
371 {
372 return i2c_hal_read_byte(&s_i2c[id].hal);
373 }
374
i2c0_master_write_data(i2c_id_t id)375 static bk_err_t i2c0_master_write_data(i2c_id_t id)
376 {
377 uint32_t remain_size = s_i2c[id].data_size - s_i2c[id].data_offset;
378 if (!remain_size) {
379 I2C_LOGD("data_size:%d tx done\r\n", s_i2c[id].data_size);
380 i2c_master_stop(id);
381 rtos_set_semaphore(&s_i2c[id].tx_sema);
382 } else {
383 i2c_master_write_byte(id, s_i2c[id].data_ptr[(s_i2c[id].data_offset)++]);
384 s_i2c[id].master_status = I2C_TX_DATA;
385 }
386 return BK_OK;
387 }
388 #endif
389
i2c1_master_write_data(i2c_id_t id)390 static bk_err_t i2c1_master_write_data(i2c_id_t id)
391 {
392 uint32_t data_size = 0;
393 uint32_t remain_size = s_i2c[id].data_size - s_i2c[id].data_offset;
394 if (!remain_size) {
395 I2C_LOGD("data_size:%d tx done\r\n", s_i2c[id].data_size);
396 i2c_master_stop(id);
397 rtos_set_semaphore(&s_i2c[id].tx_sema);
398 return BK_OK;
399 }
400 uint32_t empty_fifo_num = i2c_hal_get_write_empty_fifo_num(&s_i2c[id].hal);
401 if (remain_size < empty_fifo_num) {
402 data_size = remain_size;
403 } else {
404 data_size = empty_fifo_num;
405 }
406 for (uint32_t i = 0; i < data_size; i++) {
407 i2c_master_write_byte(id, s_i2c[id].data_ptr[(s_i2c[id].data_offset)++]);
408 }
409 remain_size = s_i2c[id].data_size - s_i2c[id].data_offset;
410 if (remain_size < empty_fifo_num) {
411 I2C_LOGD("remain_size:%d, empty_fifo_num:%d\r\n", remain_size, empty_fifo_num);
412 s_i2c[id].int_status &= ~(I2C1_F_INT_MODE_V | I2C1_F_START);
413 }
414 s_i2c[id].master_status = I2C_TX_DATA;
415 return BK_OK;
416 }
417
418
419 #if (CONFIG_FM_I2C)
i2c0_master_read_data(i2c_id_t id)420 static bk_err_t i2c0_master_read_data(i2c_id_t id)
421 {
422 i2c_hal_set_rx_mode(&s_i2c[id].hal);
423 /* tx ack, next isr read data */
424 if (i2c_hal_is_start(&s_i2c[id].hal)) {
425 i2c_hal_tx_ack(&s_i2c[id].hal);
426 s_i2c[id].master_status = I2C_RX_DATA;
427 return BK_OK;
428 }
429 s_i2c[id].data_ptr[(s_i2c[id].data_offset)++] = i2c_master_read_byte(id);
430 if (s_i2c[id].data_offset == s_i2c[id].data_size) {
431 I2C_LOGI("data_size:%d rx done\r\n", s_i2c[id].data_size);
432 /* rx data done, send NACK and stop*/
433 i2c_hal_tx_non_ack(&s_i2c[id].hal);
434 i2c_master_stop(id);
435 rtos_set_semaphore(&s_i2c[id].rx_sema);
436 } else {
437 i2c_hal_tx_ack(&s_i2c[id].hal);
438 s_i2c[id].master_status = I2C_RX_DATA;
439 }
440 return BK_OK;
441 }
442 #endif
443
i2c1_master_read_data(i2c_id_t id)444 bk_err_t i2c1_master_read_data(i2c_id_t id)
445 {
446 if (i2c_hal_is_start(&s_i2c[id].hal)) {
447 I2C_LOGD("master_read i2c_is_start\r\n");
448 s_i2c[id].int_status |= I2C1_F_ACK;
449 s_i2c[id].master_status = I2C_RX_DATA;
450 return BK_OK;
451 }
452 uint32_t fifo_num = i2c_hal_get_read_fifo_num(&s_i2c[id].hal);
453 for (uint32_t i = 0; i < fifo_num; i++) {
454 s_i2c[id].data_ptr[(s_i2c[id].data_offset)++] = i2c_hal_read_byte(&s_i2c[id].hal);
455 if (s_i2c[id].data_offset == s_i2c[id].data_size) { /* avoid index is out of array range */
456 break;
457 }
458 }
459 uint32_t remain_size = s_i2c[id].data_size - s_i2c[id].data_offset;
460 if (!remain_size) {
461 s_i2c[id].int_status &= ~(I2C1_F_ACK | I2C1_F_START);
462 i2c_master_stop(id);
463 rtos_set_semaphore(&s_i2c[id].rx_sema);
464 } else if (remain_size < fifo_num) {
465 s_i2c[id].int_status |= (I2C1_F_ACK | I2C1_F_INT_MODE_V);
466 s_i2c[id].master_status = I2C_RX_DATA;
467 } else {
468 s_i2c[id].int_status |= I2C1_F_ACK;
469 s_i2c[id].master_status = I2C_RX_DATA;
470 }
471 return BK_OK;
472 }
473
bk_i2c_timer_callback(int id,void * myTimer)474 void bk_i2c_timer_callback(int id, void* myTimer)
475 {
476 os_memset(&i2ccallback[id],0,sizeof(bkTimercb_t));
477 i2ccallback[id].i2ctimer =(beken2_timer_t*) myTimer;
478 i2ccallback[id].callbackflag = 1;
479 }
480
bk_i2c_get_busstate(int id)481 uint8_t bk_i2c_get_busstate ( int id )
482 {
483 I2C_LOGD("bk_i2c_get_busstate[%d].\n",s_i2c[id].master_status);
484 if(s_i2c[id].master_status==0){
485 return 1;//idle
486 } else {
487 return 0;//busy
488 }
489 }
490
bk_i2c_get_transstate(int id)491 uint8_t bk_i2c_get_transstate ( int id )
492 {
493 return i2ccallback[id].transtate;
494 }
495
bk_i2c_driver_init(void)496 bk_err_t bk_i2c_driver_init(void)
497 {
498 if (s_i2c_driver_is_init) {
499 return BK_OK;
500 }
501
502 os_memset(&s_i2c, 0, sizeof(s_i2c));
503 for (int id = I2C_ID_0; id < I2C_ID_MAX; id++) {
504 s_i2c[id].hal.id = id;
505 i2c_hal_init(&s_i2c[id].hal);
506 }
507 bk_int_isr_register(INT_SRC_I2C0, i2c0_isr, NULL);
508 #if (SOC_I2C_UNIT_NUM > 1)
509 bk_int_isr_register(INT_SRC_I2C1, i2c1_isr, NULL);
510 #endif
511 #if (SOC_I2C_UNIT_NUM > 2)
512 bk_int_isr_register(INT_SRC_I2C2, i2c2_isr, NULL);
513 #endif
514 i2c_statis_init();
515 s_i2c_driver_is_init = true;
516
517 return BK_OK;
518 }
519
bk_i2c_driver_deinit(void)520 bk_err_t bk_i2c_driver_deinit(void)
521 {
522 if (!s_i2c_driver_is_init) {
523 return BK_OK;
524 }
525
526 for (int id = I2C_ID_0; id < I2C_ID_MAX; id++) {
527 i2c_id_deinit_common(id);
528 }
529 bk_int_isr_unregister(INT_SRC_I2C0);
530 #if (SOC_I2C_UNIT_NUM > 1)
531 bk_int_isr_unregister(INT_SRC_I2C1);
532 #endif
533 #if (SOC_I2C_UNIT_NUM > 2)
534 bk_int_isr_unregister(INT_SRC_I2C2);
535 #endif
536 s_i2c_driver_is_init = false;
537
538 return BK_OK;
539 }
540
bk_i2c_init(i2c_id_t id,const i2c_config_t * cfg)541 bk_err_t bk_i2c_init(i2c_id_t id, const i2c_config_t *cfg)
542 {
543 BK_RETURN_ON_NULL(cfg);
544 I2C_RETURN_ON_NOT_INIT();
545
546 #if CONFIG_DUAL_CORE
547 uint32_t support_id = CONFIG_I2C_SUPPORT_ID_BITS;
548 uint32_t id_init_bits = BIT(id);
549 if (!(support_id & id_init_bits))
550 return BK_ERR_I2C_CHECK_DEFCONFIG;
551 #endif
552 s_i2c[id].int_status = 0;
553 s_i2c[id].addr_mode = cfg->addr_mode;
554 i2c_id_init_common(id);
555 i2c_hal_configure(&s_i2c[id].hal, cfg);
556 i2c_hal_start_common(&s_i2c[id].hal);
557 I2C_LOGI("I2C(%d) init ok, baud_rate:%d\r\n", id, cfg->baud_rate);
558 return BK_OK;
559 }
560
bk_i2c_deinit(i2c_id_t id)561 bk_err_t bk_i2c_deinit(i2c_id_t id)
562 {
563 I2C_RETURN_ON_NOT_INIT();
564
565 i2c_id_deinit_common(id);
566
567 return BK_OK;
568 }
569
bk_i2c_master_write(i2c_id_t id,uint32_t dev_addr,const uint8_t * data,uint32_t size,uint32_t timeout_ms)570 bk_err_t bk_i2c_master_write(i2c_id_t id, uint32_t dev_addr, const uint8_t *data, uint32_t size, uint32_t timeout_ms)
571 {
572 I2C_RETURN_ON_NOT_INIT();
573 I2C_RETURN_ON_ID_NOT_INIT(id);
574 BK_RETURN_ON_ERR(i2c_wait_sm_bus_idle(id, timeout_ms));
575 if (timeout_ms != 0xFFFFFFFF){
576 i2ccallback[id].asyncflag = 1;
577 }
578 uint32_t int_level = rtos_disable_int();
579 s_i2c[id].work_mode = I2C_MASTER_WRITE;
580 s_i2c[id].is_with_mem_addr = false;
581 s_i2c[id].dev_addr = dev_addr;
582 s_i2c[id].data_ptr = (uint8_t *)data;
583 s_i2c[id].data_size = size;
584 s_i2c[id].data_offset = 0;
585 s_i2c[id].int_status = 0;
586 i2c_master_start(id);
587 i2c_master_set_write_dev_addr(id, dev_addr);
588 i2c_hal_set_write_int_mode(&s_i2c[id].hal, size);
589 rtos_enable_int(int_level);
590
591 rtos_get_semaphore(&s_i2c[id].tx_sema, timeout_ms);
592
593 return BK_OK;
594 }
595
bk_i2c_master_read(i2c_id_t id,uint32_t dev_addr,uint8_t * data,uint32_t size,uint32_t timeout_ms)596 bk_err_t bk_i2c_master_read(i2c_id_t id, uint32_t dev_addr, uint8_t *data, uint32_t size, uint32_t timeout_ms)
597 {
598 I2C_RETURN_ON_NOT_INIT();
599 I2C_RETURN_ON_ID_NOT_INIT(id);
600 BK_RETURN_ON_ERR(i2c_wait_sm_bus_idle(id, timeout_ms));
601 if (timeout_ms != 0xFFFFFFFF){
602 i2ccallback[id].asyncflag = 1;
603 }
604 uint32_t int_level = rtos_disable_int();
605 s_i2c[id].work_mode = I2C_MASTER_READ;
606 s_i2c[id].is_with_mem_addr = false;
607 s_i2c[id].dev_addr = dev_addr;
608 s_i2c[id].data_ptr = data;
609 s_i2c[id].data_size = size;
610 s_i2c[id].data_offset = 0;
611 s_i2c[id].int_status = 0;
612 i2c_master_start(id);
613 i2c_master_set_read_dev_addr(id, dev_addr);
614 i2c_hal_set_rx_mode(&s_i2c[id].hal);
615 i2c_hal_set_read_int_mode(&s_i2c[id].hal, size);
616 rtos_enable_int(int_level);
617
618 rtos_get_semaphore(&s_i2c[id].rx_sema, timeout_ms);
619
620 return BK_OK;
621 }
622
bk_i2c_slave_write(i2c_id_t id,const uint8_t * data,uint32_t size,uint32_t timeout_ms)623 bk_err_t bk_i2c_slave_write(i2c_id_t id, const uint8_t *data, uint32_t size, uint32_t timeout_ms)
624 {
625 I2C_RETURN_ON_NOT_INIT();
626 I2C_RETURN_ON_ID_NOT_INIT(id);
627 BK_RETURN_ON_ERR(i2c_wait_sm_bus_idle(id, timeout_ms));
628
629 uint32_t int_level = rtos_disable_int();
630 i2c_hal_enable_start(&s_i2c[id].hal);
631 i2c_hal_set_write_int_mode(&s_i2c[id].hal, size);
632 s_i2c[id].work_mode = I2C_SLAVE_WRITE;
633 s_i2c[id].is_with_mem_addr = false;
634 s_i2c[id].data_ptr = (uint8_t *)data;
635 s_i2c[id].data_size = size;
636 s_i2c[id].data_offset = 0;
637 s_i2c[id].int_status = 0;
638 rtos_enable_int(int_level);
639
640 rtos_get_semaphore(&s_i2c[id].tx_sema, timeout_ms);
641
642 return BK_OK;
643 }
644
bk_i2c_slave_read(i2c_id_t id,uint8_t * data,uint32_t size,uint32_t timeout_ms)645 bk_err_t bk_i2c_slave_read(i2c_id_t id, uint8_t *data, uint32_t size, uint32_t timeout_ms)
646 {
647 I2C_RETURN_ON_NOT_INIT();
648 I2C_RETURN_ON_ID_NOT_INIT(id);
649 BK_RETURN_ON_ERR(i2c_wait_sm_bus_idle(id, timeout_ms));
650
651 uint32_t int_level = rtos_disable_int();
652 i2c_hal_enable_start(&s_i2c[id].hal);
653 i2c_hal_set_read_int_mode(&s_i2c[id].hal, size);
654 s_i2c[id].work_mode = I2C_SLAVE_READ;
655 s_i2c[id].is_with_mem_addr = false;
656 s_i2c[id].data_ptr = data;
657 s_i2c[id].data_size = size;
658 s_i2c[id].data_offset = 0;
659 s_i2c[id].int_status = 0;
660 rtos_enable_int(int_level);
661
662 rtos_get_semaphore(&s_i2c[id].rx_sema, timeout_ms);
663
664 return BK_OK;
665 }
666
bk_i2c_memory_write(i2c_id_t id,const i2c_mem_param_t * mem_param)667 bk_err_t bk_i2c_memory_write(i2c_id_t id, const i2c_mem_param_t *mem_param)
668 {
669 I2C_RETURN_ON_NOT_INIT();
670 I2C_RETURN_ON_ID_NOT_INIT(id);
671 BK_RETURN_ON_ERR(i2c_wait_sm_bus_idle(id, mem_param->timeout_ms));
672
673 uint32_t int_level = rtos_disable_int();
674 s_i2c[id].work_mode = I2C_MASTER_WRITE;
675 s_i2c[id].is_with_mem_addr = true;
676 s_i2c[id].dev_addr = mem_param->dev_addr;
677 s_i2c[id].mem_addr = mem_param->mem_addr;
678 s_i2c[id].mem_addr_size = mem_param->mem_addr_size;
679 s_i2c[id].data_ptr = mem_param->data;
680 s_i2c[id].data_size = mem_param->data_size;
681 s_i2c[id].data_offset = 0;
682 s_i2c[id].int_status = 0;
683 i2c_master_start(id);
684 i2c_master_set_write_dev_addr(id, mem_param->dev_addr);
685 i2c_hal_set_write_int_mode(&s_i2c[id].hal, mem_param->data_size);
686 rtos_enable_int(int_level);
687
688 rtos_get_semaphore(&s_i2c[id].tx_sema, mem_param->timeout_ms);
689
690 return BK_OK;
691 }
692
bk_i2c_memory_read(i2c_id_t id,const i2c_mem_param_t * mem_param)693 bk_err_t bk_i2c_memory_read(i2c_id_t id, const i2c_mem_param_t *mem_param)
694 {
695 I2C_RETURN_ON_NOT_INIT();
696 I2C_RETURN_ON_ID_NOT_INIT(id);
697 BK_RETURN_ON_ERR(i2c_wait_sm_bus_idle(id, mem_param->timeout_ms));
698
699 uint32_t int_level = rtos_disable_int();
700 s_i2c[id].work_mode = I2C_MASTER_READ;
701 s_i2c[id].is_with_mem_addr = true;
702 s_i2c[id].dev_addr = mem_param->dev_addr;
703 s_i2c[id].mem_addr = mem_param->mem_addr;
704 s_i2c[id].mem_addr_size = mem_param->mem_addr_size;
705 s_i2c[id].data_ptr = mem_param->data;
706 s_i2c[id].data_size = mem_param->data_size;
707 s_i2c[id].data_offset = 0;
708 s_i2c[id].int_status = 0;
709 i2c_master_start(id);
710 i2c_master_set_write_dev_addr(id, mem_param->dev_addr);
711 i2c_hal_set_read_int_mode(&s_i2c[id].hal, mem_param->data_size);
712 rtos_enable_int(int_level);
713
714 rtos_get_semaphore(&s_i2c[id].rx_sema, mem_param->timeout_ms);
715
716 return BK_OK;
717 }
718
bk_i2c_set_baud_rate(i2c_id_t id,uint32_t baud_rate)719 bk_err_t bk_i2c_set_baud_rate(i2c_id_t id, uint32_t baud_rate)
720 {
721 I2C_RETURN_ON_NOT_INIT();
722 i2c_hal_set_baud_rate(&s_i2c[id].hal, baud_rate);
723 return BK_OK;
724 }
725
bk_i2c_set_slave_address(i2c_id_t id,uint16_t slave_addr)726 bk_err_t bk_i2c_set_slave_address(i2c_id_t id, uint16_t slave_addr)
727 {
728 I2C_RETURN_ON_NOT_INIT();
729 i2c_hal_set_slave_addr(&s_i2c[id].hal, slave_addr);
730 return BK_OK;
731 }
732
bk_i2c_enable_interrupt(i2c_id_t id)733 bk_err_t bk_i2c_enable_interrupt(i2c_id_t id)
734 {
735 #if (CONFIG_SYSTEM_CTRL)
736 i2c_interrupt_enable(id);
737 #else
738 icu_enable_i2c_interrupt(id);
739 #endif
740 return BK_OK;
741 }
742
bk_i2c_disable_interrupt(i2c_id_t id)743 bk_err_t bk_i2c_disable_interrupt(i2c_id_t id)
744 {
745 #if (CONFIG_SYSTEM_CTRL)
746 i2c_interrupt_disable(id);
747 #else
748 icu_disable_i2c_interrupt(id);
749 #endif
750 return BK_OK;
751 }
752
bk_i2c_is_bus_busy(i2c_id_t id)753 bool bk_i2c_is_bus_busy(i2c_id_t id)
754 {
755 return i2c_hal_is_busy(&s_i2c[id].hal);
756 }
757
bk_i2c_get_cur_action(i2c_id_t id)758 uint32_t bk_i2c_get_cur_action(i2c_id_t id)
759 {
760 return s_i2c[id].master_status;
761 }
762
i2c_master_isr_common(i2c_id_t id)763 static void i2c_master_isr_common(i2c_id_t id)
764 {
765 I2C_LOGD("s_i2c[id].master_status=%d\r\n", s_i2c[id].master_status);
766 switch (s_i2c[id].master_status) {
767 case I2C_START:
768 i2c_master_start(id);
769 break;
770 case I2C_TX_DEV_ADDR:
771 i2c_master_set_write_dev_addr(id, s_i2c[id].dev_addr);
772 break;
773 case I2C_RX_DEV_ADDR:
774 i2c_master_set_read_dev_addr(id, s_i2c[id].dev_addr);
775 break;
776 case I2C_TX_MEM_ADDR_HIGH_8BIT:
777 i2c_master_write_mem_addr_high_8bit(id, s_i2c[id].mem_addr);
778 break;
779 case I2C_TX_MEM_ADDR_LOW_8BIT:
780 i2c_master_write_mem_addr_low_8bit(id, s_i2c[id].mem_addr);
781 break;
782 case I2C_TX_DATA: {
783 if (id == I2C_ID_0) {
784 #if (CONFIG_FM_I2C)
785 i2c0_master_write_data(id);
786 #else
787 i2c1_master_write_data(id);
788 #endif
789
790 } else {
791 i2c1_master_write_data(id);
792 }
793 break;
794 }
795 case I2C_RX_DATA: {
796 if (id == I2C_ID_0) {
797 #if (CONFIG_FM_I2C)
798 i2c0_master_read_data(id);
799 #else
800 i2c1_master_read_data(id);
801 #endif
802 } else {
803 i2c1_master_read_data(id);
804 }
805 break;
806 }
807 case I2C_STOP:
808 i2c_master_stop(id);
809 break;
810 default:
811 s_i2c[id].master_status = I2C_IDLE;
812 break;
813 }
814 }
815
816 #if CONFIG_FM_I2C
i2c0_isr_common(i2c_id_t id)817 static void i2c0_isr_common(i2c_id_t id)
818 {
819 i2c_hal_t *hal = &s_i2c[id].hal;
820 uint32_t int_status = 0;
821
822 int_status = i2c_hal_get_interrupt_status(hal);
823 I2C_LOGD("isr_i2c0_config:0x%x\r\n", int_status);
824 if(!i2c_hal_is_sm_int_triggered(hal, int_status)) {
825 I2C_LOGW("sm bus int not triggered\r\n");
826 return;
827 }
828
829 switch (s_i2c[id].work_mode) {
830 case I2C_MASTER_WRITE: {
831 if (!i2c_hal_is_rx_ack_triggered(hal, int_status)) {
832 I2C_LOGW("i2c(%d) master_write get ack failed\r\n", id);
833 i2c_transtate_set(id);
834 i2c_master_stop(id);
835 rtos_set_semaphore(&s_i2c[id].tx_sema);
836 break;
837 }
838 i2c_master_isr_common(id);
839 break;
840 }
841 case I2C_MASTER_READ: {
842 if (s_i2c[id].master_status != I2C_RX_DATA &&
843 !i2c_hal_is_rx_ack_triggered(hal, int_status)) {
844 I2C_LOGW("i2c(%d) master_read get ack failed\r\n", id);
845 i2c_transtate_set(id);
846 i2c_master_stop(id);
847 rtos_set_semaphore(&s_i2c[id].rx_sema);
848 break;
849 }
850 if (i2c_hal_is_start_triggered(hal, int_status) &&
851 !i2c_hal_is_rx_ack_triggered(hal, int_status)) {
852 I2C_LOGW("i2c_read get ack failed\r\n");
853 i2c_transtate_set(id);
854 i2c_master_stop(id);
855 rtos_set_semaphore(&s_i2c[id].rx_sema);
856 break;
857 }
858 i2c_master_isr_common(id);
859 break;
860 }
861 default:
862 break;
863 }
864 /* must clear SI at last,otherwise slave_addr will be sent twice */
865 i2c_hal_clear_interrupt_status(hal, int_status);
866 }
867 #endif
868
i2c1_isr_common(i2c_id_t id)869 static void i2c1_isr_common(i2c_id_t id)
870 {
871 i2c_hal_t *hal = &s_i2c[id].hal;
872 uint32_t int_status = s_i2c[id].int_status;
873 uint32_t data_num = 0;
874 uint32_t remain_size = 0;
875
876 int_status = i2c_hal_get_interrupt_status(hal);
877 s_i2c[id].int_status = int_status;
878 I2C_LOGD("isr_i2c1_status:%x\r\n", int_status);
879
880 if(!i2c_hal_is_sm_int_triggered(hal, int_status)) {
881 if (i2c_hal_is_scl_timeout_triggered(hal, int_status)) {
882 I2C_LOGW("SCL timeout triggered, restart i2c\r\n");
883 s_i2c[id].master_status = I2C_IDLE;
884 /* i2c must close->open when SCL low timeout triggered */
885 i2c_hal_disable(hal);
886 i2c_hal_enable(hal);
887 }
888 if (i2c_hal_is_arb_lost_triggered(hal, int_status)) {
889 I2C_LOGW("arb lost int triggered\r\n");
890 }
891 return;
892 }
893
894 switch (s_i2c[id].work_mode) {
895 case I2C_MASTER_WRITE: {
896 s_i2c[id].int_status &= ~I2C1_F_START;
897 /* send stop if not receive ack */
898 if (!i2c_hal_is_rx_ack_triggered(hal, int_status)) {
899 I2C_LOGW("i2c(%d) master_write get ack failed\r\n", id);
900 i2c_transtate_set(id);
901 i2c_master_stop(id);
902 rtos_set_semaphore(&s_i2c[id].tx_sema);
903 break;
904 }
905 i2c_master_isr_common(id);
906 break;
907 }
908 case I2C_MASTER_READ: {
909 s_i2c[id].int_status &= ~I2C1_F_START;
910 if (i2c_hal_is_start_triggered(hal, int_status) &&
911 !i2c_hal_is_rx_ack_triggered(hal, int_status)) {
912 I2C_LOGW("i2c(%d) master_read get ack failed\r\n", id);
913 s_i2c[id].master_status = I2C_IDLE;
914 s_i2c[id].int_status |= I2C1_F_STOP;
915 rtos_set_semaphore(&s_i2c[id].rx_sema);
916 break;
917 }
918 i2c_master_isr_common(id);
919 break;
920 }
921 case I2C_SLAVE_WRITE:
922 if (i2c_hal_is_stop_triggered(hal, int_status) || i2c_hal_is_rx_mode(hal)) {
923 I2C_LOGI("i2c(%d) slave_write get stopped\r\n", id);
924 rtos_set_semaphore(&s_i2c[id].tx_sema);
925 break;
926 }
927 if (i2c_hal_is_addr_matched(hal)) {
928 s_i2c[id].int_status |= I2C1_F_ACK;
929 }
930 if (i2c_hal_is_rx_ack_triggered(hal, int_status)) {
931 i2c_hal_write_byte(hal, s_i2c[id].data_ptr[(s_i2c[id].data_offset)++]);
932 if (s_i2c[id].data_offset == s_i2c[id].data_size) {
933 I2C_LOGW("i2c(%d) slave_write data_offset==data_size\r\n", id);
934 }
935 }
936 break;
937 case I2C_SLAVE_READ:
938 if (i2c_hal_is_stop_triggered(hal, int_status)) {
939 I2C_LOGI("i2c(%d) slave_read get stopped\r\n", id);
940 rtos_set_semaphore(&s_i2c[id].rx_sema);
941 break;
942 }
943 if (i2c_hal_is_addr_matched(hal)) {
944 s_i2c[id].int_status |= I2C1_F_ACK;
945 break;
946 }
947 remain_size = s_i2c[id].data_size - s_i2c[id].data_offset;
948 data_num = i2c_hal_get_read_fifo_num(hal);
949 for (uint32_t i = 0; i < data_num; i++) {
950 s_i2c[id].data_ptr[(s_i2c[id].data_offset)++] = i2c_hal_read_byte(hal);
951 remain_size--;
952 if (!remain_size) { /* avoid index is out of array range */
953 break;
954 }
955 }
956 if (!remain_size) {
957 s_i2c[id].int_status &= ~I2C1_F_ACK;
958 rtos_set_semaphore(&s_i2c[id].rx_sema);
959 } else if (remain_size < data_num) {
960 s_i2c[id].int_status |= (I2C1_F_ACK | I2C1_F_INT_MODE_V);
961 } else {
962 s_i2c[id].int_status |= I2C1_F_ACK;
963 }
964 break;
965 default:
966 break;
967 }
968 /* int_status sm_int/ack/start/stop/int_mode must operate together, otherwise will not work
969 * e.g.
970 * i2c_hal_enable_ack(); // only set bit of ack(bit[8]), no ack will be sent
971 */
972 i2c_hal_clear_interrupt_status(hal, s_i2c[id].int_status);
973 }
974
i2c0_isr(void)975 static void i2c0_isr(void)
976 {
977 I2C_LOGD("enter i2c0_isr\r\n");
978 #if CONFIG_FM_I2C
979 i2c0_isr_common(I2C_ID_0);
980 #else
981 i2c1_isr_common(I2C_ID_0);
982 #endif
983 }
984
985 #if (SOC_I2C_UNIT_NUM > 1)
i2c1_isr(void)986 static void i2c1_isr(void)
987 {
988 I2C_LOGD("enter i2c1_isr\r\n");
989 i2c1_isr_common(I2C_ID_1);
990 }
991 #endif
992
993 #if (SOC_I2C_UNIT_NUM > 2)
i2c2_isr(void)994 static void i2c2_isr(void)
995 {
996 I2C_LOGD("enter i2c2_isr\r\n");
997 i2c1_isr_common(I2C_ID_2);
998 }
999 #endif
1000
1001