1 // Copyright (C) 2022 Beken Corporation
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #include <common/bk_include.h>
16 #include "i2s_hal.h"
17 #include "i2s_driver.h"
18 #include "sys_driver.h"
19 #include "clock_driver.h"
20 #include <soc/soc.h>
21 #include <driver/i2s_types.h>
22 #include <os/os.h>
23 #include <os/mem.h>
24 #include <driver/int.h>
25 #include "gpio_driver.h"
26 #include <driver/gpio.h>
27 #include <modules/pm.h>
28
29 typedef struct {
30 i2s_isr_t callback;
31 void *param;
32 } i2s_callback_t;
33
34
35 #define I2S_RETURN_ON_NOT_INIT() do {\
36 if (!s_i2s_driver_is_init) {\
37 return BK_ERR_I2S_NOT_INIT;\
38 }\
39 } while(0)
40
41 #define I2S_RETURN_ON_INVALID_ISR_ID(isr_id) do {\
42 if ((isr_id) >= SOC_I2S_ISR_NUM) {\
43 return BK_ERR_I2S_ISR_ID;\
44 }\
45 } while(0)
46
47
48 static bool s_i2s_driver_is_init = false;
49 static i2s_callback_t s_i2s_isr[SOC_I2S_ISR_NUM] = {NULL};
50 //static i2s_driver_t driver_i2s;
51 static i2s_role_t i2s_role = I2S_ROLE_MAX;
52
53 static void i2s_isr(void);
54 extern void delay(int num);//TODO fix me
55
56
i2s_init_gpio(i2s_gpio_group_id_t id)57 static void i2s_init_gpio(i2s_gpio_group_id_t id)
58 {
59 switch(id)
60 {
61 case I2S_GPIO_GROUP_0:
62 gpio_dev_unmap(GPIO_6);
63 gpio_dev_map(GPIO_6, GPIO_DEV_I2S1_CLK);
64 gpio_dev_unmap(GPIO_7);
65 gpio_dev_map(GPIO_7, GPIO_DEV_I2S1_SYNC);
66 gpio_dev_unmap(GPIO_8);
67 gpio_dev_map(GPIO_8, GPIO_DEV_I2S1_DIN);
68 gpio_dev_unmap(GPIO_9);
69 gpio_dev_map(GPIO_9, GPIO_DEV_I2S1_DOUT);
70 gpio_dev_unmap(GPIO_28);
71 gpio_dev_map(GPIO_28, GPIO_DEV_I2S1_MCLK);
72 bk_gpio_disable_output(GPIO_28);
73 break;
74
75 case I2S_GPIO_GROUP_1:
76 gpio_dev_unmap(GPIO_40);
77 gpio_dev_map(GPIO_40, GPIO_DEV_I2S1_CLK);
78 bk_gpio_disable_output(GPIO_40);
79 gpio_dev_unmap(GPIO_41);
80 gpio_dev_map(GPIO_41, GPIO_DEV_I2S1_SYNC);
81 bk_gpio_disable_output(GPIO_41);
82 gpio_dev_unmap(GPIO_42);
83 gpio_dev_map(GPIO_42, GPIO_DEV_I2S1_DIN);
84 bk_gpio_disable_output(GPIO_42);
85 gpio_dev_unmap(GPIO_43);
86 gpio_dev_map(GPIO_43, GPIO_DEV_I2S1_DOUT);
87 bk_gpio_disable_output(GPIO_43);
88 gpio_dev_unmap(GPIO_28);
89 gpio_dev_map(GPIO_28, GPIO_DEV_I2S1_MCLK);
90 bk_gpio_disable_output(GPIO_28);
91 break;
92
93 default:
94 break;
95 }
96 }
97
bk_i2s_driver_init(void)98 bk_err_t bk_i2s_driver_init(void)
99 {
100 if (s_i2s_driver_is_init)
101 return BK_OK;
102
103 //power on
104 bk_pm_module_vote_power_ctrl(PM_POWER_SUB_MODULE_NAME_AUDP_I2S, PM_POWER_MODULE_STATE_ON);
105 //sys_drv_aud_power_en(0); //temp used
106
107 //select 26M XTAL clock and enable i2s clock
108 sys_drv_i2s_select_clock(1);
109 //sys_drv_i2s_clock_en(1);
110 bk_pm_clock_ctrl(PM_CLK_ID_I2S_1, CLK_PWR_CTRL_PWR_UP);
111
112 //i2s_disckg always on
113 sys_drv_i2s_disckg_set(1);
114
115 //set apll clock config
116 sys_drv_apll_en(1);
117 sys_drv_cb_manu_val_set(0x14);
118 sys_drv_ana_reg11_vsel_set(7);
119
120 //enable i2s interrupt
121 sys_drv_i2s_int_en(1);
122
123 os_memset(&s_i2s_isr, 0, sizeof(s_i2s_isr));
124
125 //register fft isr
126 i2s_int_config_t int_config_table = {INT_SRC_I2S, i2s_isr};
127 bk_int_isr_register(int_config_table.int_src, int_config_table.isr, NULL);
128 s_i2s_driver_is_init = true;
129
130 return BK_OK;
131 }
132
bk_i2s_driver_deinit(void)133 bk_err_t bk_i2s_driver_deinit(void)
134 {
135 //power down
136 bk_pm_module_vote_power_ctrl(PM_POWER_SUB_MODULE_NAME_AUDP_I2S, PM_POWER_MODULE_STATE_OFF);
137 //sys_drv_i2s_clock_en(0);
138 bk_pm_clock_ctrl(PM_CLK_ID_I2S_1, CLK_PWR_CTRL_PWR_DOWN);
139
140 //i2s_disckg not always on
141 sys_drv_i2s_disckg_set(0);
142 //disable i2s interrupt
143 sys_drv_i2s_int_en(0);
144
145 //set apll clock config
146 sys_drv_apll_en(0);
147 sys_drv_cb_manu_val_set(0x10);
148 sys_drv_ana_reg11_vsel_set(5);
149
150 i2s_int_config_t int_config_table = {INT_SRC_I2S, i2s_isr};
151 bk_int_isr_unregister(int_config_table.int_src);
152 s_i2s_driver_is_init = false;
153
154 return BK_OK;
155 }
156
bk_i2s_init(i2s_gpio_group_id_t id,const i2s_config_t * config)157 bk_err_t bk_i2s_init(i2s_gpio_group_id_t id, const i2s_config_t *config)
158 {
159 I2S_RETURN_ON_NOT_INIT();
160 if (!config)
161 return BK_ERR_I2S_PARAM;
162
163 i2s_init_gpio(id);
164 i2s_hal_config(config);
165 i2s_role = config->role;
166
167 return BK_OK;
168 }
169
bk_i2s_deinit(void)170 bk_err_t bk_i2s_deinit(void)
171 {
172 I2S_RETURN_ON_NOT_INIT();
173
174 i2s_hal_deconfig();
175 i2s_role = I2S_ROLE_MAX;
176
177 return BK_OK;
178 }
179
bk_i2s_get_read_ready(uint32_t * read_flag)180 bk_err_t bk_i2s_get_read_ready(uint32_t *read_flag)
181 {
182 I2S_RETURN_ON_NOT_INIT();
183
184 i2s_hal_read_ready_get(read_flag);
185 return BK_OK;
186 }
187
bk_i2s_get_write_ready(uint32_t * write_flag)188 bk_err_t bk_i2s_get_write_ready(uint32_t *write_flag)
189 {
190 I2S_RETURN_ON_NOT_INIT();
191
192 i2s_hal_write_ready_get(write_flag);
193 return BK_OK;
194 }
195
bk_i2s_enable(i2s_en_t en_value)196 bk_err_t bk_i2s_enable(i2s_en_t en_value)
197 {
198 I2S_RETURN_ON_NOT_INIT();
199
200 i2s_hal_en_set(en_value);
201 return BK_OK;
202 }
203
bk_i2s_int_enable(i2s_isr_id_t int_id,uint32_t value)204 bk_err_t bk_i2s_int_enable(i2s_isr_id_t int_id, uint32_t value)
205 {
206 I2S_RETURN_ON_NOT_INIT();
207
208 i2s_hal_int_set(int_id, value);
209 return BK_OK;
210 }
211
bk_i2s_set_role(i2s_role_t role)212 bk_err_t bk_i2s_set_role(i2s_role_t role)
213 {
214 I2S_RETURN_ON_NOT_INIT();
215
216 i2s_hal_role_set(role);
217 return BK_OK;
218 }
219
bk_i2s_set_work_mode(i2s_work_mode_t work_mode)220 bk_err_t bk_i2s_set_work_mode(i2s_work_mode_t work_mode)
221 {
222 I2S_RETURN_ON_NOT_INIT();
223
224 i2s_hal_work_mode_set(work_mode);
225 return BK_OK;
226 }
227
bk_i2s_set_lrck_invert(i2s_lrck_invert_en_t lrckrp)228 bk_err_t bk_i2s_set_lrck_invert(i2s_lrck_invert_en_t lrckrp)
229 {
230 I2S_RETURN_ON_NOT_INIT();
231
232 i2s_hal_lrck_invert_set(lrckrp);
233 return BK_OK;
234 }
235
bk_i2s_set_sck_invert(i2s_sck_invert_en_t sck_invert)236 bk_err_t bk_i2s_set_sck_invert(i2s_sck_invert_en_t sck_invert)
237 {
238 I2S_RETURN_ON_NOT_INIT();
239
240 i2s_hal_sck_invert_set(sck_invert);
241 return BK_OK;
242 }
243
bk_i2s_set_lsb_first(i2s_lsb_first_en_t lsb_first)244 bk_err_t bk_i2s_set_lsb_first(i2s_lsb_first_en_t lsb_first)
245 {
246 I2S_RETURN_ON_NOT_INIT();
247
248 i2s_hal_lsb_first_set(lsb_first);
249 return BK_OK;
250 }
251
bk_i2s_set_sync_len(uint32_t sync_len)252 bk_err_t bk_i2s_set_sync_len(uint32_t sync_len)
253 {
254 I2S_RETURN_ON_NOT_INIT();
255
256 i2s_hal_sync_len_set(sync_len);
257 return BK_OK;
258 }
259
bk_i2s_set_data_len(uint32_t data_len)260 bk_err_t bk_i2s_set_data_len(uint32_t data_len)
261 {
262 I2S_RETURN_ON_NOT_INIT();
263
264 i2s_hal_data_len_set(data_len);
265 return BK_OK;
266 }
267
bk_i2s_set_pcm_dlen(uint32_t pcm_dlen)268 bk_err_t bk_i2s_set_pcm_dlen(uint32_t pcm_dlen)
269 {
270 I2S_RETURN_ON_NOT_INIT();
271
272 i2s_hal_pcm_dlen_set(pcm_dlen);
273 return BK_OK;
274 }
275
bk_i2s_set_store_mode(i2s_lrcom_store_mode_t store_mode)276 bk_err_t bk_i2s_set_store_mode(i2s_lrcom_store_mode_t store_mode)
277 {
278 I2S_RETURN_ON_NOT_INIT();
279
280 i2s_hal_store_mode_set(store_mode);
281 return BK_OK;
282 }
283
bk_i2s_clear_rxfifo(void)284 bk_err_t bk_i2s_clear_rxfifo(void)
285 {
286 I2S_RETURN_ON_NOT_INIT();
287
288 i2s_hal_rxfifo_clear();
289 return BK_OK;
290 }
291
bk_i2s_clear_txfifo(void)292 bk_err_t bk_i2s_clear_txfifo(void)
293 {
294 I2S_RETURN_ON_NOT_INIT();
295
296 i2s_hal_txfifo_clear();
297 return BK_OK;
298 }
299
bk_i2s_clear_txudf_int(i2s_channel_id_t channel_id)300 bk_err_t bk_i2s_clear_txudf_int(i2s_channel_id_t channel_id)
301 {
302 I2S_RETURN_ON_NOT_INIT();
303
304 i2s_hal_txudf_int_clear(channel_id);
305 return BK_OK;
306 }
307
bk_i2s_clear_rxovf_int(i2s_channel_id_t channel_id)308 bk_err_t bk_i2s_clear_rxovf_int(i2s_channel_id_t channel_id)
309 {
310 I2S_RETURN_ON_NOT_INIT();
311
312 i2s_hal_rxovf_int_clear(channel_id);
313 return BK_OK;
314 }
315
bk_i2s_set_txint_level(i2s_txint_level_t txint_level)316 bk_err_t bk_i2s_set_txint_level(i2s_txint_level_t txint_level)
317 {
318 I2S_RETURN_ON_NOT_INIT();
319
320 i2s_hal_txint_level_set(txint_level);
321 return BK_OK;
322 }
323
bk_i2s_set_rxint_level(i2s_rxint_level_t rxint_level)324 bk_err_t bk_i2s_set_rxint_level(i2s_rxint_level_t rxint_level)
325 {
326 I2S_RETURN_ON_NOT_INIT();
327
328 i2s_hal_rxint_level_set(rxint_level);
329 return BK_OK;
330 }
331
bk_i2s_write_data(uint32_t channel_id,uint32_t * data_buf,uint32_t data_len)332 bk_err_t bk_i2s_write_data(uint32_t channel_id, uint32_t *data_buf, uint32_t data_len)
333 {
334 uint32_t i = 0;
335 I2S_RETURN_ON_NOT_INIT();
336
337 for (i=0; i<data_len; i++)
338 i2s_hal_data_write(channel_id, data_buf[i]);
339 return BK_OK;
340 }
341
bk_i2s_read_data(uint32_t * data_buf,uint32_t data_len)342 bk_err_t bk_i2s_read_data(uint32_t *data_buf, uint32_t data_len)
343 {
344 uint32_t i = 0;
345 I2S_RETURN_ON_NOT_INIT();
346
347 for (i=0; i<data_len; i++)
348 i2s_hal_data_read(&data_buf[i]);
349 return BK_OK;
350 }
351
bk_i2s_get_data_addr(uint32_t * i2s_data_addr)352 bk_err_t bk_i2s_get_data_addr(uint32_t *i2s_data_addr)
353 {
354 I2S_RETURN_ON_NOT_INIT();
355
356 *i2s_data_addr = I2S_REG0X3_ADDR;
357 return BK_OK;
358 }
359
bk_i2s_set_ratio(i2s_rate_t * rate)360 bk_err_t bk_i2s_set_ratio(i2s_rate_t *rate)
361 {
362 //SOC_I2S_APLL_RATE
363 uint32_t i = 0;
364 uint32_t smp_ratio = 0;
365 uint32_t bit_ratio = 0;
366 uint32_t apll_clk = 0;
367
368 const i2s_rate_table_node_t i2s_rate_table [] = {
369 //8000
370 {I2S_SAMP_RATE_8000, I2S_DATA_WIDTH_16, 98304000, 15, 192},
371 {I2S_SAMP_RATE_8000, I2S_DATA_WIDTH_24, 98304000, 23, 128},
372 {I2S_SAMP_RATE_8000, I2S_DATA_WIDTH_32, 98304000, 31, 96},
373
374 //12000
375 {I2S_SAMP_RATE_12000, I2S_DATA_WIDTH_16, 98304000, 15, 128},
376 {I2S_SAMP_RATE_12000, I2S_DATA_WIDTH_32, 98304000, 31, 64},
377
378 //16000
379 {I2S_SAMP_RATE_16000, I2S_DATA_WIDTH_16, 98304000, 15, 96},
380 {I2S_SAMP_RATE_16000, I2S_DATA_WIDTH_24, 98304000, 23, 64},
381 {I2S_SAMP_RATE_16000, I2S_DATA_WIDTH_32, 98304000, 31, 48},
382
383 //24000
384 {I2S_SAMP_RATE_24000, I2S_DATA_WIDTH_16, 98304000, 15, 64},
385 {I2S_SAMP_RATE_24000, I2S_DATA_WIDTH_32, 98304000, 31, 32},
386
387 //32000
388 {I2S_SAMP_RATE_32000, I2S_DATA_WIDTH_16, 98304000, 15, 48},
389 {I2S_SAMP_RATE_32000, I2S_DATA_WIDTH_24, 98304000, 23, 32},
390 {I2S_SAMP_RATE_32000, I2S_DATA_WIDTH_32, 98304000, 31, 24},
391
392 //48000
393 {I2S_SAMP_RATE_48000, I2S_DATA_WIDTH_16, 98304000, 15, 32},
394 {I2S_SAMP_RATE_48000, I2S_DATA_WIDTH_32, 98304000, 31, 16},
395
396 //96000
397 {I2S_SAMP_RATE_96000, I2S_DATA_WIDTH_16, 98304000, 15, 16},
398 {I2S_SAMP_RATE_96000, I2S_DATA_WIDTH_32, 98304000, 31, 8},
399
400 //8018.2
401 {I2S_SAMP_RATE_8018, I2S_DATA_WIDTH_16, 90316800, 15, 176},
402 {I2S_SAMP_RATE_8018, I2S_DATA_WIDTH_32, 90316800, 31, 88},
403
404 //11025
405 {I2S_SAMP_RATE_11025, I2S_DATA_WIDTH_16, 90316800, 15, 128},
406 {I2S_SAMP_RATE_11025, I2S_DATA_WIDTH_32, 90316800, 31, 64},
407
408 //22050
409 {I2S_SAMP_RATE_22050, I2S_DATA_WIDTH_16, 90316800, 15, 64},
410 {I2S_SAMP_RATE_22050, I2S_DATA_WIDTH_32, 90316800, 31, 32},
411
412 //44100
413 {I2S_SAMP_RATE_44100, I2S_DATA_WIDTH_16, 90316800, 15, 32},
414 {I2S_SAMP_RATE_44100, I2S_DATA_WIDTH_32, 90316800, 31, 16},
415
416 //88200
417 {I2S_SAMP_RATE_88200, I2S_DATA_WIDTH_16, 90316800, 15, 16},
418 {I2S_SAMP_RATE_88200, I2S_DATA_WIDTH_32, 90316800, 31, 8},
419 };
420
421 I2S_RETURN_ON_NOT_INIT();
422
423 for (i = 0; i < sizeof(i2s_rate_table)/sizeof(i2s_rate_table_node_t); i++)
424 {
425 if ((rate->samp_rate == i2s_rate_table[i].samp_rate) && (rate->datawidth == i2s_rate_table[i].datawidth)) {
426 smp_ratio = i2s_rate_table[i].smp_ratio;
427 bit_ratio = i2s_rate_table[i].bit_ratio;
428 apll_clk = i2s_rate_table[i].sys_clk;
429 break;
430 }
431 }
432
433 if (smp_ratio == 0) {
434 I2S_LOGI("cannot find ratio value to use, please check rate parameters \r\n");
435 return BK_ERR_I2S_PARAM;
436 }
437
438 if (apll_clk == 98304000)
439 sys_drv_ana_reg10_sdm_val_set(0xF1FAA45);
440 else if (apll_clk == 90316800)
441 sys_drv_ana_reg10_sdm_val_set(0xDE517A9);
442 else
443 sys_drv_ana_reg10_sdm_val_set(0xF1FAA45);
444 sys_drv_ana_reg11_spi_trigger_set(1);
445 delay(10);
446 sys_drv_ana_reg11_spi_trigger_set(0);
447
448 if (smp_ratio > 0x1F) {
449 i2s_hal_sample_ratio_set(smp_ratio & 0x1F);
450 i2s_hal_sample_ratio_h2b_set((smp_ratio >> 5) & 0x3);
451 } else {
452 i2s_hal_sample_ratio_set(smp_ratio);
453 }
454 if (bit_ratio > 0xFF) {
455 i2s_hal_sck_ratio_set(bit_ratio & 0xFF);
456 i2s_hal_sck_ratio_h4b_set((bit_ratio >> 8) & 0xF);
457 } else {
458 i2s_hal_sck_ratio_set(bit_ratio);
459 }
460
461 return BK_OK;
462 }
463
464 /* register i2s interrupt */
bk_i2s_register_i2s_isr(i2s_isr_id_t isr_id,i2s_isr_t isr,void * param)465 bk_err_t bk_i2s_register_i2s_isr(i2s_isr_id_t isr_id, i2s_isr_t isr, void *param)
466 {
467 I2S_RETURN_ON_NOT_INIT();
468 I2S_RETURN_ON_INVALID_ISR_ID(isr_id);
469 uint32_t int_level = rtos_disable_int();
470 s_i2s_isr[isr_id].callback = isr;
471 s_i2s_isr[isr_id].param = param;
472 rtos_enable_int(int_level);
473
474 return BK_OK;
475 }
476
i2s_isr(void)477 void i2s_isr(void)
478 {
479 i2s_int_status_t i2s_status = {0};
480 i2s_status.channel_id = I2S_CHANNEL_1;
481 i2s_hal_int_status_get(&i2s_status);
482
483 if (i2s_status.tx_udf) {
484 i2s_hal_txudf_int_clear(I2S_CHANNEL_1);
485 if (s_i2s_isr[I2S_ISR_CHL1_TXUDF].callback) {
486 s_i2s_isr[I2S_ISR_CHL1_TXUDF].callback(s_i2s_isr[I2S_ISR_CHL1_TXUDF].param);
487 }
488 }
489
490 if (i2s_status.rx_ovf) {
491 i2s_hal_rxovf_int_clear(I2S_CHANNEL_1);
492 if (s_i2s_isr[I2S_ISR_CHL1_RXOVF].callback) {
493 s_i2s_isr[I2S_ISR_CHL1_RXOVF].callback(s_i2s_isr[I2S_ISR_CHL1_RXOVF].param);
494 }
495 }
496
497 if (i2s_status.tx_int) {
498 if (s_i2s_isr[I2S_ISR_CHL1_TXINT].callback) {
499 s_i2s_isr[I2S_ISR_CHL1_TXINT].callback(s_i2s_isr[I2S_ISR_CHL1_TXINT].param);
500 }
501 }
502
503 if (i2s_status.rx_int) {
504 if (s_i2s_isr[I2S_ISR_CHL1_RXINT].callback) {
505 s_i2s_isr[I2S_ISR_CHL1_RXINT].callback(s_i2s_isr[I2S_ISR_CHL1_RXINT].param);
506 }
507 }
508
509 os_memset(&i2s_status, 0, sizeof(i2s_status));
510 i2s_status.channel_id = I2S_CHANNEL_2;
511 i2s_hal_int_status_get(&i2s_status);
512 if (i2s_status.tx_udf) {
513 i2s_hal_txudf_int_clear(I2S_CHANNEL_2);
514 if (s_i2s_isr[I2S_ISR_CHL2_TXUDF].callback) {
515 s_i2s_isr[I2S_ISR_CHL2_TXUDF].callback(s_i2s_isr[I2S_ISR_CHL2_TXUDF].param);
516 }
517 }
518
519 if (i2s_status.rx_ovf) {
520 i2s_hal_rxovf_int_clear(I2S_CHANNEL_2);
521 if (s_i2s_isr[I2S_ISR_CHL2_RXOVF].callback) {
522 s_i2s_isr[I2S_ISR_CHL2_RXOVF].callback(s_i2s_isr[I2S_ISR_CHL2_RXOVF].param);
523 }
524 }
525
526 if (i2s_status.tx_int) {
527 if (s_i2s_isr[I2S_ISR_CHL2_TXINT].callback) {
528 s_i2s_isr[I2S_ISR_CHL2_TXINT].callback(s_i2s_isr[I2S_ISR_CHL2_TXINT].param);
529 }
530 }
531
532 if (i2s_status.rx_int) {
533 if (s_i2s_isr[I2S_ISR_CHL2_RXINT].callback) {
534 s_i2s_isr[I2S_ISR_CHL2_RXINT].callback(s_i2s_isr[I2S_ISR_CHL2_RXINT].param);
535 }
536 }
537
538 os_memset(&i2s_status, 0, sizeof(i2s_status));
539 i2s_status.channel_id = I2S_CHANNEL_3;
540 i2s_hal_int_status_get(&i2s_status);
541 if (i2s_status.tx_udf) {
542 i2s_hal_txudf_int_clear(I2S_CHANNEL_3);
543 if (s_i2s_isr[I2S_ISR_CHL3_TXUDF].callback) {
544 s_i2s_isr[I2S_ISR_CHL3_TXUDF].callback(s_i2s_isr[I2S_ISR_CHL3_TXUDF].param);
545 }
546 }
547
548 if (i2s_status.rx_ovf) {
549 i2s_hal_rxovf_int_clear(I2S_CHANNEL_3);
550 if (s_i2s_isr[I2S_ISR_CHL3_RXOVF].callback) {
551 s_i2s_isr[I2S_ISR_CHL3_RXOVF].callback(s_i2s_isr[I2S_ISR_CHL3_RXOVF].param);
552 }
553 }
554
555 if (i2s_status.tx_int) {
556 if (s_i2s_isr[I2S_ISR_CHL3_TXINT].callback) {
557 s_i2s_isr[I2S_ISR_CHL3_TXINT].callback(s_i2s_isr[I2S_ISR_CHL3_TXINT].param);
558 }
559 }
560
561 if (i2s_status.rx_int) {
562 if (s_i2s_isr[I2S_ISR_CHL3_RXINT].callback) {
563 s_i2s_isr[I2S_ISR_CHL3_RXINT].callback(s_i2s_isr[I2S_ISR_CHL3_RXINT].param);
564 }
565 }
566
567 os_memset(&i2s_status, 0, sizeof(i2s_status));
568 i2s_status.channel_id = I2S_CHANNEL_4;
569 i2s_hal_int_status_get(&i2s_status);
570 if (i2s_status.tx_udf) {
571 i2s_hal_txudf_int_clear(I2S_CHANNEL_4);
572 if (s_i2s_isr[I2S_ISR_CHL4_TXUDF].callback) {
573 s_i2s_isr[I2S_ISR_CHL4_TXUDF].callback(s_i2s_isr[I2S_ISR_CHL4_TXUDF].param);
574 }
575 }
576
577 if (i2s_status.rx_ovf) {
578 i2s_hal_rxovf_int_clear(I2S_CHANNEL_4);
579 if (s_i2s_isr[I2S_ISR_CHL4_RXOVF].callback) {
580 s_i2s_isr[I2S_ISR_CHL4_RXOVF].callback(s_i2s_isr[I2S_ISR_CHL4_RXOVF].param);
581 }
582 }
583
584 if (i2s_status.tx_int) {
585 if (s_i2s_isr[I2S_ISR_CHL4_TXINT].callback) {
586 s_i2s_isr[I2S_ISR_CHL4_TXINT].callback(s_i2s_isr[I2S_ISR_CHL4_TXINT].param);
587 }
588 }
589
590 if (i2s_status.rx_int) {
591 if (s_i2s_isr[I2S_ISR_CHL4_RXINT].callback) {
592 s_i2s_isr[I2S_ISR_CHL4_RXINT].callback(s_i2s_isr[I2S_ISR_CHL4_RXINT].param);
593 }
594 }
595
596 }
597
598