1 // Copyright (C) 2022 Beken Corporation
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #include <driver/dma.h>
16 #include <driver/int.h>
17 #include <driver/gpio.h>
18 #include <os/mem.h>
19 #include <driver/jpeg_enc.h>
20 #include "clock_driver.h"
21 #include "gpio_driver.h"
22 #include "jpeg_driver.h"
23 #include "jpeg_hal.h"
24 #include "power_driver.h"
25 #include "sys_driver.h"
26 #include <modules/pm.h>
27
28 typedef struct {
29 jpeg_isr_t isr_handler;
30 void *param;
31 } jpeg_isr_handler_t;
32
33 typedef struct {
34 jpeg_hal_t hal;
35 jpeg_isr_handler_t jpeg_isr_handler[ISR_MAX];
36 } jpeg_driver_t;
37
38 #define JPEG_RETURN_ON_NOT_INIT() do {\
39 if (!s_jpeg_driver_is_init) {\
40 return BK_ERR_JPEG_NOT_INIT;\
41 }\
42 } while(0)
43
44 static uint8_t jpeg_dma_rx_id = 0;
45 static jpeg_driver_t s_jpeg = {0};
46 static bool s_jpeg_driver_is_init = false;
47
48 static void jpeg_isr(void);
49
50 #if (CONFIG_SYSTEM_CTRL)
jpeg_power_config_set(const jpeg_config_t * config)51 static void jpeg_power_config_set(const jpeg_config_t *config)
52 {
53 sys_drv_set_jpeg_clk_sel(1);
54 sys_drv_set_clk_div_mode1_clkdiv_jpeg(config->sys_clk_div);
55 sys_drv_set_jpeg_disckg(1);
56 bk_pm_clock_ctrl(PM_CLK_ID_JPEG, CLK_PWR_CTRL_PWR_UP);
57 }
58 #endif
59
jpeg_init_gpio(void)60 static void jpeg_init_gpio(void)
61 {
62 jpeg_gpio_map_t jpeg_gpio_map_table[] = JPEG_GPIO_MAP;
63 #if (CONFIG_SYSTEM_CTRL)
64
65 for (uint32_t i = 0; i < 2; i++) {
66 gpio_dev_unmap(jpeg_gpio_map_table[i].gpio_id);
67 gpio_dev_map(jpeg_gpio_map_table[i].gpio_id, jpeg_gpio_map_table[i].dev);
68 if (i == 0) {
69 // enhance mclk capability
70 bk_gpio_set_capacity(jpeg_gpio_map_table[i].gpio_id, 3);
71 }
72 }
73 #else
74 for(uint32_t i = 0; i < JPEG_GPIO_PIN_NUMBER; i++) {
75 gpio_dev_unmap(jpeg_gpio_map_table[i].gpio_id);
76 gpio_dev_map(jpeg_gpio_map_table[i].gpio_id, jpeg_gpio_map_table[i].dev);
77 }
78 #endif
79 }
80
jpeg_deinit_gpio(void)81 static void jpeg_deinit_gpio(void)
82 {
83 jpeg_gpio_map_t jpeg_gpio_map_table[] = JPEG_GPIO_MAP;
84
85 for(uint32_t i = 0; i < JPEG_GPIO_PIN_NUMBER; i++) {
86 gpio_dev_unmap(jpeg_gpio_map_table[i].gpio_id);
87 }
88 }
89
jpeg_dma_rx_init(const jpeg_config_t * config)90 static void jpeg_dma_rx_init(const jpeg_config_t *config)
91 {
92 dma_config_t dma_config = {0};
93
94 if (config->yuv_mode == 0) {
95 dma_config.mode = DMA_WORK_MODE_REPEAT;
96 dma_config.chan_prio = 0;
97 dma_config.src.dev = DMA_DEV_JPEG;
98 dma_config.src.width = DMA_DATA_WIDTH_32BITS;
99 dma_config.src.start_addr = JPEG_R_RX_FIFO;
100 dma_config.dst.dev = DMA_DEV_DTCM;
101 dma_config.dst.width = DMA_DATA_WIDTH_32BITS;
102 dma_config.dst.addr_inc_en = DMA_ADDR_INC_ENABLE;
103 dma_config.dst.addr_loop_en = DMA_ADDR_LOOP_ENABLE;
104 dma_config.dst.start_addr = (uint32_t)config->rx_buf;
105 dma_config.dst.end_addr = (uint32_t)(config->rx_buf + config->rx_buf_len);
106 jpeg_dma_rx_id = config->dma_channel;
107
108 BK_LOG_ON_ERR(bk_dma_init(jpeg_dma_rx_id, &dma_config));
109 BK_LOG_ON_ERR(bk_dma_set_transfer_len(jpeg_dma_rx_id, config->node_len));
110 BK_LOG_ON_ERR(bk_dma_register_isr(jpeg_dma_rx_id, NULL, config->dma_rx_finish_handler));
111 BK_LOG_ON_ERR(bk_dma_enable_finish_interrupt(jpeg_dma_rx_id));
112 BK_LOG_ON_ERR(bk_dma_start(jpeg_dma_rx_id));
113 }
114 }
115
jpeg_dma_rx_deinit(void)116 static void jpeg_dma_rx_deinit(void)
117 {
118 BK_LOG_ON_ERR(bk_dma_stop(jpeg_dma_rx_id));
119 jpeg_dma_rx_id = 0;
120 }
121
jpeg_init_common(const jpeg_config_t * config)122 static void jpeg_init_common(const jpeg_config_t *config)
123 {
124 #if (CONFIG_SYSTEM_CTRL)
125 jpeg_power_config_set(config);
126 sys_drv_int_enable(JPEGENC_INTERRUPT_CTRL_BIT);
127 #else
128 power_jpeg_pwr_up();
129 icu_enable_jpeg_interrupt();
130 #endif
131
132 jpeg_init_gpio();
133 }
134
jpeg_deinit_common(void)135 static void jpeg_deinit_common(void)
136 {
137 jpeg_hal_stop_common(&s_jpeg.hal, JPEG_ENC_MODE);
138 jpeg_hal_reset_config_to_default(&s_jpeg.hal);
139 #if (CONFIG_SYSTEM_CTRL)
140 bk_pm_clock_ctrl(PM_CLK_ID_JPEG, CLK_PWR_CTRL_PWR_DOWN);
141 sys_hal_set_jpeg_disckg(0);
142 sys_drv_int_disable(JPEGENC_INTERRUPT_CTRL_BIT);
143 #else
144 icu_disable_jpeg_interrupt();
145 power_jpeg_pwr_down();
146 #endif
147
148 jpeg_dma_rx_deinit();
149 jpeg_deinit_gpio();
150 }
151
bk_jpeg_enc_driver_init(void)152 bk_err_t bk_jpeg_enc_driver_init(void)
153 {
154 if (s_jpeg_driver_is_init) {
155 return BK_OK;
156 }
157 #if CONFIG_SYSTEM_CTRL
158 //power on
159 bk_pm_module_vote_power_ctrl(PM_POWER_SUB_MODULE_NAME_VIDP_JPEG_EN, PM_POWER_MODULE_STATE_ON);
160 #endif
161
162 os_memset(&s_jpeg, 0, sizeof(s_jpeg));
163 jpeg_hal_init(&s_jpeg.hal);
164 bk_int_isr_register(INT_SRC_JPEG, jpeg_isr, NULL);
165 s_jpeg_driver_is_init = true;
166
167 return BK_OK;
168 }
169
bk_jpeg_enc_driver_deinit(void)170 bk_err_t bk_jpeg_enc_driver_deinit(void)
171 {
172 if (!s_jpeg_driver_is_init) {
173 return BK_OK;
174 }
175 bk_int_isr_unregister(INT_SRC_JPEG);
176 #if CONFIG_SYSTEM_CTRL
177 // power off
178 bk_pm_module_vote_power_ctrl(PM_POWER_SUB_MODULE_NAME_VIDP_JPEG_EN, PM_POWER_MODULE_STATE_OFF);
179 #endif
180
181 s_jpeg_driver_is_init = false;
182
183 return BK_OK;
184 }
185
bk_jpeg_enc_init(const jpeg_config_t * config)186 bk_err_t bk_jpeg_enc_init(const jpeg_config_t *config)
187 {
188 BK_RETURN_ON_NULL(config);
189 JPEG_RETURN_ON_NOT_INIT();
190
191 jpeg_init_common(config);
192
193 if (config->yuv_mode) {
194 jpeg_hal_set_yuv_config(&s_jpeg.hal, config);
195 } else {
196 jpeg_hal_set_encode_config(&s_jpeg.hal, config);
197 }
198
199 jpeg_dma_rx_init(config);
200
201 return BK_OK;
202 }
203
bk_jpeg_enc_deinit(void)204 bk_err_t bk_jpeg_enc_deinit(void)
205 {
206 jpeg_deinit_common();
207
208 return BK_OK;
209 }
210
bk_jpeg_enc_partial_display_init(const jpeg_partial_offset_config_t * offset_config)211 bk_err_t bk_jpeg_enc_partial_display_init(const jpeg_partial_offset_config_t *offset_config)
212 {
213 JPEG_RETURN_ON_NOT_INIT();
214 jpeg_hal_partial_display_offset_config(&s_jpeg.hal, offset_config);
215 jpeg_hal_enable_partial_display(&s_jpeg.hal, 1);
216
217 return BK_OK;
218 }
219
bk_jpeg_enc_partial_display_deinit(const jpeg_partial_offset_config_t * offset_config)220 bk_err_t bk_jpeg_enc_partial_display_deinit(const jpeg_partial_offset_config_t *offset_config)
221 {
222 jpeg_hal_enable_partial_display(&s_jpeg.hal, 0);;
223 os_memset((void *)offset_config, 0, sizeof(jpeg_partial_offset_config_t));
224 jpeg_hal_partial_display_offset_config(&s_jpeg.hal, offset_config);
225
226 return BK_OK;
227 }
228
bk_jpeg_enc_dvp_init(const jpeg_config_t * config)229 bk_err_t bk_jpeg_enc_dvp_init(const jpeg_config_t *config)
230 {
231 BK_RETURN_ON_NULL(config);
232 JPEG_RETURN_ON_NOT_INIT();
233
234 jpeg_init_common(config);
235
236 if (config->yuv_mode) {
237 jpeg_hal_set_yuv_config(&s_jpeg.hal, config);
238 } else {
239 jpeg_hal_set_encode_config(&s_jpeg.hal, config);
240 }
241
242 return BK_OK;
243 }
244
bk_jpeg_enc_dvp_deinit(void)245 bk_err_t bk_jpeg_enc_dvp_deinit(void)
246 {
247 jpeg_hal_stop_common(&s_jpeg.hal, JPEG_ENC_MODE);
248 jpeg_hal_stop_common(&s_jpeg.hal, JPEG_YUV_MODE);
249 jpeg_hal_reset_config_to_default(&s_jpeg.hal);
250
251 bk_pm_clock_ctrl(PM_CLK_ID_JPEG, CLK_PWR_CTRL_PWR_DOWN);
252 sys_hal_set_jpeg_disckg(0);
253 #if (CONFIG_SYSTEM_CTRL)
254 sys_drv_int_disable(JPEGENC_INTERRUPT_CTRL_BIT);
255 #endif
256 jpeg_deinit_gpio();
257
258
259 return BK_OK;
260 }
261
bk_jpeg_enc_set_enable(uint8_t enable,uint8_t mode)262 bk_err_t bk_jpeg_enc_set_enable(uint8_t enable, uint8_t mode)
263 {
264 JPEG_RETURN_ON_NOT_INIT();
265
266 if (enable) {
267 jpeg_hal_start_common(&s_jpeg.hal, mode);
268 } else {
269 jpeg_hal_stop_common(&s_jpeg.hal, mode);
270 }
271
272 return BK_OK;
273 }
274
bk_jpeg_set_em_base_addr(uint8_t * address)275 bk_err_t bk_jpeg_set_em_base_addr(uint8_t *address)
276 {
277 JPEG_RETURN_ON_NOT_INIT();
278 jpeg_hal_set_em_base_addr(&s_jpeg.hal, address);
279 return BK_OK;
280 }
281
bk_jpeg_enc_yuv_fmt_sel(uint32_t value)282 bk_err_t bk_jpeg_enc_yuv_fmt_sel(uint32_t value)
283 {
284 JPEG_RETURN_ON_NOT_INIT();
285
286 jpeg_hal_yuv_fmt_sel(&s_jpeg.hal, value);
287
288 return BK_OK;
289 }
290
bk_jpeg_enc_get_frame_size(void)291 uint32_t bk_jpeg_enc_get_frame_size(void)
292 {
293 JPEG_RETURN_ON_NOT_INIT();
294
295 return jpeg_hal_get_frame_byte_number(&s_jpeg.hal);
296 }
297
bk_jpeg_enc_register_isr(jpeg_isr_type_t type_id,jpeg_isr_t isr,void * param)298 bk_err_t bk_jpeg_enc_register_isr(jpeg_isr_type_t type_id, jpeg_isr_t isr, void *param)
299 {
300 uint32_t int_level = rtos_disable_int();
301 s_jpeg.jpeg_isr_handler[type_id].isr_handler = isr;
302 s_jpeg.jpeg_isr_handler[type_id].param = param;
303
304 rtos_enable_int(int_level);
305 return BK_OK;
306 }
307
bk_jpeg_enc_dvp_gpio_enable(void)308 bk_err_t bk_jpeg_enc_dvp_gpio_enable(void)
309 {
310 jpeg_gpio_map_t jpeg_gpio_map_table[] = JPEG_GPIO_MAP;
311 for (uint32_t i = 2; i < JPEG_GPIO_PIN_NUMBER; i++) {
312 gpio_dev_unmap(jpeg_gpio_map_table[i].gpio_id);
313 gpio_dev_map(jpeg_gpio_map_table[i].gpio_id, jpeg_gpio_map_table[i].dev);
314 }
315
316 return BK_OK;
317 }
318
bk_jpeg_enc_get_fifo_addr(uint32_t * fifo_addr)319 bk_err_t bk_jpeg_enc_get_fifo_addr(uint32_t *fifo_addr)
320 {
321 JPEG_RETURN_ON_NOT_INIT();
322 *fifo_addr = JPEG_R_RX_FIFO;
323 return BK_OK;
324 }
325
bk_jpeg_enc_enable_int(uint32_t type)326 bk_err_t bk_jpeg_enc_enable_int(uint32_t type)
327 {
328 JPEG_RETURN_ON_NOT_INIT();
329 if (type & JPEG_END_YUV_INT) {
330 jpeg_hal_enable_end_yuv_int(&s_jpeg.hal);
331 }
332
333 if (type & JPEG_HEAD_OUTPUT_INT) {
334 jpeg_hal_enable_head_output_int(&s_jpeg.hal);
335 }
336
337 if (type & JPEG_START_FRAME_INT) {
338 jpeg_hal_enable_start_frame_int(&s_jpeg.hal);
339 }
340
341 if (type & JPEG_END_FRAME_INT) {
342 jpeg_hal_enable_end_frame_int(&s_jpeg.hal);
343 }
344
345 if (type & JPEG_VSYNC_NEGEDGE_INT) {
346 jpeg_hal_enable_vsync_negedge_int(&s_jpeg.hal);
347 }
348
349 return BK_OK;
350 }
351
bk_jpeg_enc_disable_int(uint32_t type)352 bk_err_t bk_jpeg_enc_disable_int(uint32_t type)
353 {
354 JPEG_RETURN_ON_NOT_INIT();
355 if (type & JPEG_END_YUV_INT) {
356 jpeg_hal_disable_end_yuv_int(&s_jpeg.hal);
357 }
358
359 if (type & JPEG_HEAD_OUTPUT_INT) {
360 jpeg_hal_disable_head_output_int(&s_jpeg.hal);
361 }
362
363 if (type & JPEG_START_FRAME_INT) {
364 jpeg_hal_disable_start_frame_int(&s_jpeg.hal);
365 }
366
367 if (type & JPEG_END_FRAME_INT) {
368 jpeg_hal_disable_end_frame_int(&s_jpeg.hal);
369 }
370
371 if (type & JPEG_VSYNC_NEGEDGE_INT) {
372 jpeg_hal_disable_vsync_negedge_int(&s_jpeg.hal);
373 }
374
375 return BK_OK;
376 }
377
bk_jpeg_enc_set_auxs(uint32_t cksel,uint32_t ckdiv)378 bk_err_t bk_jpeg_enc_set_auxs(uint32_t cksel, uint32_t ckdiv)
379 {
380 #if CONFIG_SYSTEM_CTRL
381 gpio_dev_unmap(JPEG_GPIO_AUXS);
382 gpio_dev_map(JPEG_GPIO_AUXS, GPIO_DEV_CLK_AUXS);
383 sys_hal_set_auxs_clk_sel(cksel);
384 sys_hal_set_auxs_clk_div(ckdiv);
385 return BK_OK;
386 #else
387 return BK_FAIL;
388 #endif
389 }
390
bk_jpeg_enc_mclk_enable(void)391 bk_err_t bk_jpeg_enc_mclk_enable(void)
392 {
393 JPEG_RETURN_ON_NOT_INIT();
394
395 sys_drv_set_jpeg_clk_sel(1);
396 sys_drv_set_clk_div_mode1_clkdiv_jpeg(4);
397 sys_drv_set_jpeg_disckg(1);
398
399 jpeg_hal_enable_clk(&s_jpeg.hal, 0);
400 bk_pm_clock_ctrl(PM_CLK_ID_JPEG, CLK_PWR_CTRL_PWR_UP);
401
402 return BK_OK;
403 }
404
bk_jpeg_enc_enable_encode_auto_ctrl(uint8_t enable)405 bk_err_t bk_jpeg_enc_enable_encode_auto_ctrl(uint8_t enable)
406 {
407 JPEG_RETURN_ON_NOT_INIT();
408
409 jpeg_hal_enable_bitrate_ctrl(&s_jpeg.hal, enable);
410
411 return BK_OK;
412 }
413
bk_jpeg_enc_set_target_size(uint32_t up_size,uint32_t low_size)414 bk_err_t bk_jpeg_enc_set_target_size(uint32_t up_size, uint32_t low_size)
415 {
416 JPEG_RETURN_ON_NOT_INIT();
417
418 jpeg_hal_set_target_size(&s_jpeg.hal, up_size, low_size);
419
420 return BK_OK;
421 }
422
jpeg_isr(void)423 static void jpeg_isr(void)
424 {
425 jpeg_hal_t *hal = &s_jpeg.hal;
426 uint32_t int_status = jpeg_hal_get_interrupt_status(hal);
427 jpeg_hal_clear_interrupt_status(hal, int_status);
428
429 if (jpeg_hal_is_frame_start_int_triggered(hal, int_status)) {
430 if (s_jpeg.jpeg_isr_handler[START_OF_FRAME].isr_handler) {
431 s_jpeg.jpeg_isr_handler[START_OF_FRAME].isr_handler(0, s_jpeg.jpeg_isr_handler[START_OF_FRAME].param);
432 }
433 }
434
435 if (jpeg_hal_is_frame_end_int_triggered(hal, int_status)) {
436 if (s_jpeg.jpeg_isr_handler[END_OF_FRAME].isr_handler) {
437 s_jpeg.jpeg_isr_handler[END_OF_FRAME].isr_handler(0, s_jpeg.jpeg_isr_handler[END_OF_FRAME].param);
438 }
439 }
440
441 if (jpeg_hal_is_yuv_end_int_triggered(hal, int_status)) {
442 if (s_jpeg.jpeg_isr_handler[END_OF_YUV].isr_handler) {
443 s_jpeg.jpeg_isr_handler[END_OF_YUV].isr_handler(0, s_jpeg.jpeg_isr_handler[END_OF_YUV].param);
444 }
445 }
446
447 if (jpeg_hal_is_head_output_int_triggered(hal, int_status)) {
448 if (s_jpeg.jpeg_isr_handler[HEAD_OUTPUT].isr_handler) {
449 s_jpeg.jpeg_isr_handler[HEAD_OUTPUT].isr_handler(0, s_jpeg.jpeg_isr_handler[HEAD_OUTPUT].param);
450 }
451 }
452
453 if (jpeg_hal_is_sync_negedge_int_triggered(hal, int_status)) {
454 if (s_jpeg.jpeg_isr_handler[VSYNC_NEGEDGE].isr_handler) {
455 s_jpeg.jpeg_isr_handler[VSYNC_NEGEDGE].isr_handler(0, s_jpeg.jpeg_isr_handler[VSYNC_NEGEDGE].param);
456 }
457 }
458 }
459
460