1 // Copyright (C) 2022 Beken Corporation
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #include <driver/int.h>
16 #include <os/mem.h>
17 #include "clock_driver.h"
18 #include "sys_driver.h"
19 #include "psram_hal.h"
20 #include "aon_pmu_hal.h"
21 #include "driver/psram_types.h"
22
23 extern int delay(INT32 num);
24 #define addSYSTEM_Reg0xe *((volatile unsigned long *) (0x44010000+0xe*4))
25
26 #define addFLASH_Reg0x7 *((volatile unsigned long *) (0x44030000+0x7*4))
27 #define set_FLASH_Reg0x7_mode_sel(val) addFLASH_Reg0x7 = ((addFLASH_Reg0x7 & (~0x1F0)) | ((val) << 4))
28 #define get_FLASH_Reg0x7_mode_sel ((addFLASH_Reg0x7 & 0x1F0) >> 4)
29
30 #define BK_ERR_PSRAM_DRIVER_NOT_INIT (BK_ERR_PSRAM_BASE - 1) /**< psram driver not init */
31 #define BK_ERR_PSRAM_SERVER_NOT_INIT (BK_ERR_PSRAM_BASE - 2) /**< psram server not init */
32
33
34 static bool s_psram_driver_is_init = false;
35 static bool s_psram_server_is_init = false;
36
37 #define PSRAM_RETURN_ON_DRIVER_NOT_INIT() do {\
38 if (!s_psram_driver_is_init) {\
39 return BK_ERR_PSRAM_DRIVER_NOT_INIT;\
40 }\
41 } while(0)
42
43 #define PSRAM_RETURN_ON_SERVER_NOT_INIT() do {\
44 if (!s_psram_server_is_init) {\
45 return BK_ERR_PSRAM_SERVER_NOT_INIT;\
46 }\
47 } while(0)
48
psram_init_common(void)49 static void psram_init_common(void)
50 {
51 addSYSTEM_Reg0xe |= (0x1 << 25); // not set
52
53 //setf_SYSTEM_Reg0x9_cksel_psram;//480M
54 sys_drv_psram_clk_sel(0x0);// 0/1:160M/240M
55
56 //set_SYSTEM_Reg0x9_ckdiv_psram(1);//120M
57 sys_drv_psram_set_clkdiv(0x0);//0/1:div
58
59 // when use psram 120M, need open this code
60 //aon_pmu_hal_psram_iodrv_set(0x2);
61
62 //setf_SYSTEM_Reg0xc_psram_cken;
63 sys_drv_dev_clk_pwr_up(CLK_PWR_ID_PSRAM, CLK_PWR_CTRL_PWR_UP);//psram_clk_enable bit19=1
64 }
65
bk_psram_driver_init(void)66 bk_err_t bk_psram_driver_init(void)
67 {
68 if (s_psram_driver_is_init)
69 return BK_OK;
70
71 sys_drv_psram_power_enable();
72
73 //sys_drv_psram_psldo_vsel(1);
74
75 s_psram_driver_is_init = true;
76
77 return BK_OK;
78 }
79
bk_psram_driver_deinit(void)80 bk_err_t bk_psram_driver_deinit(void)
81 {
82 if (!s_psram_driver_is_init) {
83 return BK_OK;
84 }
85
86 sys_drv_psram_ldo_enable(0); // 断电
87
88 s_psram_driver_is_init = false;
89 s_psram_server_is_init = false;
90
91 return BK_OK;
92 }
93
94
bk_psram_set_clk(psram_clk_t clk)95 bk_err_t bk_psram_set_clk(psram_clk_t clk)
96 {
97 bk_err_t ret = BK_OK;
98
99 switch (clk)
100 {
101 case PSRAM_240M:
102 sys_hal_psram_clk_sel(1); // clk sel: 0-320 1-480
103 sys_hal_psram_set_clkdiv(0); //frq: F/(2 + (1+div))
104 break;
105 case PSRAM_160M:
106 sys_hal_psram_clk_sel(0); // clk sel: 0-320 1-480
107 sys_hal_psram_set_clkdiv(0); //frq: F/(2 + (1+div))
108 break;
109 case PSRAM_120M:
110 sys_hal_psram_clk_sel(1); // clk sel: 0-320 1-480
111 sys_hal_psram_set_clkdiv(1); //frq: F/(2 + (1+div))
112 break;
113 case PSRAM_60M:
114 sys_hal_psram_clk_sel(0); // clk sel: 0-320 1-480
115 sys_hal_psram_set_clkdiv(1); //frq: F/(2 + (1+div))
116 break;
117 default:
118 break;
119 }
120
121 return ret;
122 }
123
bk_psram_set_voltage(psram_voltage_t voltage)124 bk_err_t bk_psram_set_voltage(psram_voltage_t voltage)
125 {
126 bk_err_t ret = BK_OK;
127
128 switch (voltage)
129 {
130 case PSRAM_OUT_3_2V:
131 sys_hal_psram_psldo_vset(0, 1);
132 break;
133 case PSRAM_OUT_3V:
134 sys_hal_psram_psldo_vset(0, 0);
135 break;
136 case PSRAM_OUT_2V:
137 sys_hal_psram_psldo_vset(1, 1);
138 break;
139 case PSRAM_OUT_1_3V:
140 sys_hal_psram_psldo_vset(1, 0);
141 break;
142 default:
143 break;
144 }
145
146 return ret;
147 }
148
bk_psram_set_transfer_mode(psram_tansfer_mode_t transfer_mode)149 bk_err_t bk_psram_set_transfer_mode(psram_tansfer_mode_t transfer_mode)
150 {
151 bk_err_t ret = BK_OK;
152
153 psram_hal_set_transfer_mode(transfer_mode);
154
155 return ret;
156 }
157
158
bk_psram_init(void)159 bk_err_t bk_psram_init(void)
160 {
161 PSRAM_RETURN_ON_DRIVER_NOT_INIT();
162
163 if (s_psram_server_is_init) {
164 return BK_OK;
165 }
166
167 uint32_t mode = 0xa8054043;
168 uint32_t val = 0;
169
170 psram_init_common();
171 delay(1000);
172
173 psram_hal_set_sf_reset(1);
174
175 psram_hal_set_mode_value(mode);
176 delay(1500);
177
178 psram_hal_set_cmd_reset();
179 delay(1500);
180
181 psram_hal_cmd_read(0x00000000);//1 0001 10001101
182 delay(100);
183
184 val = psram_hal_get_regb_value();
185 //val = (val & ~(0x7 << 10)) | (0x4 << 10) | (0x3 << 8);//read latency 100 166Mhz
186 val = (val & ~(0x1F << 8)) | (0x4 << 10) | (0x3 << 8);
187 // val = (val & ~(0x1f << 8)) | (0x10 << 8);//read latency 100 166Mhz dstr set 00
188 psram_hal_cmd_write(0x00000000, val);
189 delay(100);
190
191 psram_hal_cmd_read(0x00000000);//1 0001 10001101
192
193 psram_hal_cmd_read(0x00000004);
194
195 val = psram_hal_get_regb_value();
196 val = (val & ~(0x7 << 13)) | (0x6 << 13);//write latency 110 166Mhz
197
198 psram_hal_cmd_write(0x00000004, val);
199 s_psram_server_is_init = true;
200 delay(1000);
201 return BK_OK;
202 }
203
bk_psram_deinit(void)204 bk_err_t bk_psram_deinit(void)
205 {
206 PSRAM_RETURN_ON_DRIVER_NOT_INIT();
207
208 if (!s_psram_server_is_init) {
209 return BK_OK;
210 }
211
212 sys_drv_dev_clk_pwr_up(CLK_PWR_ID_PSRAM, CLK_PWR_CTRL_PWR_DOWN);//psram_clk_disable
213 delay(1000);
214 s_psram_server_is_init = false;
215 return BK_OK;
216 }
217
218