1
2 /*
3 * isp521_reg_cfg.c
4 *
5 * Copyright (c) 2007-2017 Allwinnertech Co., Ltd.
6 *
7 * Authors: Zhao Wei <zhaowei@allwinnertech.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19 #include <linux/io.h>
20 #include <linux/string.h>
21 #include "isp521_reg.h"
22 #include "isp521_reg_cfg.h"
23
24 #define ISP521_MAX_NUM 1
25 /* #define USE_DEF_PARA */
26
27 /*
28 * Load ISP register variables
29 */
30
31 struct isp521_reg {
32 ISP_GLOBAL_CFG0_REG_t *isp_global_cfg0;
33 ISP_GLOBAL_CFG1_REG_t *isp_global_cfg1;
34 ISP_GLOBAL_CFG2_REG_t *isp_global_cfg2;
35 ISP_GLOBAL_CFG3_REG_t *isp_global_cfg3;
36
37 ISP_UPDATE_CTRL0_REG_t *isp_update_ctrl0;
38 unsigned int *isp_load_addr0;
39 unsigned int *isp_load_addr1;
40 unsigned int *isp_save_addr;
41 ISP_INT_BYPASS0_REG_t *isp_int_bypass0;
42 ISP_INT_STATUS0_REG_t *isp_int_status0;
43 ISP_INTER_STATUS0_REG_t *isp_inter_status0;
44 ISP_INTER_STATUS1_REG_t *isp_inter_status1;
45 ISP_LBC_INTER_STATUS_REG_t *isp_lbc_inter_status;
46 ISP_VER_CFG_REG_t *isp_ver_cfg;
47 ISP_MAX_SIZE_REG_t *isp_max_width;
48
49 ISP_WDR_CMP_BANDWIDTH_REG_t *isp_wdr_cmp_bandwidth;
50 ISP_WDR_DECMP_BANDWIDTH_REG_t *isp_wdr_decmp_bandwidth;
51 ISP_D3D_CMP_BANDWIDTH_REG_t *isp_d3d_cmp_bandwidth;
52 ISP_D3D_DECMP_BANDWIDTH_REG_t *isp_d3d_decmp_bandwidth;
53
54 ISP_S0_FMERR_CNT_REG_t *isp_s0_fmerr_cnt;
55 ISP_S1_FMERR_CNT_REG_t *isp_s1_fmerr_cnt;
56 ISP_S0_HB_CNT_REG_t *isp_s0_hb_cnt;
57 ISP_S1_HB_CNT_REG_t *isp_s1_hb_cnt;
58 ISP_WDR_FIFO_OVERFLOW_LINE_REG_t *isp_wdr_fifo_overflow_line;
59 ISP_D3D_FIFO_OVERFLOW_LINE_REG_t *isp_d3d_fifo_overflow_line;
60 ISP_WDR_DMA_STRIDE_LEN_REG_t *isp_wdr_dma_stride;
61 ISP_D3D_DMA_STRIDE_LEN_REG_t *isp_d3d_dma_stride;
62 unsigned int *isp_wdr_exp_addr0;
63 ISP_SIM_CTRL_REG_t *isp_sim_ctrl;
64 unsigned int *isp_d3d_ref_k_addr;
65 unsigned int *isp_d3d_ref_raw_addr;
66 unsigned int *isp_d3d_ltf_raw_addr;
67 ISP_TOP_CTRL_REG_t *isp_top_ctrl;
68
69 ISP_UPDATE_CTRL0_REG_t *isp_update_flag;
70 ISP_S1_CFG_REG_t *isp_s1_cfg;
71 ISP_MODULE_BYPASS0_REG_t *isp_module_bypass0;
72 ISP_INPUT_SIZE_REG_t *isp_input_size;
73 ISP_VALID_SIZE_REG_t *isp_valid_size;
74 ISP_VALID_START_REG_t *isp_valid_start;
75
76 ISP_WDR_RAW_LBC_CTRL_REG_t *isp_wdr_raw_lbc_ctrl;
77 ISP_D3D_RAW_LBC_CTRL_REG_t *isp_d3d_raw_lbc_ctrl;
78 ISP_D3D_K_LBC_CTRL_REG_t *isp_d3d_k_lbc_ctrl;
79 };
80
81 struct isp521_reg isp_regs[ISP521_MAX_NUM];
82
bsp_isp_map_reg_addr(unsigned long id,unsigned long base)83 void bsp_isp_map_reg_addr(unsigned long id, unsigned long base)
84 {
85 isp_regs[id].isp_global_cfg0 = (ISP_GLOBAL_CFG0_REG_t *) (base + ISP_GLOBAL_CFG0_REG);
86 isp_regs[id].isp_global_cfg1 = (ISP_GLOBAL_CFG1_REG_t *) (base + ISP_GLOBAL_CFG1_REG);
87 isp_regs[id].isp_global_cfg2 = (ISP_GLOBAL_CFG2_REG_t *) (base + ISP_GLOBAL_CFG2_REG);
88 isp_regs[id].isp_global_cfg3 = (ISP_GLOBAL_CFG3_REG_t *) (base + ISP_GLOBAL_CFG3_REG);
89
90 isp_regs[id].isp_update_ctrl0 = (ISP_UPDATE_CTRL0_REG_t *) (base + ISP_UPDATE_CTRL0_REG);
91 isp_regs[id].isp_load_addr0 = (unsigned int *) (base + ISP_LOAD_ADDR0_REG);
92 isp_regs[id].isp_load_addr1 = (unsigned int *) (base + ISP_LOAD_ADDR1_REG);
93 isp_regs[id].isp_save_addr = (unsigned int *) (base + ISP_SAVE_ADDR_REG);
94 isp_regs[id].isp_int_bypass0 = (ISP_INT_BYPASS0_REG_t *) (base + ISP_INT_BYPASS0_REG);
95 isp_regs[id].isp_int_status0 = (ISP_INT_STATUS0_REG_t *) (base + ISP_INT_STATUS0_REG);
96 isp_regs[id].isp_inter_status0 = (ISP_INTER_STATUS0_REG_t *) (base + ISP_INTER_STATUS0_REG);
97 isp_regs[id].isp_inter_status1 = (ISP_INTER_STATUS1_REG_t *) (base + ISP_INTER_STATUS1_REG);
98 isp_regs[id].isp_lbc_inter_status = (ISP_LBC_INTER_STATUS_REG_t *) (base + ISP_LBC_INTER_STATUS_REG);
99 isp_regs[id].isp_ver_cfg = (ISP_VER_CFG_REG_t *) (base + ISP_VER_CFG_REG);
100 isp_regs[id].isp_max_width = (ISP_MAX_SIZE_REG_t *) (base + ISP_MAX_WIDTH_REG);
101
102 isp_regs[id].isp_wdr_cmp_bandwidth = (ISP_WDR_CMP_BANDWIDTH_REG_t *) (base + ISP_WDR_CMP_BANDWIDTH_REG);
103 isp_regs[id].isp_wdr_decmp_bandwidth = (ISP_WDR_DECMP_BANDWIDTH_REG_t *) (base + ISP_WDR_DECMP_BANDWIDTH_REG);
104 isp_regs[id].isp_d3d_cmp_bandwidth = (ISP_D3D_CMP_BANDWIDTH_REG_t *) (base + ISP_D3D_CMP_BANDWIDTH_REG);
105 isp_regs[id].isp_d3d_decmp_bandwidth = (ISP_D3D_DECMP_BANDWIDTH_REG_t *) (base + ISP_D3D_DECMP_BANDWIDTH_REG);
106
107 isp_regs[id].isp_s0_fmerr_cnt = (ISP_S0_FMERR_CNT_REG_t *) (base + ISP_S0_FMERR_CNT_REG);
108 isp_regs[id].isp_s1_fmerr_cnt = (ISP_S1_FMERR_CNT_REG_t *) (base + ISP_S1_FMERR_CNT_REG);
109 isp_regs[id].isp_s0_hb_cnt = (ISP_S0_HB_CNT_REG_t *) (base + ISP_S0_HB_CNT_REG);
110 isp_regs[id].isp_s1_hb_cnt = (ISP_S1_HB_CNT_REG_t *) (base + ISP_S1_HB_CNT_REG);
111 isp_regs[id].isp_wdr_fifo_overflow_line = (ISP_WDR_FIFO_OVERFLOW_LINE_REG_t *) (base + ISP_WDR_FIFO_OVERFLOW_LINE_REG);
112 isp_regs[id].isp_d3d_fifo_overflow_line = (ISP_D3D_FIFO_OVERFLOW_LINE_REG_t *) (base + ISP_D3D_FIFO_OVERFLOW_LINE_REG);
113 isp_regs[id].isp_wdr_dma_stride = (ISP_WDR_DMA_STRIDE_LEN_REG_t *)(base + ISP_WDR_DMA_STRIDE_LEN_REG);
114 isp_regs[id].isp_d3d_dma_stride = (ISP_D3D_DMA_STRIDE_LEN_REG_t *)(base + ISP_D3D_DMA_STRIDE_LEN_REG);
115 isp_regs[id].isp_wdr_exp_addr0 = (unsigned int *) (base + ISP_WDR_EXP_ADDR0_REG);
116 isp_regs[id].isp_sim_ctrl = (ISP_SIM_CTRL_REG_t *) (base + ISP_SIM_CTRL_REG);
117
118 isp_regs[id].isp_input_size = (ISP_INPUT_SIZE_REG_t *) (base + ISP_INPUT_SIZE_REG);
119 isp_regs[id].isp_valid_size = (ISP_VALID_SIZE_REG_t *) (base + ISP_VALID_SIZE_REG);
120 isp_regs[id].isp_valid_start = (ISP_VALID_START_REG_t *) (base + ISP_VALID_START_REG);
121
122 isp_regs[id].isp_d3d_ref_k_addr = (unsigned int *) (base + ISP_D3D_REF_K_ADDR_REG);
123 isp_regs[id].isp_d3d_ref_raw_addr = (unsigned int *) (base + ISP_D3D_REF_RAW_ADDR_REG);
124 isp_regs[id].isp_d3d_ltf_raw_addr = (unsigned int *) (base + ISP_D3D_LTF_RAW_ADDR_REG);
125
126 isp_regs[id].isp_top_ctrl = (ISP_TOP_CTRL_REG_t *) (base + ISP_TOP_CTRL_REG);
127
128 #ifdef USE_DEF_PARA
129 isp_regs[id].isp_s1_cfg = (ISP_S1_CFG_REG_t *) (base + ISP_S1_CFG_REG);
130 isp_regs[id].isp_module_bypass0 = (ISP_MODULE_BYPASS0_REG_t *) (base + ISP_MODULE_BYPASS0_REG);
131 isp_regs[id].isp_wdr_raw_lbc_ctrl = (ISP_WDR_RAW_LBC_CTRL_REG_t *) (base + ISP_WDR_RAW_LBC_CTRL_REG);
132 isp_regs[id].isp_d3d_raw_lbc_ctrl = (ISP_D3D_RAW_LBC_CTRL_REG_t *) (base + ISP_D3D_RAW_LBC_CTRL_REG);
133 isp_regs[id].isp_d3d_k_lbc_ctrl = (ISP_D3D_K_LBC_CTRL_REG_t *) (base + ISP_D3D_K_LBC_CTRL_REG);
134
135 #endif
136 }
137
138 /*
139 * Load DRAM Register Address
140 */
141
bsp_isp_map_load_dram_addr(unsigned long id,unsigned long base)142 void bsp_isp_map_load_dram_addr(unsigned long id, unsigned long base)
143 {
144 #ifndef USE_DEF_PARA
145 isp_regs[id].isp_update_flag = (ISP_UPDATE_CTRL0_REG_t *) (base + ISP_UPDATE_CTRL0_REG);
146 isp_regs[id].isp_s1_cfg = (ISP_S1_CFG_REG_t *) (base + ISP_S1_CFG_REG);
147 isp_regs[id].isp_module_bypass0 = (ISP_MODULE_BYPASS0_REG_t *) (base + ISP_MODULE_BYPASS0_REG);
148 isp_regs[id].isp_wdr_raw_lbc_ctrl = (ISP_WDR_RAW_LBC_CTRL_REG_t *) (base + ISP_WDR_RAW_LBC_CTRL_REG);
149 isp_regs[id].isp_d3d_raw_lbc_ctrl = (ISP_D3D_RAW_LBC_CTRL_REG_t *) (base + ISP_D3D_RAW_LBC_CTRL_REG);
150 isp_regs[id].isp_d3d_k_lbc_ctrl = (ISP_D3D_K_LBC_CTRL_REG_t *) (base + ISP_D3D_K_LBC_CTRL_REG);
151 #endif
152 }
153
154 /*******isp control register which we can write directly to register*********/
155
bsp_isp_enable(unsigned long id,unsigned int en)156 void bsp_isp_enable(unsigned long id, unsigned int en)
157 {
158 isp_regs[id].isp_global_cfg0->bits.isp_enable = en;
159 }
160
bsp_isp_capture_start(unsigned long id)161 void bsp_isp_capture_start(unsigned long id)
162 {
163 isp_regs[id].isp_global_cfg0->bits.cap_en = 1;
164 }
165
bsp_isp_capture_stop(unsigned long id)166 void bsp_isp_capture_stop(unsigned long id)
167 {
168 isp_regs[id].isp_global_cfg0->bits.cap_en = 0;
169 }
170
bsp_isp_ver_read_en(unsigned long id,unsigned int en)171 void bsp_isp_ver_read_en(unsigned long id, unsigned int en)
172 {
173 isp_regs[id].isp_global_cfg0->bits.isp_ver_rd_en = en;
174 }
175
bsp_isp_set_input_fmt(unsigned long id,unsigned int fmt)176 void bsp_isp_set_input_fmt(unsigned long id, unsigned int fmt)
177 {
178 isp_regs[id].isp_global_cfg0->bits.input_fmt = fmt;
179 }
180
bsp_isp_ch_enable(unsigned long id,int ch,int enable)181 void bsp_isp_ch_enable(unsigned long id, int ch, int enable)
182 {
183 switch (ch) {
184 case 0:
185 isp_regs[id].isp_global_cfg0->bits.isp_ch0_en = enable;
186 break;
187 case 1:
188 isp_regs[id].isp_global_cfg0->bits.isp_ch1_en = enable;
189 break;
190 case 2:
191 isp_regs[id].isp_global_cfg0->bits.isp_ch2_en = enable;
192 break;
193 case 3:
194 isp_regs[id].isp_global_cfg0->bits.isp_ch3_en = enable;
195 break;
196 default:
197 isp_regs[id].isp_global_cfg0->bits.isp_ch0_en = enable;
198 break;
199 }
200 }
201
bsp_isp_wdr_mode_cfg(unsigned long id,struct isp_wdr_mode_cfg * cfg)202 void bsp_isp_wdr_mode_cfg(unsigned long id, struct isp_wdr_mode_cfg *cfg)
203 {
204 isp_regs[id].isp_global_cfg0->bits.wdr_ch_seq = cfg->wdr_ch_seq;
205 isp_regs[id].isp_global_cfg0->bits.wdr_exp_seq = cfg->wdr_exp_seq;
206 isp_regs[id].isp_global_cfg0->bits.wdr_mode = cfg->wdr_mode;
207 isp_regs[id].isp_global_cfg0->bits.wdr_cmp_mode = 1;
208 }
209
bsp_isp_set_line_int_num(unsigned long id,unsigned int line_num)210 void bsp_isp_set_line_int_num(unsigned long id, unsigned int line_num)
211 {
212 isp_regs[id].isp_global_cfg1->bits.line_int_num = line_num;
213 }
214
bsp_isp_set_speed_mode(unsigned long id,unsigned int speed)215 void bsp_isp_set_speed_mode(unsigned long id, unsigned int speed)
216 {
217 isp_regs[id].isp_global_cfg1->bits.speed_mode = speed;
218 }
219
bsp_isp_set_last_blank_cycle(unsigned long id,unsigned int blank)220 void bsp_isp_set_last_blank_cycle(unsigned long id, unsigned int blank)
221 {
222 isp_regs[id].isp_global_cfg1->bits.last_blank_cycle = blank;
223 }
224
bsp_isp_debug_output_cfg(unsigned long id,int enable,int output_sel)225 void bsp_isp_debug_output_cfg(unsigned long id, int enable, int output_sel)
226 {
227 isp_regs[id].isp_global_cfg2->bits.debug_en = enable;
228 isp_regs[id].isp_global_cfg2->bits.debug_sel = output_sel;
229 }
230
bsp_isp_set_para_ready_mode(unsigned long id,int enable)231 void bsp_isp_set_para_ready_mode(unsigned long id, int enable)
232 {
233 }
234
bsp_isp_set_para_ready(unsigned long id,int ready)235 void bsp_isp_set_para_ready(unsigned long id, int ready)
236 {
237 #ifndef USE_DEF_PARA
238 if (ready)
239 isp_regs[id].isp_update_ctrl0->dwval |= S1_PARA_READY;
240 else
241 isp_regs[id].isp_update_ctrl0->dwval &= ~S1_PARA_READY;
242 isp_regs[id].isp_update_ctrl0->bits.para_ready = ready;
243 #endif
244 }
245
bsp_isp_update_table(unsigned long id,unsigned short table_update)246 void bsp_isp_update_table(unsigned long id, unsigned short table_update)
247 {
248 isp_regs[id].isp_update_ctrl0->bits.linear_update = !!(table_update & LINEAR_UPDATE);
249 isp_regs[id].isp_update_ctrl0->bits.lens_update = !!(table_update & LENS_UPDATE);
250 isp_regs[id].isp_update_ctrl0->bits.gamma_update = !!(table_update & GAMMA_UPDATE);
251 isp_regs[id].isp_update_ctrl0->bits.drc_update = !!(table_update & DRC_UPDATE);
252 isp_regs[id].isp_update_ctrl0->bits.satu_update = !!(table_update & SATU_UPDATE);
253 isp_regs[id].isp_update_ctrl0->bits.wdr_update = !!(table_update & WDR_UPDATE);
254 isp_regs[id].isp_update_ctrl0->bits.d3d_update = !!(table_update & D3D_UPDATE);
255 isp_regs[id].isp_update_ctrl0->bits.pltm_update = !!(table_update & PLTM_UPDATE);
256 isp_regs[id].isp_update_ctrl0->bits.cem_update = !!(table_update & CEM_UPDATE);
257 isp_regs[id].isp_update_ctrl0->bits.msc_update = !!(table_update & MSC_UPDATE);
258 isp_regs[id].isp_update_ctrl0->bits.dehaze_update = !!(table_update & DEHAZE_UPDATE);
259
260 isp_regs[id].isp_update_ctrl0->bits.s1_linear_update = !!(table_update & S1_LINEAR_UPDATE);
261 }
262
bsp_isp_set_load_addr0(unsigned long id,dma_addr_t addr)263 void bsp_isp_set_load_addr0(unsigned long id, dma_addr_t addr)
264 {
265 writel(addr >> ISP_ADDR_BIT_R_SHIFT, isp_regs[id].isp_load_addr0);
266 }
267
bsp_isp_set_load_addr1(unsigned long id,dma_addr_t addr)268 void bsp_isp_set_load_addr1(unsigned long id, dma_addr_t addr)
269 {
270 writel(addr >> ISP_ADDR_BIT_R_SHIFT, isp_regs[id].isp_load_addr1);
271 }
272
bsp_isp_set_saved_addr(unsigned long id,unsigned long addr)273 void bsp_isp_set_saved_addr(unsigned long id, unsigned long addr)
274 {
275 writel(addr >> ISP_ADDR_BIT_R_SHIFT, isp_regs[id].isp_save_addr);
276 }
277
bsp_isp_set_statistics_addr(unsigned long id,dma_addr_t addr)278 void bsp_isp_set_statistics_addr(unsigned long id, dma_addr_t addr)
279 {
280 writel(addr >> ISP_ADDR_BIT_R_SHIFT, isp_regs[id].isp_save_addr);
281 }
282
bsp_isp_irq_enable(unsigned long id,unsigned int irq_flag)283 void bsp_isp_irq_enable(unsigned long id, unsigned int irq_flag)
284 {
285 isp_regs[id].isp_int_bypass0->dwval |= irq_flag;
286 }
287
bsp_isp_irq_disable(unsigned long id,unsigned int irq_flag)288 void bsp_isp_irq_disable(unsigned long id, unsigned int irq_flag)
289 {
290 isp_regs[id].isp_int_bypass0->dwval &= ~irq_flag;
291 }
292
bsp_isp_get_irq_status(unsigned long id,unsigned int flag)293 unsigned int bsp_isp_get_irq_status(unsigned long id, unsigned int flag)
294 {
295 return isp_regs[id].isp_int_status0->dwval & flag;
296 }
297
bsp_isp_clr_irq_status(unsigned long id,unsigned int flag)298 void bsp_isp_clr_irq_status(unsigned long id, unsigned int flag)
299 {
300 isp_regs[id].isp_int_status0->dwval = flag;
301 }
302
bsp_isp_get_internal_status0(unsigned long id,unsigned int flag)303 unsigned int bsp_isp_get_internal_status0(unsigned long id, unsigned int flag)
304 {
305 return isp_regs[id].isp_inter_status0->dwval & flag;
306 }
307
bsp_isp_clr_internal_status0(unsigned long id,unsigned int flag)308 void bsp_isp_clr_internal_status0(unsigned long id, unsigned int flag)
309 {
310 isp_regs[id].isp_inter_status0->dwval = flag;
311 }
312
bsp_isp_get_lbc_internal_status(unsigned long id,unsigned int flag)313 unsigned int bsp_isp_get_lbc_internal_status(unsigned long id, unsigned int flag)
314 {
315 return isp_regs[id].isp_lbc_inter_status->dwval & flag;
316 }
317
bsp_isp_clr_lbc_internal_status(unsigned long id,unsigned int flag)318 void bsp_isp_clr_lbc_internal_status(unsigned long id, unsigned int flag)
319 {
320 isp_regs[id].isp_lbc_inter_status->dwval = flag;
321 }
322
bsp_isp_get_internal_status1(unsigned long id)323 unsigned int bsp_isp_get_internal_status1(unsigned long id)
324 {
325 return isp_regs[id].isp_inter_status1->dwval;
326 }
327
bsp_isp_get_isp_ver(unsigned long id,unsigned int * major,unsigned int * minor)328 unsigned int bsp_isp_get_isp_ver(unsigned long id, unsigned int *major, unsigned int *minor)
329 {
330 *major = isp_regs[id].isp_ver_cfg->bits.big_ver;
331 *minor = isp_regs[id].isp_ver_cfg->bits.small_ver;
332 return isp_regs[id].isp_ver_cfg->dwval;
333 }
334
bsp_isp_get_max_width(unsigned long id)335 unsigned int bsp_isp_get_max_width(unsigned long id)
336 {
337 return isp_regs[id].isp_max_width->bits.max_width;
338 }
339
bsp_isp_get_s0_ch_fmerr_cnt(unsigned long id,struct isp_size * size)340 void bsp_isp_get_s0_ch_fmerr_cnt(unsigned long id, struct isp_size *size)
341 {
342 size->width = isp_regs[id].isp_s0_fmerr_cnt->bits.input_width;
343 size->height = isp_regs[id].isp_s0_fmerr_cnt->bits.input_height;
344 }
345
bsp_isp_get_s1_ch_fmerr_cnt(unsigned long id,struct isp_size * size)346 void bsp_isp_get_s1_ch_fmerr_cnt(unsigned long id, struct isp_size *size)
347 {
348 size->width = isp_regs[id].isp_s1_fmerr_cnt->bits.input_width;
349 size->height = isp_regs[id].isp_s1_fmerr_cnt->bits.input_height;
350 }
351
bsp_isp_get_s0_ch_hb_cnt(unsigned long id,unsigned int * hb_max,unsigned int * hb_min)352 void bsp_isp_get_s0_ch_hb_cnt(unsigned long id, unsigned int *hb_max, unsigned int *hb_min)
353 {
354 *hb_max = isp_regs[id].isp_s0_hb_cnt->bits.hb_max;
355 *hb_min = isp_regs[id].isp_s0_hb_cnt->bits.hb_min;
356 }
357
bsp_isp_get_s1_ch_hb_cnt(unsigned long id,unsigned int * hb_max,unsigned int * hb_min)358 void bsp_isp_get_s1_ch_hb_cnt(unsigned long id, unsigned int *hb_max, unsigned int *hb_min)
359 {
360 *hb_max = isp_regs[id].isp_s1_hb_cnt->bits.hb_max;
361 *hb_min = isp_regs[id].isp_s1_hb_cnt->bits.hb_min;
362 }
363
bsp_isp_get_wdr_fifo_overflow_line(unsigned long id,unsigned int * decomp_line,unsigned int * comp_line)364 void bsp_isp_get_wdr_fifo_overflow_line(unsigned long id, unsigned int *decomp_line, unsigned int *comp_line)
365 {
366 *decomp_line = isp_regs[id].isp_wdr_fifo_overflow_line->bits.decomp_overflow_line;
367 *comp_line = isp_regs[id].isp_wdr_fifo_overflow_line->bits.comp_overflow_line;
368 }
369
bsp_isp_get_d3d_fifo_overflow_line(unsigned long id,unsigned int * decomp_line,unsigned int * comp_line)370 void bsp_isp_get_d3d_fifo_overflow_line(unsigned long id, unsigned int *decomp_line, unsigned int *comp_line)
371 {
372 *decomp_line = isp_regs[id].isp_d3d_fifo_overflow_line->bits.decomp_overflow_line;
373 *comp_line = isp_regs[id].isp_d3d_fifo_overflow_line->bits.comp_overflow_line;
374 }
375
bsp_isp_set_size(unsigned long id,struct isp_size_settings * size)376 void bsp_isp_set_size(unsigned long id, struct isp_size_settings *size)
377 {
378 isp_regs[id].isp_input_size->bits.input_width = size->ob_black.width;
379 isp_regs[id].isp_input_size->bits.input_height = size->ob_black.height;
380 isp_regs[id].isp_valid_size->bits.valid_width = size->ob_valid.width;
381 isp_regs[id].isp_valid_size->bits.valid_height = size->ob_valid.height;
382 isp_regs[id].isp_valid_start->bits.valid_hor_start = size->ob_start.hor;
383 isp_regs[id].isp_valid_start->bits.valid_ver_start = size->ob_start.ver;
384 }
385
bsp_isp_set_wdr_stride(unsigned long id,int stride)386 void bsp_isp_set_wdr_stride(unsigned long id, int stride)
387 {
388 isp_regs[id].isp_wdr_dma_stride->bits.wdr_dma_len = stride;
389 }
390
bsp_isp_set_d3d_stride(unsigned long id,int k_stride,int raw_stride)391 void bsp_isp_set_d3d_stride(unsigned long id, int k_stride, int raw_stride)
392 {
393 isp_regs[id].isp_d3d_dma_stride->bits.d3d_ref_raw_dma_len = raw_stride;
394 isp_regs[id].isp_d3d_dma_stride->bits.d3d_ref_k_dma_len = k_stride;
395 }
396
bsp_isp_set_wdr_addr0(unsigned long id,dma_addr_t addr)397 void bsp_isp_set_wdr_addr0(unsigned long id, dma_addr_t addr)
398 {
399 writel(addr >> ISP_ADDR_BIT_R_SHIFT, isp_regs[id].isp_wdr_exp_addr0);
400 }
401
bsp_isp_set_d3d_ref_k_addr(unsigned long id,dma_addr_t addr)402 void bsp_isp_set_d3d_ref_k_addr(unsigned long id, dma_addr_t addr)
403 {
404 writel(addr >> ISP_ADDR_BIT_R_SHIFT, isp_regs[id].isp_d3d_ref_k_addr);
405 }
406
bsp_isp_set_d3d_ref_raw_addr(unsigned long id,dma_addr_t addr)407 void bsp_isp_set_d3d_ref_raw_addr(unsigned long id, dma_addr_t addr)
408 {
409 writel(addr >> ISP_ADDR_BIT_R_SHIFT, isp_regs[id].isp_d3d_ref_raw_addr);
410 }
411
bsp_isp_set_d3d_ltf_raw_addr(unsigned long id,dma_addr_t addr)412 void bsp_isp_set_d3d_ltf_raw_addr(unsigned long id, dma_addr_t addr)
413 {
414 writel(addr >> ISP_ADDR_BIT_R_SHIFT, isp_regs[id].isp_d3d_ltf_raw_addr);
415 }
416
bsp_isp_wdr_fifo_en(unsigned long id,unsigned int en)417 void bsp_isp_wdr_fifo_en(unsigned long id, unsigned int en)
418 {
419 isp_regs[id].isp_global_cfg1->bits.wdr_fifo_exit = en;
420 }
421
bsp_isp_d3d_fifo_en(unsigned long id,unsigned int en)422 void bsp_isp_d3d_fifo_en(unsigned long id, unsigned int en)
423 {
424 isp_regs[id].isp_global_cfg1->bits.d3d_ltf_fifo_exit = en;
425 isp_regs[id].isp_global_cfg1->bits.d3d_fifo_exit = en;
426 }
427
bsp_isp_top_control(unsigned long id,int isp_num,int isp0_max_w)428 void bsp_isp_top_control(unsigned long id, int isp_num, int isp0_max_w)
429 {
430 isp_regs[id].isp_top_ctrl->bits.isp0_max_width = isp0_max_w;
431 isp_regs[id].isp_top_ctrl->bits.isp_mode = isp_num - 1;
432 }
433
bsp_isp_set_fifo_mode(unsigned long id,unsigned int mode)434 void bsp_isp_set_fifo_mode(unsigned long id, unsigned int mode)
435 {
436 isp_regs[id].isp_global_cfg1->bits.wdr_fifo_exit = mode;
437 isp_regs[id].isp_global_cfg1->bits.d3d_ltf_fifo_exit = mode;
438 }
439
bsp_isp_min_ddr_size(unsigned long id,unsigned int size)440 void bsp_isp_min_ddr_size(unsigned long id, unsigned int size)
441 {
442 isp_regs[id].isp_global_cfg3->bits.raw_min_ddr_size = size;
443 }
444
bsp_isp_fifo_raw_write(unsigned long id,unsigned int depth)445 void bsp_isp_fifo_raw_write(unsigned long id, unsigned int depth)
446 {
447 isp_regs[id].isp_global_cfg3->bits.fifo_dep_raw_wr = depth;
448 }
449
bsp_isp_k_min_ddr_size(unsigned long id,unsigned int size)450 void bsp_isp_k_min_ddr_size(unsigned long id, unsigned int size)
451 {
452 isp_regs[id].isp_global_cfg3->bits.k_min_ddr_size = size;
453 }
454
455 /*******isp load register which we should write to ddr first*********/
456
bsp_isp_module_enable(unsigned long id,unsigned int module_flag)457 void bsp_isp_module_enable(unsigned long id, unsigned int module_flag)
458 {
459 isp_regs[id].isp_module_bypass0->dwval |= module_flag;
460 if (module_flag & WDR_EN)
461 isp_regs[id].isp_global_cfg1->bits.wdr_en = 1;
462 }
463
bsp_isp_module_disable(unsigned long id,unsigned int module_flag)464 void bsp_isp_module_disable(unsigned long id, unsigned int module_flag)
465 {
466 isp_regs[id].isp_module_bypass0->dwval &= ~module_flag;
467 if (module_flag & WDR_EN)
468 isp_regs[id].isp_global_cfg1->bits.wdr_en = 0;
469 }
470
bsp_isp_load_update_flag(unsigned long id)471 unsigned int bsp_isp_load_update_flag(unsigned long id)
472 {
473 return isp_regs[id].isp_update_flag->dwval;
474 }
475
bsp_isp_set_wdr_raw_lbc_ctrl(unsigned long id,struct isp_lbc_cfg * lbc,unsigned int mode)476 void bsp_isp_set_wdr_raw_lbc_ctrl(unsigned long id, struct isp_lbc_cfg *lbc, unsigned int mode)
477 {
478 isp_regs[id].isp_wdr_raw_lbc_ctrl->bits.line_tar_bits = lbc->line_tar_bits;
479 isp_regs[id].isp_wdr_raw_lbc_ctrl->bits.lmtqp_min = 0;
480 isp_regs[id].isp_wdr_raw_lbc_ctrl->bits.mb_min_bit = lbc->mb_min_bit;
481 isp_regs[id].isp_wdr_raw_lbc_ctrl->bits.lmtqp_en = 0;
482 isp_regs[id].isp_wdr_raw_lbc_ctrl->bits.is_lossy = mode;
483 }
484
bsp_isp_set_d3d_k_lbc_ctrl(unsigned long id,struct isp_lbc_cfg * lbc,unsigned int mode)485 void bsp_isp_set_d3d_k_lbc_ctrl(unsigned long id, struct isp_lbc_cfg *lbc, unsigned int mode)
486 {
487 isp_regs[id].isp_d3d_k_lbc_ctrl->bits.line_tar_bits = lbc->line_tar_bits;
488 isp_regs[id].isp_d3d_k_lbc_ctrl->bits.lmtqp_min = 0;
489 isp_regs[id].isp_d3d_k_lbc_ctrl->bits.mb_min_bit = lbc->mb_min_bit;
490 isp_regs[id].isp_d3d_k_lbc_ctrl->bits.lmtqp_en = 1;
491 isp_regs[id].isp_d3d_k_lbc_ctrl->bits.is_lossy = mode;
492 }
493
bsp_isp_set_d3d_raw_lbc_ctrl(unsigned long id,struct isp_lbc_cfg * lbc,unsigned int mode)494 void bsp_isp_set_d3d_raw_lbc_ctrl(unsigned long id, struct isp_lbc_cfg *lbc, unsigned int mode)
495 {
496 isp_regs[id].isp_d3d_raw_lbc_ctrl->bits.line_tar_bits = lbc->line_tar_bits;
497 isp_regs[id].isp_d3d_raw_lbc_ctrl->bits.lmtqp_min = 0;
498 isp_regs[id].isp_d3d_raw_lbc_ctrl->bits.mb_min_bit = lbc->mb_min_bit;
499 isp_regs[id].isp_d3d_raw_lbc_ctrl->bits.lmtqp_en = 1;
500 isp_regs[id].isp_d3d_raw_lbc_ctrl->bits.is_lossy = mode;
501 }
502
503