1 // Copyright (C) 2022 Beken Corporation 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #pragma once 16 17 #ifdef __cplusplus 18 extern "C" { 19 #endif 20 21 typedef volatile struct { 22 23 /* REG_0x00 */ 24 union { 25 struct { 26 uint32_t adc_mode: 2; /**< bit[0:1] adc mode:0:power down; 1:single step; 2:software control 3: continus modes*/ 27 uint32_t adc_en: 1; /**< bit[2] adc enable/disable, */ 28 uint32_t adc_channel: 4; /**< bit[3-6] adc channel; 0-5 : digital channel, others : analog channel*/ 29 uint32_t adc_setting: 1; /**< bit[7] waiting for sample cycle: 0:4 cycles 1:8 cycyles*/ 30 uint32_t adc_int_clear: 1; /**< bit[8] clear interrupt flag bit*/ 31 uint32_t adc_div: 6; /**< bit[9:14] sample clock division, adc_clk = clk/[2*(adc_div +1)]*/ 32 uint32_t adc_32m_mode: 1; /**< bit[15] adc sample clk set 32M, adc_div is ineffective*/ 33 uint32_t adc_samp_rate: 6; /**< bit[16:21] adc sample rate only effective in continuous mode, every period 34 period=(16+adc_samp_rate)*adc_clk */ 35 uint32_t adc_filter: 7; /**< bit[22:28] 1.continuous mode:adc cumulative num of adc data: if adc_filter>64, the result of accumulative /2 36 will be output, others, the result output directly.2.output sample rate = period/(adc_filter+1)*/ 37 uint32_t adc_busy: 1; /**< bit[29] adc busy flag */ 38 uint32_t fifo_empty: 1; /**< bit[30] fifo empty flag: 1:fifo empty; 0:not empty */ 39 uint32_t fifo_full: 1; /**< bit[31] fifo full flag: 1:fifo full; 0:not full*/ 40 }; 41 uint32_t v; 42 } ctrl; 43 44 /* REG_0x01 */ 45 uint32_t adc_raw_data; /**original adc output data*/ 46 47 /* REG_0x02 */ 48 union { 49 struct { 50 uint32_t fifo_level: 5; /**< bit[0:4] only effective in continuous mode, when fifo data num > fifo_level, generate int */ 51 uint32_t steady_ctrl: 3; /**< bit[5:7] when adc power on wait (steady_ctrl +1)*8 adc clk to send valid*/ 52 53 uint32_t calibration_triggle: 1;/**< bit[8] write 1 to start clib mode and auto calib, save the offset to mem*/ 54 uint32_t calibration_done: 1;/**< bit[9] tihs bit will be set as 1 after auto calib and generate interrupt*/ 55 uint32_t bypass_calibration: 1;/**< bit[10] bypass the calib result not offset the adc_raw_data value*/ 56 57 uint32_t rfu: 21; /**< bit[31:11] */ 58 }; 59 60 uint32_t v; 61 } steady_ctrl; 62 63 /* REG_0x03 */ 64 union { 65 struct { 66 uint32_t sat_ctrl: 2; /**< bit[0:1] adc saturation processing: 67 10 bit: 68 00: sel [15:0] 69 01: sel [16:0] 70 10/11: ineffective 71 12bit: 72 00: sel [18:3] + round[2:0] 73 01: sel [17:2]+ round[1:0] 74 10: sel [16:1]+ round[0] 75 11: sel [15:0]*/ 76 uint32_t sat_enable: 1; /**< bit[2] enable saturation*/ 77 uint32_t over_flow: 1; /**< bit[3] adc over flag*/ 78 79 uint32_t reserved: 28; /**< bit[4:31] */ 80 }; 81 82 uint32_t v; 83 } sat_ctrl; 84 85 /* REG_0x04 */ 86 uint32_t adc_data; /**adc output data after satutate processs*/ 87 88 /* REG_0x05 */ 89 union { 90 struct { 91 uint32_t fifo_data_16: 16; /**< bit[0:15] adc fifo data:read only, it is read out after calibration done.*/ 92 uint32_t reserved: 16; /**< bit[16:31] */ 93 }; 94 95 uint32_t v; 96 } fifo_data; 97 98 /* REG_0x06 */ 99 union { 100 struct { 101 /**< bit[0:11] save the dc-offset value of SADC. 102 1. The value is wrote to flash in factory 103 2. When chip power up, SW should clear the default value in this REG. 104 3. SW read the value from flash, and save the value to this REG 105 4. SADC auto calibration will use the value from this REG.*/ 106 uint32_t dc_offset: 12; 107 uint32_t reserved: 20; /**< bit[12:31] */ 108 }; 109 110 uint32_t v; 111 } dc_offset_ctrl; 112 113 /* REG_0x07 */ 114 union { 115 struct { 116 /**< bit[0:16] The value is N.xxx(N == Bit[16], xxx == Bit[0-15] is decimals) 117 1. The value is wrote to flash in factory 118 2. When chip power up, SW should clear the default value in this REG. 119 3. SW read the value from flash, and save the value to this REG 120 4. SADC auto calibration will use the value from this REG.*/ 121 uint32_t gain: 17; 122 uint32_t reserved: 16; /**< bit[17:31] */ 123 }; 124 125 uint32_t v; 126 } gain_ctrl; 127 }adc_hw_t; 128 129 #ifdef __cplusplus 130 } 131 #endif 132 133