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/device/board/hisilicon/hispark_aries/uboot/secureboot_release/ddr_init/drv/
Dddr_phy_s40.h268 #define DDR_PHY_VREF_HOST_SET(base_phy, rank, bytenum, byte_index, val) \ argument
272 #define DDR_PHY_VREF_HOST_GET(base_phy, rank, byte_index, val) \ argument
293 #define DDR_PHY_VREF_DRAM_SET(base_phy, val, byte_index) argument
294 #define DDR_PHY_VREF_DRAM_GET(base_phy, val, byte_index) argument
Dddr_training_impl.c532 unsigned int byte_index = cfg->cur_byte; in ddr_phy_set_dq_bdl() local
563 unsigned int byte_index = cfg->cur_byte; in ddr_phy_get_dq_bdl() local
907 unsigned int byte_index = cfg->cur_byte; in ddr_adjust_get_average() local
1345 unsigned int byte_index = cfg->cur_byte; in ddr_dataeye_deskew() local
1850 unsigned int byte_index = cfg->cur_byte; in ddr_mpr_extract() local
1913 unsigned int byte_index, dq_index; in ddr_mpr_find_rdq() local
1959 unsigned int byte_index = cfg->cur_byte; in ddr_mpr_find_rdqs() local
2088 unsigned int byte_index; in ddr_vref_save_bdl() local
2109 unsigned int byte_index; in ddr_vref_restore_bdl() local
3913 unsigned int byte_index; in ddr_dcc_get_ck0_win() local
[all …]
Dddr_phy_t12_v100.h306 #define DDR_PHY_VREF_HOST_SET(base_phy, rank, bytenum, byte_index, val) \ argument
322 #define DDR_PHY_VREF_HOST_GET(base_phy, rank, byte_index, val) \ argument
357 #define DDR_PHY_VREF_DRAM_SET(base_phy, val, byte_index) \ argument
380 #define DDR_PHY_VREF_DRAM_GET(base_phy, val, byte_index) \ argument
Dddr_phy_t12_v101.h305 #define DDR_PHY_VREF_HOST_SET(base_phy, rank, bytenum, byte_index, val) \ argument
321 #define DDR_PHY_VREF_HOST_GET(base_phy, rank, byte_index, val) \ argument
356 #define DDR_PHY_VREF_DRAM_SET(base_phy, val, byte_index) \ argument
379 #define DDR_PHY_VREF_DRAM_GET(base_phy, val, byte_index) \ argument
Dddr_phy_t16.h293 #define DDR_PHY_VREF_HOST_SET(base_phy, rank, bytenum, byte_index, val) \ argument
305 #define DDR_PHY_VREF_HOST_GET(base_phy, rank, byte_index, val) \ argument
330 #define DDR_PHY_VREF_DRAM_SET(base_phy, val, byte_index) \ argument
353 #define DDR_PHY_VREF_DRAM_GET(base_phy, val, byte_index) \ argument
Dddr_phy_t28.h291 #define DDR_PHY_VREF_HOST_SET(base_phy, rank, bytenum, byte_index, val) \ argument
300 #define DDR_PHY_VREF_HOST_GET(base_phy, rank, byte_index, val) \ argument
330 #define DDR_PHY_VREF_DRAM_SET(base_phy, val, byte_index) \ argument
353 #define DDR_PHY_VREF_DRAM_GET(base_phy, val, byte_index) \ argument
Dddr_interface.h122 unsigned int byte_index; member
Dddr_ddrc_v500.h110 #define DMC_MPR_CHECK_BIT_128_255(base_dmc, byte_index, dq_index) 0 argument
/device/board/hisilicon/hispark_taurus/uboot/secureboot_release/ddr_init/drv/
Dddr_phy_s40.h269 #define DDR_PHY_VREF_HOST_SET(base_phy, rank, bytenum, byte_index, val) \ argument
273 #define DDR_PHY_VREF_HOST_GET(base_phy, rank, byte_index, val) \ argument
294 #define DDR_PHY_VREF_DRAM_SET(base_phy, val, byte_index) argument
295 #define DDR_PHY_VREF_DRAM_GET(base_phy, val, byte_index) argument
Dddr_training_impl.c531 unsigned int byte_index = cfg->cur_byte; in ddr_phy_set_dq_bdl() local
562 unsigned int byte_index = cfg->cur_byte; in ddr_phy_get_dq_bdl() local
906 unsigned int byte_index = cfg->cur_byte; in ddr_adjust_get_average() local
1344 unsigned int byte_index = cfg->cur_byte; in ddr_dataeye_deskew() local
1852 unsigned int byte_index = cfg->cur_byte; in ddr_mpr_extract() local
1915 unsigned int byte_index, dq_index; in ddr_mpr_find_rdq() local
1961 unsigned int byte_index = cfg->cur_byte; in ddr_mpr_find_rdqs() local
2090 unsigned int byte_index; in ddr_vref_save_bdl() local
2111 unsigned int byte_index; in ddr_vref_restore_bdl() local
3915 unsigned int byte_index; in ddr_dcc_get_ck0_win() local
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Dddr_phy_t16.h294 #define DDR_PHY_VREF_HOST_SET(base_phy, rank, bytenum, byte_index, val) \ argument
306 #define DDR_PHY_VREF_HOST_GET(base_phy, rank, byte_index, val) \ argument
331 #define DDR_PHY_VREF_DRAM_SET(base_phy, val, byte_index) \ argument
354 #define DDR_PHY_VREF_DRAM_GET(base_phy, val, byte_index) \ argument
Dddr_phy_t28.h292 #define DDR_PHY_VREF_HOST_SET(base_phy, rank, bytenum, byte_index, val) \ argument
301 #define DDR_PHY_VREF_HOST_GET(base_phy, rank, byte_index, val) \ argument
331 #define DDR_PHY_VREF_DRAM_SET(base_phy, val, byte_index) \ argument
354 #define DDR_PHY_VREF_DRAM_GET(base_phy, val, byte_index) \ argument
Dddr_phy_t12_v100.h307 #define DDR_PHY_VREF_HOST_SET(base_phy, rank, bytenum, byte_index, val) \ argument
323 #define DDR_PHY_VREF_HOST_GET(base_phy, rank, byte_index, val) \ argument
358 #define DDR_PHY_VREF_DRAM_SET(base_phy, val, byte_index) \ argument
381 #define DDR_PHY_VREF_DRAM_GET(base_phy, val, byte_index) \ argument
Dddr_phy_t12_v101.h306 #define DDR_PHY_VREF_HOST_SET(base_phy, rank, bytenum, byte_index, val) \ argument
322 #define DDR_PHY_VREF_HOST_GET(base_phy, rank, byte_index, val) \ argument
357 #define DDR_PHY_VREF_DRAM_SET(base_phy, val, byte_index) \ argument
380 #define DDR_PHY_VREF_DRAM_GET(base_phy, val, byte_index) \ argument
Dddr_interface.h122 unsigned int byte_index; member
Dddr_ddrc_v500.h110 #define DMC_MPR_CHECK_BIT_128_255(base_dmc, byte_index, dq_index) 0 argument
/device/board/isoftstone/zhiyuan/kernel/driver/drivers/vin/vin-cci/
Dcsi_cci_reg.c202 static void cci_wr_tx_buf(unsigned int sel, unsigned int byte_index, in cci_wr_tx_buf()
219 static void cci_rd_tx_buf(unsigned int sel, unsigned int byte_index, in cci_rd_tx_buf()
/device/board/isoftstone/yangfan/kernel/src/driv/net/rockchip_wlan/rkwifi/bcmdhd/
Dwl_cfgscan.c3545 int byte_index = 0; in wl_cfg80211_scan_mac_config() local