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Searched defs:byte_num (Results 1 – 25 of 25) sorted by relevance

/device/board/hisilicon/hispark_taurus/uboot/secureboot_release/ddr_init/drv/cmd_bin/
Dddr_training_cmd.c273 static void ddr_dump_wdqs_result(unsigned int base_phy, unsigned int byte_num, in ddr_dump_wdqs_result()
291 static void ddr_dump_wdq_phase_result(unsigned int base_phy, unsigned int byte_num, in ddr_dump_wdq_phase_result()
306 static void ddr_dump_wdq_bdl_result(unsigned int base_phy, unsigned int byte_num, in ddr_dump_wdq_bdl_result()
329 static void ddr_dump_wdm_result(unsigned int base_phy, unsigned int byte_num, in ddr_dump_wdm_result()
345 static void ddr_dump_rdqs_result(unsigned int base_phy, unsigned int byte_num, in ddr_dump_rdqs_result()
363 static void ddr_dump_rdq_bdl_result(unsigned int base_phy, unsigned int byte_num, in ddr_dump_rdq_bdl_result()
390 unsigned int byte_num = ddrtr_data->byte_num; in dump_result() local
/device/board/hisilicon/hispark_aries/uboot/secureboot_release/ddr_init/drv/
Dddr_training_impl.c588 unsigned int byte_num; in ddr_phy_get_byte_num() local
1481 unsigned int byte_num = cfg->phy[cfg->phy_idx].total_byte_num; in ddr_hw_read_adj() local
1508 unsigned int byte_num = cfg->phy[cfg->phy_idx].total_byte_num; in ddr_training_get_rdqs() local
1519 unsigned int byte_num = cfg->phy[cfg->phy_idx].total_byte_num; in ddr_training_set_rdqs() local
1530 unsigned int byte_num = cfg->phy[cfg->phy_idx].total_byte_num; in ddr_hw_training_adjust_rdqs() local
1603 unsigned int byte_num = cfg->phy[cfg->phy_idx].total_byte_num; in ddr_hw_dataeye_read() local
1633 unsigned int byte_num = cfg->phy[cfg->phy_idx].total_byte_num; in ddr_hw_training_ctl() local
2015 unsigned int byte_num = GET_BYTE_NUM(cfg); in ddr_mpr_training() local
2517 unsigned int byte_num = GET_BYTE_NUM(cfg); in ddr_wl_wdq_adjust() local
2595 unsigned int byte_num = GET_BYTE_NUM(cfg); in ddr_wl_bdl_sync() local
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Dddr_interface.h98 unsigned int byte_num; member
Dddr_phy_s40.h287 #define DDR_PHY_VREF_HOST_DISPLAY_CMD(base_phy, rank, byte_num) \ argument
296 #define DDR_PHY_VREF_DRAM_DISPLAY_CMD(base_phy, byte_num) argument
Dddr_phy_t12_v100.h345 #define DDR_PHY_VREF_HOST_DISPLAY_CMD(base_phy, rank, byte_num) \ argument
392 #define DDR_PHY_VREF_DRAM_DISPLAY_CMD(base_phy, byte_num) \ argument
Dddr_phy_t12_v101.h344 #define DDR_PHY_VREF_HOST_DISPLAY_CMD(base_phy, rank, byte_num) \ argument
391 #define DDR_PHY_VREF_DRAM_DISPLAY_CMD(base_phy, byte_num) \ argument
Dddr_phy_t16.h319 #define DDR_PHY_VREF_HOST_DISPLAY_CMD(base_phy, rank, byte_num) \ argument
365 #define DDR_PHY_VREF_DRAM_DISPLAY_CMD(base_phy, byte_num) \ argument
Dddr_phy_t28.h318 #define DDR_PHY_VREF_HOST_DISPLAY_CMD(base_phy, rank, byte_num) \ argument
365 #define DDR_PHY_VREF_DRAM_DISPLAY_CMD(base_phy, byte_num) \ argument
Dddr_training_impl.h279 unsigned int byte_num; member
/device/board/hisilicon/hispark_taurus/uboot/secureboot_release/ddr_init/drv/
Dddr_training_impl.c587 unsigned int byte_num; in ddr_phy_get_byte_num() local
1480 unsigned int byte_num = cfg->phy[cfg->phy_idx].total_byte_num; in ddr_hw_read_adj() local
1507 unsigned int byte_num = cfg->phy[cfg->phy_idx].total_byte_num; in ddr_training_get_rdqs() local
1518 unsigned int byte_num = cfg->phy[cfg->phy_idx].total_byte_num; in ddr_training_set_rdqs() local
1529 unsigned int byte_num = cfg->phy[cfg->phy_idx].total_byte_num; in ddr_hw_training_adjust_rdqs() local
1602 unsigned int byte_num = cfg->phy[cfg->phy_idx].total_byte_num; in ddr_hw_dataeye_read() local
1632 unsigned int byte_num = cfg->phy[cfg->phy_idx].total_byte_num; in ddr_hw_training_ctl() local
2017 unsigned int byte_num = GET_BYTE_NUM(cfg); in ddr_mpr_training() local
2519 unsigned int byte_num = GET_BYTE_NUM(cfg); in ddr_wl_wdq_adjust() local
2597 unsigned int byte_num = GET_BYTE_NUM(cfg); in ddr_wl_bdl_sync() local
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Dddr_interface.h98 unsigned int byte_num; member
Dddr_phy_s40.h288 #define DDR_PHY_VREF_HOST_DISPLAY_CMD(base_phy, rank, byte_num) \ argument
297 #define DDR_PHY_VREF_DRAM_DISPLAY_CMD(base_phy, byte_num) argument
Dddr_phy_t16.h320 #define DDR_PHY_VREF_HOST_DISPLAY_CMD(base_phy, rank, byte_num) \ argument
366 #define DDR_PHY_VREF_DRAM_DISPLAY_CMD(base_phy, byte_num) \ argument
Dddr_phy_t28.h319 #define DDR_PHY_VREF_HOST_DISPLAY_CMD(base_phy, rank, byte_num) \ argument
366 #define DDR_PHY_VREF_DRAM_DISPLAY_CMD(base_phy, byte_num) \ argument
Dddr_phy_t12_v100.h346 #define DDR_PHY_VREF_HOST_DISPLAY_CMD(base_phy, rank, byte_num) \ argument
393 #define DDR_PHY_VREF_DRAM_DISPLAY_CMD(base_phy, byte_num) \ argument
Dddr_phy_t12_v101.h345 #define DDR_PHY_VREF_HOST_DISPLAY_CMD(base_phy, rank, byte_num) \ argument
392 #define DDR_PHY_VREF_DRAM_DISPLAY_CMD(base_phy, byte_num) \ argument
Dddr_training_impl.h280 unsigned int byte_num; member
/device/soc/rockchip/rk3588/kernel/drivers/video/rockchip/rga3/
Drga2_mmu_info.c830 uint32_t sw, byte_num; in rga2_mmu_info_color_palette_mode() local
Drga2_reg_info.c1444 u32 byte_num; in RGA2_set_reg_color_palette() local
/device/soc/esp/esp32/components/hal/esp32/include/hal/
Di2c_ll.h32 uint32_t byte_num: 8, member
/device/board/isoftstone/yangfan/kernel/src/driv/video/rockchip/rga2/
Drga2_reg_info.c867 RK_U32 byte_num; in RGA2_set_reg_color_palette() local
Drga2_mmu_info.c1381 uint32_t sw, byte_num; in rga2_mmu_info_color_palette_mode() local
/device/soc/rockchip/common/vendor/drivers/video/rockchip/rga2/
Drga2_reg_info.c1255 unsigned int byte_num; in RGA2_set_reg_color_palette() local
Drga2_mmu_info.c1248 uint32_t sw, byte_num; in rga2_mmu_info_color_palette_mode() local
/device/soc/esp/esp32/components/soc/esp32/include/soc/
Di2c_struct.h256 …uint32_t byte_num: 8; /*Byte_num represent the number of data need to be send or… member