1 // Copyright (C) 2022 Beken Corporation 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #pragma once 16 17 #ifdef __cplusplus 18 extern "C" { 19 #endif 20 21 //TODO add full comments according to reg spec 22 typedef volatile struct { 23 struct { 24 union { 25 struct { 26 /* PWM mode 27 * 000: idle 28 * 001: PWM mode 29 * 010: Timer mode 30 * 011: Counter mode 31 * 100: Capture mode (pos -> pos) 32 * 101: Capture mode (neg -> neg) 33 * 110: Capture mode (edge -> edge) 34 */ 35 uint32_t chan0_mode: 3; /**< bit[0:2] pwm0_mode, R/W */ 36 uint32_t chan0_en: 1; /**< bit[3] pwm0_int_enable, R/W */ 37 uint32_t chan0_int_en: 1; /**< bit[4] */ 38 uint32_t chan0_timer_stop: 1; /**< bit[5] */ 39 uint32_t chan0_init_level: 1; /**< bit[6] */ 40 uint32_t chan0_cfg_update: 1; /**< bit[7] */ 41 42 uint32_t chan1_mode: 3; /**< bit[8:10] pwm1_mode, R/W */ 43 uint32_t chan1_en: 1; /**< bit[11] pwm1_int_enable, R/W */ 44 uint32_t chan1_int_en: 1; /**< bit[12] */ 45 uint32_t chan1_timer_stop: 1; /**< bit[13] */ 46 uint32_t chan1_init_level: 1; /**< bit[14] */ 47 uint32_t chan1_cfg_update: 1; /**< bit[15] */ 48 49 uint32_t pre_div: 8; /**< bit[16:23] */ 50 uint32_t group_pwm_en: 1; /**< bit[24] */ 51 uint32_t group_en: 1; /**< bit[25] */ 52 53 uint32_t reserved: 4; /**< bit[26:29] */ 54 55 uint32_t chan0_int_st: 1; /**< bit[30] */ 56 uint32_t chan1_int_st: 1; /**< bit[31] */ 57 }; 58 uint32_t v; 59 } ctrl; 60 61 struct { 62 uint32_t t1; 63 uint32_t t2; 64 uint32_t t3; 65 uint32_t t4; /**< PWM period cycle, t4 >= (t1 + t2 + t3) */ 66 } duty_cycle[SOC_PWM_CHAN_NUM_PER_GROUP]; 67 68 union { 69 struct { 70 uint32_t rd0: 1; /**< bit[0], W, software write 1 to begin the read, HW clear it when data ready */ 71 uint32_t rd1: 1; /**< bit[0], R/W, */ 72 uint32_t reserved: 30; /**< bit[2:31] */ 73 }; 74 uint32_t v; 75 } cnt_read_ctrl; 76 77 uint32_t cnt_or_capture_rdata[SOC_PWM_CHAN_NUM_PER_GROUP]; 78 79 uint32_t reserved[0xe - 0xb - 1]; 80 union { 81 struct { 82 uint32_t read_en: 1; /**< bit[0], W, Software write '1', and hardware clear it after finish read*/ 83 uint32_t chan_id: 3; /**< bit[1:3] */ 84 uint32_t reserved: 28; /**< bit[4:31] */ 85 }; 86 uint32_t v; 87 } counter_read_ctrl; 88 89 uint32_t cnt_read; /** dump this part*/ 90 91 92 } group[SOC_PWM_GROUP_NUM]; 93 } pwm_hw_t; 94 95 #ifdef __cplusplus 96 } 97 #endif 98