1 /* 2 * include/linux/amlogic/media/vout/lcd/lcd_vout.h 3 * 4 * Copyright (C) 2017 Amlogic, Inc. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 */ 17 18 #ifndef _INC_LCD_VOUT_H 19 #define _INC_LCD_VOUT_H 20 #include <linux/types.h> 21 #include <linux/platform_device.h> 22 #include <linux/amlogic/aml_gpio_consumer.h> 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/amlogic/media/vout/vout_notify.h> 25 #include <linux/amlogic/iomap.h> 26 27 extern void lcd_vlock_m_update(unsigned int vlock_m); 28 extern void lcd_vlock_frac_update(unsigned int vlock_farc); 29 30 /* ********************************** 31 * debug print define 32 * ********************************** 33 */ 34 #define LCD_DEBUG_LEVEL_NORMAL (1 << 0) 35 #define LCD_DEBUG_LEVEL_CLK (1 << 1) 36 #define LCD_DEBUG_LEVEL_VSYNC (1 << 3) 37 38 #define LCD_DEBUG_VSYNC_INTERVAL 60 39 40 /* #define LCD_DEBUG_INFO */ 41 extern unsigned char lcd_debug_print_flag; 42 #define LCDPR(fmt, args...) pr_info("lcd: "fmt"", ## args) 43 #define LCDERR(fmt, args...) pr_err("lcd: error: "fmt"", ## args) 44 45 /* ********************************** 46 * clk parameter bit define 47 * pll_ctrl, div_ctrl, clk_ctrl 48 * ********************************** 49 */ 50 /* ******** pll_ctrl ******** */ 51 #define PLL_CTRL_OD3 20 /* [21:20] */ 52 #define PLL_CTRL_OD2 18 /* [19:18] */ 53 #define PLL_CTRL_OD1 16 /* [17:16] */ 54 #define PLL_CTRL_N 9 /* [13:9] */ 55 #define PLL_CTRL_M 0 /* [8:0] */ 56 57 /* ******** div_ctrl ******** */ 58 #define DIV_CTRL_EDP_DIV1 24 /* [26:24] */ 59 #define DIV_CTRL_EDP_DIV0 20 /* [23:20] */ 60 #define DIV_CTRL_DIV_SEL 8 /* [15:8] */ 61 #define DIV_CTRL_XD 0 /* [7:0] */ 62 63 /* ******** clk_ctrl ******** */ 64 #define CLK_CTRL_LEVEL 28 /* [30:28] */ 65 #define CLK_CTRL_FRAC_SHIFT 24 /* [24] */ 66 #define CLK_CTRL_FRAC 0 /* [18:0] */ 67 68 /* ********************************** 69 * VENC to TCON sync delay 70 * ********************************** 71 */ 72 #define TTL_DELAY 13 73 #define PRE_DE_DELAY 8 74 75 76 /* ********************************** 77 * global control define 78 * ********************************** 79 */ 80 enum lcd_mode_e { 81 LCD_MODE_TV = 0, 82 LCD_MODE_TABLET, 83 LCD_MODE_MAX, 84 }; 85 86 87 enum lcd_chip_e { 88 LCD_CHIP_GXL = 0, 89 LCD_CHIP_GXM, /* 1 */ 90 LCD_CHIP_TXL, /* 2 */ 91 LCD_CHIP_TXLX, /* 3 */ 92 LCD_CHIP_AXG, /* 4 */ 93 LCD_CHIP_G12A, /* 5 */ 94 LCD_CHIP_G12B, /* 6 */ 95 LCD_CHIP_TL1, /* 7 */ 96 LCD_CHIP_SM1, /* 8 */ 97 LCD_CHIP_TM2, /* 9 */ 98 LCD_CHIP_MAX, 99 }; 100 101 struct lcd_data_s { 102 enum lcd_chip_e chip_type; 103 const char *chip_name; 104 int *reg_map_table; 105 }; 106 107 enum lcd_type_e { 108 LCD_TTL = 0, 109 LCD_LVDS, 110 LCD_VBYONE, 111 LCD_MIPI, 112 LCD_MLVDS, 113 LCD_P2P, 114 LCD_TYPE_MAX, 115 }; 116 117 #define MOD_LEN_MAX 30 118 struct lcd_basic_s { 119 char model_name[MOD_LEN_MAX]; 120 enum lcd_type_e lcd_type; 121 unsigned short lcd_bits; 122 123 unsigned short h_active; /* Horizontal display area */ 124 unsigned short v_active; /* Vertical display area */ 125 unsigned short h_period; /* Horizontal total period time */ 126 unsigned short v_period; /* Vertical total period time */ 127 unsigned short h_period_min; 128 unsigned short h_period_max; 129 unsigned short v_period_min; 130 unsigned short v_period_max; 131 unsigned int lcd_clk_min; 132 unsigned int lcd_clk_max; 133 134 unsigned int screen_width; /* screen physical width(unit: mm) */ 135 unsigned int screen_height; /* screen physical height(unit: mm) */ 136 }; 137 138 #define LCD_CLK_FRAC_UPDATE (1 << 0) 139 #define LCD_CLK_PLL_CHANGE (1 << 1) 140 struct lcd_timing_s { 141 unsigned char clk_auto; /* clk parameters auto generation */ 142 unsigned char fr_adjust_type; /* 0=clock, 1=htotal, 2=vtotal */ 143 unsigned char clk_change; /* internal used */ 144 unsigned int lcd_clk; /* pixel clock(unit: Hz) */ 145 unsigned int lcd_clk_dft; /* internal used */ 146 unsigned int bit_rate; /* Hz */ 147 unsigned int h_period_dft; /* internal used */ 148 unsigned int v_period_dft; /* internal used */ 149 unsigned int pll_ctrl; /* pll settings */ 150 unsigned int div_ctrl; /* divider settings */ 151 unsigned int clk_ctrl; /* clock settings */ 152 unsigned int ss_level; /* [15:12]: ss_freq, [11:8]: ss_mode, 153 * [7:0]: ss_level 154 */ 155 156 unsigned int sync_duration_num; 157 unsigned int sync_duration_den; 158 159 unsigned short video_on_pixel; 160 unsigned short video_on_line; 161 162 unsigned short hsync_width; 163 unsigned short hsync_bp; 164 unsigned short hsync_pol; 165 unsigned short vsync_width; 166 unsigned short vsync_bp; 167 unsigned short vsync_pol; 168 /* unsigned int vsync_h_phase; // [31]sign, [15:0]value */ 169 unsigned int h_offset; 170 unsigned int v_offset; 171 172 unsigned short de_hs_addr; 173 unsigned short de_he_addr; 174 unsigned short de_vs_addr; 175 unsigned short de_ve_addr; 176 177 unsigned short hs_hs_addr; 178 unsigned short hs_he_addr; 179 unsigned short hs_vs_addr; 180 unsigned short hs_ve_addr; 181 182 unsigned short vs_hs_addr; 183 unsigned short vs_he_addr; 184 unsigned short vs_vs_addr; 185 unsigned short vs_ve_addr; 186 }; 187 188 /* ********************************** 189 * HDR info define 190 * ********************************** 191 */ 192 struct lcd_optical_info_s { 193 unsigned int hdr_support; 194 unsigned int features; 195 unsigned int primaries_r_x; 196 unsigned int primaries_r_y; 197 unsigned int primaries_g_x; 198 unsigned int primaries_g_y; 199 unsigned int primaries_b_x; 200 unsigned int primaries_b_y; 201 unsigned int white_point_x; 202 unsigned int white_point_y; 203 unsigned int luma_max; 204 unsigned int luma_min; 205 unsigned int luma_avg; 206 }; 207 208 struct ttl_config_s { 209 unsigned int clk_pol; 210 unsigned int sync_valid; /* [1]DE, [0]hvsync */ 211 unsigned int swap_ctrl; /* [1]rb swap, [0]bit swap */ 212 }; 213 214 #define LVDS_PHY_VSWING_DFT 3 215 #define LVDS_PHY_PREEM_DFT 0 216 #define LVDS_PHY_CLK_VSWING_DFT 0 217 #define LVDS_PHY_CLK_PREEM_DFT 0 218 struct lvds_config_s { 219 unsigned int lvds_vswing; 220 unsigned int lvds_repack; 221 unsigned int dual_port; 222 unsigned int pn_swap; 223 unsigned int port_swap; 224 unsigned int lane_reverse; 225 unsigned int port_sel; 226 unsigned int phy_vswing; 227 unsigned int phy_preem; 228 unsigned int phy_clk_vswing; 229 unsigned int phy_clk_preem; 230 }; 231 232 #define VX1_PHY_VSWING_DFT 3 233 #define VX1_PHY_PREEM_DFT 0 234 235 #define VX1_PWR_ON_RESET_DLY_DFT 500 /* 500ms */ 236 #define VX1_HPD_DATA_DELAY_DFT 10 /* 10ms */ 237 #define VX1_CDR_TRAINING_HOLD_DFT 200 /* 200ms */ 238 239 struct vbyone_config_s { 240 unsigned int lane_count; 241 unsigned int region_num; 242 unsigned int byte_mode; 243 unsigned int color_fmt; 244 unsigned int phy_div; 245 unsigned int phy_vswing; /*[4]:ext_pullup, [3:0]vswing*/ 246 unsigned int phy_preem; 247 unsigned int intr_en; 248 unsigned int vsync_intr_en; 249 250 unsigned int ctrl_flag; 251 /* bit[0]:power_on_reset_en 252 * bit[1]:hpd_data_delay_en 253 * bit[2]:cdr_training_hold_en 254 * bit[3]:hw_filter_en 255 * bit[5:4]:sw_filter 256 */ 257 258 /* ctrl timing */ 259 unsigned int power_on_reset_delay; /* ms */ 260 unsigned int hpd_data_delay; /* ms */ 261 unsigned int cdr_training_hold; /* ms */ 262 /* hw filter */ 263 unsigned int hw_filter_time; 264 unsigned int hw_filter_cnt; 265 }; 266 267 /* mipi-dsi config */ 268 /* Operation mode parameters */ 269 #define OPERATION_VIDEO_MODE 0 270 #define OPERATION_COMMAND_MODE 1 271 272 #define SYNC_PULSE 0x0 273 #define SYNC_EVENT 0x1 274 #define BURST_MODE 0x2 275 276 /* command config */ 277 #define DSI_CMD_SIZE_INDEX 1 /* byte[1] */ 278 #define DSI_GPIO_INDEX 2 /* byte[2] */ 279 280 #define DSI_INIT_ON_MAX 400 281 #define DSI_INIT_OFF_MAX 30 282 283 #define DSI_READ_CNT_MAX 30 284 struct dsi_read_s { 285 unsigned char flag; 286 unsigned char reg; 287 unsigned char cnt; 288 unsigned char *value; 289 unsigned char ret_code; 290 291 unsigned int line_start; 292 unsigned int line_end; 293 }; 294 295 struct dsi_config_s { 296 unsigned char lane_num; 297 unsigned int bit_rate_max; /* MHz */ 298 unsigned int bit_rate_min; /* MHz*/ 299 unsigned int clk_factor; /* bit_rate/pclk */ 300 unsigned int factor_numerator; 301 unsigned int factor_denominator; /* 100 */ 302 unsigned char operation_mode_init; /* 0=video mode, 1=command mode */ 303 unsigned char operation_mode_display; /* 0=video mode, 1=command mode */ 304 unsigned char video_mode_type; /* 0=sync_pulse, 1=sync_event, 2=burst */ 305 unsigned char clk_always_hs; /* 0=disable, 1=enable */ 306 unsigned char phy_switch; /* 0=auto, 1=standard, 2=slow */ 307 308 unsigned int venc_data_width; 309 unsigned int dpi_data_format; 310 311 unsigned char *dsi_init_on; 312 unsigned char *dsi_init_off; 313 unsigned char extern_init; 314 315 unsigned char check_en; 316 unsigned char check_reg; 317 unsigned char check_cnt; 318 unsigned char check_state; 319 320 unsigned char current_mode; 321 322 struct dsi_read_s *dread; 323 }; 324 325 struct mlvds_config_s { 326 unsigned int channel_num; 327 unsigned int channel_sel0; 328 unsigned int channel_sel1; 329 unsigned int clk_phase; /* [13:12]=clk01_pi_sel, 330 * [11:8]=pi2, [7:4]=pi1, [3:0]=pi0 331 */ 332 unsigned int pn_swap; 333 unsigned int bit_swap; /* MSB/LSB reverse */ 334 unsigned int phy_vswing; 335 unsigned int phy_preem; 336 337 /* internal used */ 338 unsigned int pi_clk_sel; /* bit[9:0] */ 339 }; 340 341 enum p2p_type_e { 342 P2P_CEDS = 0, 343 P2P_CMPI, 344 P2P_ISP, 345 P2P_EPI, 346 P2P_CHPI = 0x10, /* low common mode */ 347 P2P_CSPI, 348 P2P_USIT, 349 P2P_MAX, 350 }; 351 352 struct p2p_config_s { 353 unsigned int p2p_type; 354 unsigned int lane_num; 355 unsigned int channel_sel0; 356 unsigned int channel_sel1; 357 unsigned int pn_swap; 358 unsigned int bit_swap; /* MSB/LSB reverse */ 359 unsigned int phy_vswing; 360 unsigned int phy_preem; 361 }; 362 363 struct lcd_control_config_s { 364 struct ttl_config_s *ttl_config; 365 struct lvds_config_s *lvds_config; 366 struct vbyone_config_s *vbyone_config; 367 struct dsi_config_s *mipi_config; 368 struct mlvds_config_s *mlvds_config; 369 struct p2p_config_s *p2p_config; 370 unsigned int *vlock_param; 371 }; 372 373 /* ********************************** 374 * power control define 375 * ********************************** 376 */ 377 enum lcd_power_type_e { 378 LCD_POWER_TYPE_CPU = 0, 379 LCD_POWER_TYPE_PMU, 380 LCD_POWER_TYPE_SIGNAL, 381 LCD_POWER_TYPE_EXTERN, 382 LCD_POWER_TYPE_WAIT_GPIO, 383 LCD_POWER_TYPE_CLK_SS, 384 LCD_POWER_TYPE_MAX, 385 }; 386 387 enum lcd_pmu_gpio_e { 388 LCD_PMU_GPIO0 = 0, 389 LCD_PMU_GPIO1, 390 LCD_PMU_GPIO2, 391 LCD_PMU_GPIO3, 392 LCD_PMU_GPIO4, 393 LCD_PMU_GPIO_MAX, 394 }; 395 396 #define LCD_CLK_SS_BIT_FREQ 0 397 #define LCD_CLK_SS_BIT_MODE 4 398 399 #define LCD_GPIO_MAX 0xff 400 #define LCD_GPIO_OUTPUT_LOW 0 401 #define LCD_GPIO_OUTPUT_HIGH 1 402 #define LCD_GPIO_INPUT 2 403 404 /* Power Control */ 405 #define LCD_CPU_GPIO_NUM_MAX 10 406 struct lcd_cpu_gpio_s { 407 char name[15]; 408 struct gpio_desc *gpio; 409 int probe_flag; 410 int register_flag; 411 }; 412 413 #define LCD_PMU_GPIO_NUM_MAX 3 414 struct lcd_pmu_gpio_s { 415 char name[15]; 416 int gpio; 417 }; 418 419 #define LCD_PWR_STEP_MAX 15 420 struct lcd_power_step_s { 421 unsigned char type; 422 unsigned int index; /* point to lcd_cpu/pmu_gpio_s or lcd_extern */ 423 unsigned int value; 424 unsigned int delay; 425 }; 426 427 struct lcd_power_ctrl_s { 428 struct lcd_cpu_gpio_s cpu_gpio[LCD_CPU_GPIO_NUM_MAX]; 429 struct lcd_pmu_gpio_s pmu_gpio[LCD_PMU_GPIO_NUM_MAX]; 430 struct lcd_power_step_s power_on_step[LCD_PWR_STEP_MAX]; 431 struct lcd_power_step_s power_off_step[LCD_PWR_STEP_MAX]; 432 int power_on_step_max; /* internal use for debug */ 433 int power_off_step_max; /* internal use for debug */ 434 }; 435 436 struct lcd_boot_ctrl_s { 437 unsigned char lcd_type; //bit[3:0] 438 unsigned char lcd_bits; //bit[7:4] bits:6 or 8 439 unsigned char advanced_flag; //bit[15:8] 440 unsigned char lcd_init_level; //bit[19] 441 unsigned char debug_print_flag; //bit[23:20] 442 unsigned char debug_test_pattern; //bit[27:24] 443 unsigned char debug_para_source;//bit[29:28] 444 //0:normal, 1:dts, 2:unifykey, 3:TBD 445 unsigned char debug_lcd_mode; //bit[31:30] 446 //0:normal, 1:tv, 2:tablet, 3:TBD 447 }; 448 449 #define LCD_ENABLE_RETRY_MAX 3 450 struct lcd_config_s { 451 char *lcd_propname; 452 unsigned int backlight_index; 453 unsigned int extern_index; 454 struct lcd_basic_s lcd_basic; 455 struct lcd_timing_s lcd_timing; 456 struct lcd_optical_info_s optical_info; 457 struct lcd_control_config_s lcd_control; 458 struct lcd_power_ctrl_s *lcd_power; 459 struct lcd_boot_ctrl_s *lcd_boot_ctrl; 460 struct pinctrl *pin; 461 unsigned char pinmux_flag; 462 unsigned char change_flag; 463 unsigned char retry_enable_flag; 464 unsigned char retry_enable_cnt; 465 }; 466 467 struct lcd_duration_s { 468 unsigned int duration_num; 469 unsigned int duration_den; 470 }; 471 472 #define LCD_STATUS_IF_ON (1 << 0) 473 #define LCD_STATUS_ENCL_ON (1 << 1) 474 #define LCD_STATUS_VMODE_ACTIVE (1 << 2) 475 #define LCD_STATUS_ON (LCD_STATUS_IF_ON | LCD_STATUS_ENCL_ON) 476 477 #define LCD_MUTE_UPDATE (1 << 4) 478 #define LCD_TEST_UPDATE (1 << 4) 479 480 #define LCD_VIU_SEL_NONE 0 481 struct aml_lcd_drv_s { 482 char version[20]; 483 struct lcd_data_s *data; 484 unsigned char lcd_mode; 485 unsigned char lcd_status; 486 unsigned char lcd_key_valid; 487 unsigned char lcd_clk_path; /* 0=hpll, 1=gp0_pll */ 488 unsigned char lcd_config_load; 489 unsigned char lcd_resume_type; /* 0=directly, 1=workqueue */ 490 unsigned char lcd_auto_test; 491 unsigned char lcd_test_state; 492 unsigned char lcd_test_flag; 493 unsigned char lcd_mute_state; 494 unsigned char lcd_mute_flag; 495 unsigned char viu_sel; 496 unsigned char vsync_none_timer_flag; 497 498 struct device *dev; 499 struct lcd_config_s *lcd_config; 500 struct vinfo_s *lcd_info; 501 struct class *lcd_debug_class; 502 503 int fr_auto_policy; 504 int fr_mode; 505 struct lcd_duration_s std_duration; 506 507 int tcon_status; 508 509 void (*driver_init_pre)(void); 510 void (*driver_disable_post)(void); 511 int (*driver_init)(void); 512 void (*driver_disable)(void); 513 int (*driver_change)(void); 514 void (*module_reset)(void); 515 void (*module_tiny_reset)(void); 516 void (*lcd_screen_black)(void); 517 void (*lcd_screen_restore)(void); 518 void (*power_ctrl)(int status); 519 520 struct workqueue_struct *workqueue; 521 struct work_struct lcd_probe_work; 522 struct work_struct lcd_resume_work; 523 struct resource *res_vsync_irq; 524 struct resource *res_vsync2_irq; 525 struct resource *res_vx1_irq; 526 struct resource *res_tcon_irq; 527 528 struct mutex power_mutex; 529 }; 530 531 extern struct aml_lcd_drv_s *aml_lcd_get_driver(void); 532 533 534 /* ********************************** 535 * IOCTL define 536 * ********************************** 537 */ 538 #define LCD_IOC_TYPE 'C' 539 #define LCD_IOC_NR_GET_HDR_INFO 0x0 540 #define LCD_IOC_NR_SET_HDR_INFO 0x1 541 542 #define LCD_IOC_CMD_GET_HDR_INFO \ 543 _IOR(LCD_IOC_TYPE, LCD_IOC_NR_GET_HDR_INFO, struct lcd_optical_info_s) 544 #define LCD_IOC_CMD_SET_HDR_INFO \ 545 _IOW(LCD_IOC_TYPE, LCD_IOC_NR_SET_HDR_INFO, struct lcd_optical_info_s) 546 547 #endif 548