1 /* 2 * A V4L2 driver for nvp6324 cameras and AHD Coax protocol. 3 * 4 * Copyright (c) 2017 by Allwinnertech Co., Ltd. http://www.allwinnertech.com 5 * 6 * Authors: Li Huiyu <lihuiyu@allwinnertech.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #ifndef _JAGUAR1_VIDEO_EQ_H_ 14 #define _JAGUAR1_VIDEO_EQ_H_ 15 16 #include "jaguar1_common.h" 17 18 typedef struct _video_equalizer_hsync_stage_s{ 19 unsigned int hsync_stage[6]; 20 } video_equalizer_hsync_stage_s; 21 22 typedef struct _video_equalizer_agc_stage_s{ 23 unsigned int agc_stage[6]; 24 } video_equalizer_agc_stage_s; 25 26 typedef struct _video_equalizer_distance_table_s{ 27 video_equalizer_hsync_stage_s hsync_stage; 28 video_equalizer_agc_stage_s agc_stage; 29 } video_equalizer_distance_table_s; 30 31 32 typedef struct _video_equalizer_base_s{ 33 unsigned char eq_bypass[11]; // B5x01 34 unsigned char eq_band_sel[11]; // B5x58 35 unsigned char eq_gain_sel[11]; // B5x5C 36 37 unsigned char deq_a_on[11]; // BAx3d 38 unsigned char deq_a_sel[11]; // BAx3C 39 40 } video_equalizer_base_s; 41 42 typedef struct _video_equalizer_coeff_s{ 43 44 unsigned char deqA_01[11]; // BankA 0x30 45 unsigned char deqA_02[11]; // BankA 0x31 46 unsigned char deqA_03[11]; // BankA 0x32 47 unsigned char deqA_04[11]; // BankA 0x33 48 unsigned char deqA_05[11]; // BankA 0x34 49 unsigned char deqA_06[11]; // BankA 0x35 50 unsigned char deqA_07[11]; // BankA 0x36 51 unsigned char deqA_08[11]; // BankA 0x37 52 unsigned char deqA_09[11]; // BankA 0x38 53 unsigned char deqA_10[11]; // BankA 0x39 54 unsigned char deqA_11[11]; // BankA 0x3A 55 unsigned char deqA_12[11]; // BankA 0x3B 56 57 } video_equalizer_coeff_s; 58 59 typedef struct _video_equalizer_color_s{ 60 unsigned char contrast[11]; // Bank0 0x10 61 unsigned char y_peaking_mode[11]; // Bank0 0x18 62 unsigned char y_fir_mode[11]; 63 unsigned char c_filter[11]; // Bank0 0x21 64 unsigned char pal_cm_off[11]; // Bank0 0x21 65 unsigned char hue[11]; // Bank0 0x40 66 unsigned char u_gain[11]; // Bank0 0x44 67 unsigned char v_gain[11]; // Bank0 0x48 68 unsigned char u_offset[11]; // Bank0 0x4c 69 unsigned char v_offset[11]; // Bank0 0x50 70 71 unsigned char black_level[11]; // Bank5 0x20 72 unsigned char acc_ref[11]; // Bank5 0x27 73 74 unsigned char cti_delay[11]; // Bank5 0x28 75 unsigned char saturation_b[11]; // Bank5 0x2B 76 unsigned char burst_dec_a[11]; // Bank5 0x24 77 unsigned char burst_dec_b[11]; // Bank5 0x5F 78 unsigned char burst_dec_c[11]; // Bank5 0xD1 79 unsigned char c_option[11]; // Bank5 0xD5 80 81 unsigned char y_filter_b[11]; // BankA 0x25 82 unsigned char y_filter_b_sel[11]; // BankA 0x27 83 84 } video_equalizer_color_s; 85 86 typedef struct _video_equalizer_timing_a_s{ 87 unsigned char h_delay_a[11]; // Bank0 0x58 88 unsigned char h_delay_b[11]; // Bank0 0x89 89 unsigned char h_delay_c[11]; // Bank0 0x8E 90 unsigned char y_delay[11]; // Bank0 0xA0 91 92 } video_equalizer_timing_a_s; 93 94 typedef struct _video_equalizer_clk_s{ 95 unsigned char clk_adc_pre[11]; // Bank1 0x84 96 unsigned char clk_adc_post[11]; // Bank1 0x8C 97 unsigned char clk_adc[11]; // Bank1 0x8C 98 99 } video_equalizer_clk_s; 100 101 typedef struct _video_equalizer_timing_b_s{ 102 unsigned char h_scaler1[11]; // B9x96 + ch*0x20 103 unsigned char h_scaler2[11]; // B9x97 + ch*0x20 104 unsigned char h_scaler3[11]; // B9x98 + ch*0x20 105 unsigned char h_scaler4[11]; // B9x99 + ch*0x20 106 unsigned char h_scaler5[11]; // B9x9a + ch*0x20 107 unsigned char h_scaler6[11]; // B9x9b + ch*0x20 108 unsigned char h_scaler7[11]; // B9x9c + ch*0x20 109 unsigned char h_scaler8[11]; // B9x9d + ch*0x20 110 unsigned char h_scaler9[11]; // B9x9e + ch*0x20 111 112 unsigned char pn_auto[11]; // B9x40 + ch 113 114 unsigned char comb_mode[11]; // B5x90 115 unsigned char h_pll_op_a[11]; // B5xB9 116 unsigned char mem_path[11]; // B5x57 117 unsigned char fsc_lock_speed[11]; //B5x25 118 119 unsigned char ahd_mode[11]; 120 unsigned char sd_mode[11]; 121 unsigned char spl_mode[11]; 122 unsigned char vblk_end[11]; 123 unsigned char afe_g_sel[11]; 124 unsigned char afe_ctr_clp[11]; 125 unsigned char d_agc_option[11]; 126 } video_equalizer_timing_b_s; 127 128 129 typedef struct _video_equalizer_value_table_s{ 130 video_equalizer_base_s eq_base; 131 video_equalizer_coeff_s eq_coeff; 132 video_equalizer_color_s eq_color; 133 134 video_equalizer_timing_a_s eq_timing_a; 135 video_equalizer_clk_s eq_clk; 136 video_equalizer_timing_b_s eq_timing_b; 137 138 } video_equalizer_value_table_s; 139 140 typedef struct _jaguar1_video_eq_value_table_s{ 141 char *name; 142 NC_VIVO_CH_FORMATDEF video_fmt; 143 NC_ANALOG_INPUT analog_input; 144 video_equalizer_base_s eq_base; 145 video_equalizer_coeff_s eq_coeff; 146 video_equalizer_color_s eq_color; 147 148 video_equalizer_timing_a_s eq_timing_a; 149 video_equalizer_clk_s eq_clk; 150 video_equalizer_timing_b_s eq_timing_b; 151 152 } _jaguar1_video_eq_value_table_s; 153 154 typedef struct _video_equalizer_info{ 155 unsigned char Ch; 156 unsigned char devnum; 157 unsigned char stage; 158 unsigned char FmtDef; 159 unsigned char Cable; 160 unsigned char Input; 161 } video_equalizer_info_s; 162 163 void video_input_eq_val_set(video_equalizer_info_s *pvin_eq_set); 164 void video_input_eq_cable_set(video_equalizer_info_s *pvin_eq_set); 165 void video_input_eq_analog_input_set(video_equalizer_info_s *pvin_eq_set); 166 167 #endif /* _JAGUAR1_VIDEO_EQ_H_ */ 168