1 /**
2 * Copyright (c) 2022-2023 HPMicro
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7
8 #ifndef HPM_SYSCTL_DRV_H
9 #define HPM_SYSCTL_DRV_H
10
11 #include "hpm_common.h"
12 #include "hpm_sysctl_regs.h"
13
14 /**
15 *
16 * @brief SYSCTL driver APIs
17 * @defgroup sysctl_interface SYSCTL driver APIs
18 * @ingroup io_interfaces
19 * @{
20 */
21
22 /**
23 * @brief Retention domains
24 */typedef enum {
25 sysctl_retention_domain_sys = 0,
26 sysctl_retention_domain_cpu0 = 2,
27 sysctl_retention_domain_cpu1 = 4,
28 sysctl_retention_domain_xtal24m = 6,
29 sysctl_retention_domain_pll0 = 7,
30 sysctl_retention_domain_pll1 = 8,
31 sysctl_retention_domain_pll2 = 9,
32 } sysctl_retention_domain_t;
33
34 /**
35 * @brief Clock presets
36 */
37 typedef enum {
38 sysctl_preset_0 = 1 << 0,
39 sysctl_preset_1 = 1 << 1,
40 sysctl_preset_2 = 1 << 2,
41 sysctl_preset_3 = 1 << 3,
42 } sysctl_preset_t;
43
44 /**
45 * @brief Reset domains
46 */
47 typedef enum {
48 sysctl_reset_domain_soc = 0,
49 sysctl_reset_domain_cpu0,
50 sysctl_reset_domain_cpu1,
51 } sysctl_reset_domain_t;
52
53 /**
54 * @brief Resource
55 */
56 typedef enum {
57 sysctl_resource_cpu0 = SYSCTL_RESOURCE_CPU0,
58 sysctl_resource_cpx0 = SYSCTL_RESOURCE_CPX0,
59 sysctl_resource_cpu1 = SYSCTL_RESOURCE_CPU1,
60 sysctl_resource_cpx1 = SYSCTL_RESOURCE_CPX1,
61 sysctl_resource_pow_cpu0 = SYSCTL_RESOURCE_POW_CPU0,
62 sysctl_resource_pow_cpu1 = SYSCTL_RESOURCE_POW_CPU1,
63 sysctl_resource_rst_soc = SYSCTL_RESOURCE_RST_SOC,
64 sysctl_resource_rst_cpu0 = SYSCTL_RESOURCE_RST_CPU0,
65 sysctl_resource_rst_cpu1 = SYSCTL_RESOURCE_RST_CPU1,
66 sysctl_resource_xtal = SYSCTL_RESOURCE_CLK_SRC_XTAL,
67 sysctl_resource_pll0 = SYSCTL_RESOURCE_CLK_SRC_PLL0,
68 sysctl_resource_clk0_pll0 = SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL0,
69 sysctl_resource_clk1_pll0 = SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL0,
70 sysctl_resource_clk2_pll0 = SYSCTL_RESOURCE_CLK_SRC_CLK2_PLL0,
71 sysctl_resource_pll1 = SYSCTL_RESOURCE_CLK_SRC_PLL1,
72 sysctl_resource_clk0_pll1 = SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL1,
73 sysctl_resource_clk1_pll1 = SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL1,
74 sysctl_resource_pll2 = SYSCTL_RESOURCE_CLK_SRC_PLL2,
75 sysctl_resource_clk0_pll2 = SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL2,
76 sysctl_resource_clk1_pll2 = SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL2,
77 sysctl_resource_pll0_ref = SYSCTL_RESOURCE_CLK_SRC_PLL0_REF,
78 sysctl_resource_pll1_ref = SYSCTL_RESOURCE_CLK_SRC_PLL1_REF,
79 sysctl_resource_pll2_ref = SYSCTL_RESOURCE_CLK_SRC_PLL2_REF,
80
81 sysctl_resource_clk_top_cpu0 = SYSCTL_RESOURCE_CLK_TOP_CPU0,
82 sysctl_resource_clk_top_mchtmr0 = SYSCTL_RESOURCE_CLK_TOP_MCT0,
83 sysctl_resource_clk_top_mchtmr1 = SYSCTL_RESOURCE_CLK_TOP_MCT1,
84 sysctl_resource_clk_top_xpi0 = SYSCTL_RESOURCE_CLK_TOP_XPI0,
85 sysctl_resource_clk_top_gptmr0 = SYSCTL_RESOURCE_CLK_TOP_TMR0,
86 sysctl_resource_clk_top_gptmr1 = SYSCTL_RESOURCE_CLK_TOP_TMR1,
87 sysctl_resource_clk_top_gptmr2 = SYSCTL_RESOURCE_CLK_TOP_TMR2,
88 sysctl_resource_clk_top_gptmr3 = SYSCTL_RESOURCE_CLK_TOP_TMR3,
89 sysctl_resource_clk_top_uart0 = SYSCTL_RESOURCE_CLK_TOP_URT0,
90 sysctl_resource_clk_top_uart1 = SYSCTL_RESOURCE_CLK_TOP_URT1,
91 sysctl_resource_clk_top_uart2 = SYSCTL_RESOURCE_CLK_TOP_URT2,
92 sysctl_resource_clk_top_uart3 = SYSCTL_RESOURCE_CLK_TOP_URT3,
93 sysctl_resource_clk_top_uart4 = SYSCTL_RESOURCE_CLK_TOP_URT4,
94 sysctl_resource_clk_top_uart5 = SYSCTL_RESOURCE_CLK_TOP_URT5,
95 sysctl_resource_clk_top_uart6 = SYSCTL_RESOURCE_CLK_TOP_URT6,
96 sysctl_resource_clk_top_uart7 = SYSCTL_RESOURCE_CLK_TOP_URT7,
97 sysctl_resource_clk_top_i2c0 = SYSCTL_RESOURCE_CLK_TOP_I2C0,
98 sysctl_resource_clk_top_i2c1 = SYSCTL_RESOURCE_CLK_TOP_I2C1,
99 sysctl_resource_clk_top_i2c2 = SYSCTL_RESOURCE_CLK_TOP_I2C2,
100 sysctl_resource_clk_top_i2c3 = SYSCTL_RESOURCE_CLK_TOP_I2C3,
101 sysctl_resource_clk_top_spi0 = SYSCTL_RESOURCE_CLK_TOP_SPI0,
102 sysctl_resource_clk_top_spi1 = SYSCTL_RESOURCE_CLK_TOP_SPI1,
103 sysctl_resource_clk_top_spi2 = SYSCTL_RESOURCE_CLK_TOP_SPI2,
104 sysctl_resource_clk_top_spi3 = SYSCTL_RESOURCE_CLK_TOP_SPI3,
105 sysctl_resource_clk_top_can0 = SYSCTL_RESOURCE_CLK_TOP_CAN0,
106 sysctl_resource_clk_top_can1 = SYSCTL_RESOURCE_CLK_TOP_CAN1,
107 sysctl_resource_clk_top_can2 = SYSCTL_RESOURCE_CLK_TOP_CAN2,
108 sysctl_resource_clk_top_can3 = SYSCTL_RESOURCE_CLK_TOP_CAN3,
109 sysctl_resource_clk_top_ptpc = SYSCTL_RESOURCE_CLK_TOP_PTPC,
110 sysctl_resource_clk_top_ana0 = SYSCTL_RESOURCE_CLK_TOP_ANA0,
111 sysctl_resource_clk_top_ana1 = SYSCTL_RESOURCE_CLK_TOP_ANA1,
112 sysctl_resource_clk_top_ana2 = SYSCTL_RESOURCE_CLK_TOP_ANA2,
113 sysctl_resource_clk_top_ana3 = SYSCTL_RESOURCE_CLK_TOP_ANA3,
114 sysctl_resource_clk_top_ana4 = SYSCTL_RESOURCE_CLK_TOP_ANA4,
115 sysctl_resource_clk_top_ref0 = SYSCTL_RESOURCE_CLK_TOP_REF0,
116 sysctl_resource_clk_top_ref1 = SYSCTL_RESOURCE_CLK_TOP_REF1,
117 sysctl_resource_clk_top_lin0 = SYSCTL_RESOURCE_CLK_TOP_LIN0,
118 sysctl_resource_clk_top_lin1 = SYSCTL_RESOURCE_CLK_TOP_LIN1,
119 sysctl_resource_clk_top_lin2 = SYSCTL_RESOURCE_CLK_TOP_LIN2,
120 sysctl_resource_clk_top_lin3 = SYSCTL_RESOURCE_CLK_TOP_LIN3,
121 sysctl_resource_clk_top_adc0 = SYSCTL_RESOURCE_CLK_TOP_ADC0,
122 sysctl_resource_clk_top_adc1 = SYSCTL_RESOURCE_CLK_TOP_ADC1,
123 sysctl_resource_clk_top_adc2 = SYSCTL_RESOURCE_CLK_TOP_ADC2,
124 sysctl_resource_clk_top_dac0 = SYSCTL_RESOURCE_CLK_TOP_DAC0,
125 sysctl_resource_clk_top_dac1 = SYSCTL_RESOURCE_CLK_TOP_DAC1,
126
127
128 sysctl_resource_linkable_start = 256,
129 sysctl_resource_ahbp = SYSCTL_RESOURCE_AHBP,
130 sysctl_resource_axis = SYSCTL_RESOURCE_AXIS,
131 sysctl_resource_axic = SYSCTL_RESOURCE_AXIC,
132 sysctl_resource_lmm0 = SYSCTL_RESOURCE_LMM0,
133 sysctl_resource_mchtmr0 = SYSCTL_RESOURCE_MCT0,
134 sysctl_resource_lmm1 = SYSCTL_RESOURCE_LMM1,
135 sysctl_resource_mchtmr1 = SYSCTL_RESOURCE_MCT1,
136 sysctl_resource_rom0 = SYSCTL_RESOURCE_ROM0,
137 sysctl_resource_ram0 = SYSCTL_RESOURCE_RAM0,
138 sysctl_resource_i2c0 = SYSCTL_RESOURCE_I2C0,
139 sysctl_resource_i2c1 = SYSCTL_RESOURCE_I2C1,
140 sysctl_resource_i2c2 = SYSCTL_RESOURCE_I2C2,
141 sysctl_resource_i2c3 = SYSCTL_RESOURCE_I2C3,
142 sysctl_resource_gptmr0 = SYSCTL_RESOURCE_TMR0,
143 sysctl_resource_gptmr1 = SYSCTL_RESOURCE_TMR1,
144 sysctl_resource_gptmr2 = SYSCTL_RESOURCE_TMR2,
145 sysctl_resource_gptmr3 = SYSCTL_RESOURCE_TMR3,
146 sysctl_resource_gpio = SYSCTL_RESOURCE_GPIO,
147 sysctl_resource_adc0 = SYSCTL_RESOURCE_ADC0,
148 sysctl_resource_adc1 = SYSCTL_RESOURCE_ADC1,
149 sysctl_resource_adc2 = SYSCTL_RESOURCE_ADC2,
150 sysctl_resource_dac0 = SYSCTL_RESOURCE_DAC0,
151 sysctl_resource_dac1 = SYSCTL_RESOURCE_DAC1,
152 sysctl_resource_acmp = SYSCTL_RESOURCE_ACMP,
153 sysctl_resource_spi0 = SYSCTL_RESOURCE_SPI0,
154 sysctl_resource_spi1 = SYSCTL_RESOURCE_SPI1,
155 sysctl_resource_spi2 = SYSCTL_RESOURCE_SPI2,
156 sysctl_resource_spi3 = SYSCTL_RESOURCE_SPI3,
157 sysctl_resource_sdm0 = SYSCTL_RESOURCE_SDM0,
158 sysctl_resource_uart0 = SYSCTL_RESOURCE_URT0,
159 sysctl_resource_uart1 = SYSCTL_RESOURCE_URT1,
160 sysctl_resource_uart2 = SYSCTL_RESOURCE_URT2,
161 sysctl_resource_uart3 = SYSCTL_RESOURCE_URT3,
162 sysctl_resource_uart4 = SYSCTL_RESOURCE_URT4,
163 sysctl_resource_uart5 = SYSCTL_RESOURCE_URT5,
164 sysctl_resource_uart6 = SYSCTL_RESOURCE_URT6,
165 sysctl_resource_uart7 = SYSCTL_RESOURCE_URT7,
166 sysctl_resource_lin0 = SYSCTL_RESOURCE_LIN0,
167 sysctl_resource_lin1 = SYSCTL_RESOURCE_LIN1,
168 sysctl_resource_lin2 = SYSCTL_RESOURCE_LIN2,
169 sysctl_resource_lin3 = SYSCTL_RESOURCE_LIN3,
170 sysctl_resource_ptpc = SYSCTL_RESOURCE_PTPC,
171 sysctl_resource_can0 = SYSCTL_RESOURCE_CAN0,
172 sysctl_resource_can1 = SYSCTL_RESOURCE_CAN1,
173 sysctl_resource_can2 = SYSCTL_RESOURCE_CAN2,
174 sysctl_resource_can3 = SYSCTL_RESOURCE_CAN3,
175 sysctl_resource_wdg0 = SYSCTL_RESOURCE_WDG0,
176 sysctl_resource_wdg1 = SYSCTL_RESOURCE_WDG1,
177 sysctl_resource_mbx0 = SYSCTL_RESOURCE_MBX0,
178 sysctl_resource_mbx1 = SYSCTL_RESOURCE_MBX1,
179 sysctl_resource_crc0 = SYSCTL_RESOURCE_CRC0,
180 sysctl_resource_mot0 = SYSCTL_RESOURCE_MOT0,
181 sysctl_resource_mot1 = SYSCTL_RESOURCE_MOT1,
182 sysctl_resource_mot2 = SYSCTL_RESOURCE_MOT2,
183 sysctl_resource_mot3 = SYSCTL_RESOURCE_MOT3,
184 sysctl_resource_msyn = SYSCTL_RESOURCE_MSYN,
185 sysctl_resource_xpi0 = SYSCTL_RESOURCE_XPI0,
186 sysctl_resource_dma0 = SYSCTL_RESOURCE_HDMA,
187 sysctl_resource_dma1 = SYSCTL_RESOURCE_XDMA,
188 sysctl_resource_kman = SYSCTL_RESOURCE_KMAN,
189 sysctl_resource_sdp0 = SYSCTL_RESOURCE_SDP0,
190 sysctl_resource_rng0 = SYSCTL_RESOURCE_RNG0,
191 sysctl_resource_tsns = SYSCTL_RESOURCE_TSNS,
192 sysctl_resource_usb0 = SYSCTL_RESOURCE_USB0,
193 sysctl_resource_ref0 = SYSCTL_RESOURCE_REF0,
194 sysctl_resource_ref1 = SYSCTL_RESOURCE_REF1,
195 sysctl_resource_linkable_end,
196 sysctl_resource_end = sysctl_resource_linkable_end,
197 } sysctl_resource_t;
198
199 /**
200 * @brief Resource modes
201 */
202 typedef enum {
203 sysctl_resource_mode_auto = 0, /*!< Resource clock is automatically managed by system request */
204 sysctl_resource_mode_force_on, /*!< Force the resource clock on */
205 sysctl_resource_mode_force_off, /*!< Force the resource clock off */
206 } sysctl_resource_mode_t;
207
208 /**
209 * @brief Clock nodes
210 */
211 typedef enum {
212 clock_node_mchtmr0 = SYSCTL_CLOCK_CLK_TOP_MCT0,
213 clock_node_mchtmr1 = SYSCTL_CLOCK_CLK_TOP_MCT1,
214 clock_node_xpi0 = SYSCTL_CLOCK_CLK_TOP_XPI0,
215 clock_node_gptmr0 = SYSCTL_CLOCK_CLK_TOP_TMR0,
216 clock_node_gptmr1 = SYSCTL_CLOCK_CLK_TOP_TMR1,
217 clock_node_gptmr2 = SYSCTL_CLOCK_CLK_TOP_TMR2,
218 clock_node_gptmr3 = SYSCTL_CLOCK_CLK_TOP_TMR3,
219 clock_node_uart0 = SYSCTL_CLOCK_CLK_TOP_URT0,
220 clock_node_uart1 = SYSCTL_CLOCK_CLK_TOP_URT1,
221 clock_node_uart2 = SYSCTL_CLOCK_CLK_TOP_URT2,
222 clock_node_uart3 = SYSCTL_CLOCK_CLK_TOP_URT3,
223 clock_node_uart4 = SYSCTL_CLOCK_CLK_TOP_URT4,
224 clock_node_uart5 = SYSCTL_CLOCK_CLK_TOP_URT5,
225 clock_node_uart6 = SYSCTL_CLOCK_CLK_TOP_URT6,
226 clock_node_uart7 = SYSCTL_CLOCK_CLK_TOP_URT7,
227 clock_node_i2c0 = SYSCTL_CLOCK_CLK_TOP_I2C0,
228 clock_node_i2c1 = SYSCTL_CLOCK_CLK_TOP_I2C1,
229 clock_node_i2c2 = SYSCTL_CLOCK_CLK_TOP_I2C2,
230 clock_node_i2c3 = SYSCTL_CLOCK_CLK_TOP_I2C3,
231 clock_node_spi0 = SYSCTL_CLOCK_CLK_TOP_SPI0,
232 clock_node_spi1 = SYSCTL_CLOCK_CLK_TOP_SPI1,
233 clock_node_spi2 = SYSCTL_CLOCK_CLK_TOP_SPI2,
234 clock_node_spi3 = SYSCTL_CLOCK_CLK_TOP_SPI3,
235 clock_node_can0 = SYSCTL_CLOCK_CLK_TOP_CAN0,
236 clock_node_can1 = SYSCTL_CLOCK_CLK_TOP_CAN1,
237 clock_node_can2 = SYSCTL_CLOCK_CLK_TOP_CAN2,
238 clock_node_can3 = SYSCTL_CLOCK_CLK_TOP_CAN3,
239 clock_node_ptpc = SYSCTL_CLOCK_CLK_TOP_PTPC,
240 clock_node_ana0 = SYSCTL_CLOCK_CLK_TOP_ANA0,
241 clock_node_ana1 = SYSCTL_CLOCK_CLK_TOP_ANA1,
242 clock_node_ana2 = SYSCTL_CLOCK_CLK_TOP_ANA2,
243 clock_node_ana3 = SYSCTL_CLOCK_CLK_TOP_ANA3,
244 clock_node_ana4 = SYSCTL_CLOCK_CLK_TOP_ANA4,
245 clock_node_ref0 = SYSCTL_CLOCK_CLK_TOP_REF0,
246 clock_node_ref1 = SYSCTL_CLOCK_CLK_TOP_REF1,
247 clock_node_lin0 = SYSCTL_CLOCK_CLK_TOP_LIN0,
248 clock_node_lin1 = SYSCTL_CLOCK_CLK_TOP_LIN1,
249 clock_node_lin2 = SYSCTL_CLOCK_CLK_TOP_LIN2,
250 clock_node_lin3 = SYSCTL_CLOCK_CLK_TOP_LIN3,
251
252 clock_node_adc_start,
253 clock_node_adc0 = clock_node_adc_start,
254 clock_node_adc1,
255 clock_node_adc2,
256 clock_node_adc3,
257
258 clock_node_dac_start,
259 clock_node_dac0 = clock_node_dac_start,
260 clock_node_dac1,
261 clock_node_end,
262
263 clock_node_core_start = 0xfc,
264 clock_node_cpu0 = clock_node_core_start,
265 clock_node_cpu1 = clock_node_cpu0,
266 clock_node_axi,
267 clock_node_ahb,
268 } clock_node_t;
269
270 /**
271 * @brief General clock sources
272 */
273 typedef enum {
274 clock_source_osc0_clk0 = 0,
275 clock_source_pll0_clk0 = 1,
276 clock_source_pll0_clk1 = 2,
277 clock_source_pll0_clk2 = 3,
278 clock_source_pll1_clk0 = 4,
279 clock_source_pll1_clk1 = 5,
280 clock_source_pll2_clk0 = 6,
281 clock_source_pll2_clk1 = 7,
282 clock_source_general_source_end,
283 } clock_source_t;
284
285 /**
286 * @brief ADC clock sources
287 */
288 typedef enum {
289 clock_source_adc_ana_clock = 0,
290 clock_source_adc_ahb_clock = 1,
291 clock_source_adc_clk_end,
292 } clock_source_adc_t;
293
294 /**
295 * @brief DAC clock sources
296 */
297 typedef enum {
298 clock_source_dac_ana_clock = 0,
299 clock_source_dac_ahb_clock = 1,
300 clock_source_dac_clk_end,
301 } clock_source_dac_t;
302
303 /**
304 * @brief CPU low power mode
305 */
306 typedef enum {
307 cpu_lp_mode_gate_cpu_clock = 0,
308 cpu_lp_mode_trigger_system_lp = 0x1,
309 cpu_lp_mode_ungate_cpu_clock = 0x2,
310 } cpu_lp_mode_t;
311
312 /**
313 * @brief Monitor targets
314 */
315 /* Monitor Target types */
316 typedef enum {
317 monitor_target_clk_32k = 0,
318 monitor_target_clk_irc24m = 1,
319 monitor_target_clk_xtal_24m = 2,
320 monitor_target_clk_usb0_phy = 3,
321 monitor_target_clk_usb1_phy = 4,
322 monitor_target_clk0_osc0 = 8,
323 monitor_target_clk0_pll0 = 9,
324 monitor_target_clk1_pll0 = 10,
325 monitor_target_clk2_pll0 = 11,
326 monitor_target_clk0_pll1 = 12,
327 monitor_target_clk1_pll1 = 13,
328 monitor_target_clk0_pll2 = 14,
329 monitor_target_clk1_pll2 = 15,
330 monitor_target_clk_top_cpu0 = 128,
331 monitor_target_clk_top_mchtmr0 = 129,
332 monitor_target_clk_top_mchtmr1 = 130,
333 monitor_target_clk_top_xpi0 = 131,
334 monitor_target_clk_top_gptmr0 = 132,
335 monitor_target_clk_top_gptmr1 = 133,
336 monitor_target_clk_top_gptmr2 = 134,
337 monitor_target_clk_top_gptmr3 = 135,
338 monitor_target_clk_top_uart0 = 136,
339 monitor_target_clk_top_uart1 = 137,
340 monitor_target_clk_top_uart2 = 138,
341 monitor_target_clk_top_uart3 = 139,
342 monitor_target_clk_top_uart4 = 140,
343 monitor_target_clk_top_uart5 = 141,
344 monitor_target_clk_top_uart6 = 142,
345 monitor_target_clk_top_uart7 = 143,
346 monitor_target_clk_top_i2c0 = 144,
347 monitor_target_clk_top_i2c1 = 145,
348 monitor_target_clk_top_i2c2 = 146,
349 monitor_target_clk_top_i2c3 = 147,
350 monitor_target_clk_top_spi0 = 148,
351 monitor_target_clk_top_spi1 = 149,
352 monitor_target_clk_top_spi2 = 150,
353 monitor_target_clk_top_spi3 = 151,
354 monitor_target_clk_top_can0 = 152,
355 monitor_target_clk_top_can1 = 153,
356 monitor_target_clk_top_can2 = 154,
357 monitor_target_clk_top_can3 = 155,
358 monitor_target_clk_top_ptpc = 156,
359 monitor_target_clk_top_ana0 = 157,
360 monitor_target_clk_top_ana1 = 158,
361 monitor_target_clk_top_ana2 = 159,
362 monitor_target_clk_top_ana3 = 160,
363 monitor_target_clk_top_ana4 = 161,
364 monitor_target_clk_top_ref0 = 162,
365 monitor_target_clk_top_ref1 = 163,
366 monitor_target_clk_top_lin0 = 164,
367 monitor_target_clk_top_lin1 = 165,
368 monitor_target_clk_top_lin2 = 166,
369 monitor_target_clk_top_lin3 = 167,
370 } monitor_target_t;
371
372 /**
373 * @brief Monitor work mode
374 */
375 typedef enum {
376 monitor_work_mode_compare = 0,
377 monitor_work_mode_record = 1,
378 } monitor_work_mode_t;
379
380 /**
381 * @brief Monitor accuracy
382 */
383 typedef enum {
384 monitor_accuracy_1khz = 0,
385 monitor_accuracy_1hz = 1,
386 } monitor_accuracy_t;
387
388 /**
389 * @brief Monitor reference clock source
390 */
391 typedef enum {
392 monitor_reference_32khz = 0,
393 monitor_reference_24mhz = 1,
394 } monitor_reference_t;
395
396 typedef enum {
397 cpu_event_flag_mask_reset = SYSCTL_CPU_LP_RESET_FLAG_MASK,
398 cpu_event_flag_mask_sleep = SYSCTL_CPU_LP_SLEEP_FLAG_MASK,
399 cpu_event_flag_mask_wake = SYSCTL_CPU_LP_WAKE_FLAG_MASK,
400 cpu_event_flag_mask_all = SYSCTL_CPU_LP_RESET_FLAG_MASK | SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK,
401 } cpu_event_flag_mask_t;
402
403 /**
404 * @brief Monitor config
405 */
406 typedef struct monitor_config {
407 uint8_t divide_by; /**< Divider to be used for OBS output to pads */
408 monitor_work_mode_t mode; /**< Monitor work mode */
409 monitor_accuracy_t accuracy; /**< Monitor reference accuracy */
410 monitor_reference_t reference; /**< Monitor reference clock source */
411 monitor_target_t target; /**< Monitor target */
412 bool start_measure; /**< Start flag */
413 bool enable_output; /**< Enable output to pads if true */
414 uint32_t high_limit; /**< Maximum frequency at compare mode */
415 uint32_t low_limit; /**< Minimum frequency at compare mode */
416 } monitor_config_t;
417
418 #ifdef __cplusplus
419 extern "C" {
420 #endif
421
422 /**
423 * @brief Check if monitor result is valid
424 *
425 * @param[in] ptr SYSCTL_Type base address
426 * @param[in] monitor_index specific monitor instance to be used
427 *
428 * @return true if it is valid
429 */
sysctl_monitor_result_is_valid(SYSCTL_Type * ptr,uint8_t monitor_index)430 static inline bool sysctl_monitor_result_is_valid(SYSCTL_Type *ptr, uint8_t monitor_index)
431 {
432 return SYSCTL_MONITOR_CONTROL_VALID_GET(ptr->MONITOR[monitor_index].CONTROL);
433 }
434
435 /**
436 * @brief Get target monitor instance result
437 *
438 * @param[in] ptr SYSCTL_Type base address
439 * @param[in] monitor_index specific monitor instance to be used
440 * @return value of monitor result measured
441 */
sysctl_monitor_get_current_result(SYSCTL_Type * ptr,uint8_t monitor_index)442 static inline uint32_t sysctl_monitor_get_current_result(SYSCTL_Type *ptr, uint8_t monitor_index)
443 {
444 while (!sysctl_monitor_result_is_valid(ptr, monitor_index)) {
445 }
446 return ptr->MONITOR[monitor_index].CURRENT;
447 }
448
449 /**
450 * @brief Set work mode for target monitor instance
451 *
452 * @param[in] ptr SYSCTL_Type base address
453 * @param[in] monitor_index specific monitor instance to be used
454 * @param[in] mode monitor_work_mode_compare, monitor_work_mode_record
455 */
sysctl_monitor_set_work_mode(SYSCTL_Type * ptr,uint8_t monitor_index,monitor_work_mode_t mode)456 static inline void sysctl_monitor_set_work_mode(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_work_mode_t mode)
457 {
458 ptr->MONITOR[monitor_index].CONTROL = (ptr->MONITOR[monitor_index].CONTROL & ~SYSCTL_MONITOR_CONTROL_MODE_MASK) |
459 (SYSCTL_MONITOR_CONTROL_MODE_SET(mode));
460 }
461
462 /**
463 * @brief Set minimum frequency for target monitor instance
464 *
465 * @param[in] ptr SYSCTL_Type base address
466 * @param[in] monitor_index specific monitor instance to be used
467 * @param[in] limit measurement low limit
468 */
sysctl_monitor_set_limit_low(SYSCTL_Type * ptr,uint8_t monitor_index,uint32_t limit)469 static inline hpm_stat_t sysctl_monitor_set_limit_low(SYSCTL_Type *ptr, uint8_t monitor_index, uint32_t limit)
470 {
471 if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) {
472 return status_invalid_argument;
473 }
474 ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(limit);
475 return status_success;
476 }
477
478 /**
479 * @brief Set maximum frequency for target monitor instance
480 *
481 * @param[in] ptr SYSCTL_Type base address
482 * @param[in] monitor_index specific monitor instance to be used
483 * @param[in] limit measurement high limit
484 */
sysctl_monitor_set_limit_high(SYSCTL_Type * ptr,uint8_t monitor_index,uint32_t limit)485 static inline hpm_stat_t sysctl_monitor_set_limit_high(SYSCTL_Type *ptr, uint8_t monitor_index, uint32_t limit)
486 {
487 if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) {
488 return status_invalid_argument;
489 }
490 ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(limit);
491 return status_success;
492 }
493
494 /**
495 * @brief Set frequency limit for target monitor instance
496 *
497 * @param[in] ptr SYSCTL_Type base address
498 * @param[in] monitor_index specific monitor instance to be used
499 * @param[in] limit_high measurement high limit
500 * @param[in] limit_low measurement low limit
501 */
sysctl_monitor_set_limit(SYSCTL_Type * ptr,uint8_t monitor_index,uint32_t limit_high,uint32_t limit_low)502 static inline hpm_stat_t sysctl_monitor_set_limit(SYSCTL_Type *ptr,
503 uint8_t monitor_index,
504 uint32_t limit_high,
505 uint32_t limit_low)
506 {
507 if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) {
508 return status_invalid_argument;
509 }
510 ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(limit_high);
511 ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(limit_low);
512 return status_success;
513 }
514
515 /**
516 * @brief Get maximum frequency for target monitor instance
517 *
518 * @param[in] ptr SYSCTL_Type base address
519 * @param[in] monitor_index specific monitor instance to be used
520 * @return current high limit value
521 */
sysctl_monitor_get_limit_high(SYSCTL_Type * ptr,uint32_t monitor_index)522 static inline uint32_t sysctl_monitor_get_limit_high(SYSCTL_Type *ptr, uint32_t monitor_index)
523 {
524 return SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(ptr->MONITOR[monitor_index].HIGH_LIMIT);
525 }
526
527 /**
528 * @brief Get minimum frequency for target monitor instance
529 *
530 * @param[in] ptr SYSCTL_Type base address
531 * @param[in] monitor_index specific monitor instance to be used
532 * @return current low limit value
533 */
sysctl_monitor_get_limit_low(SYSCTL_Type * ptr,uint32_t monitor_index)534 static inline uint32_t sysctl_monitor_get_limit_low(SYSCTL_Type *ptr, uint32_t monitor_index)
535 {
536 return SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(ptr->MONITOR[monitor_index].LOW_LIMIT);
537 }
538
539 /**
540 * @brief Measure specific target frequency
541 *
542 * @param[in] ptr SYSCTL_Type base address
543 * @param[in] monitor_index specific monitor instance to be used
544 * @param[in] target monitor target to be measured
545 * @param[in] enable_output enable clock obs output
546 * @return frequency of monitor target measured
547 */
548 uint32_t sysctl_monitor_measure_frequency(SYSCTL_Type *ptr,
549 uint8_t monitor_index,
550 monitor_target_t target,
551 bool enable_output);
552
553 /**
554 * @brief Link current CPU core its own group
555 *
556 * Once it is linked, peripherals state in that group will keep on as long as this core is not in low power mode
557 *
558 * @param[in] ptr SYSCTL_Type base address
559 * @param[in] cpu_index cpu index to enable its own affiliated group
560 */
sysctl_set_enable_cpu_affiliate(SYSCTL_Type * ptr,uint8_t cpu_index)561 static inline void sysctl_set_enable_cpu_affiliate(SYSCTL_Type *ptr, uint8_t cpu_index)
562 {
563 ptr->AFFILIATE[cpu_index].SET = 1 << cpu_index;
564 }
565
566 /**
567 * @brief Unlink current CPU core with its own group
568 *
569 * @param[in] ptr SYSCTL_Type base address
570 * @param[in] cpu_index cpu index to enable its own affiliated group
571 */
sysctl_set_disable_cpu_affiliate(SYSCTL_Type * ptr,uint8_t cpu_index)572 static inline void sysctl_set_disable_cpu_affiliate(SYSCTL_Type *ptr, uint8_t cpu_index)
573 {
574 ptr->AFFILIATE[cpu_index].CLEAR = 1 << cpu_index;
575 }
576
577 /**
578 * @brief Check if any resource is busy
579 *
580 * @param[in] ptr SYSCTL_Type base address
581 * @return true if any resource is busy
582 */
sysctl_resource_any_is_busy(SYSCTL_Type * ptr)583 static inline bool sysctl_resource_any_is_busy(SYSCTL_Type *ptr)
584 {
585 return ptr->RESOURCE[0] & SYSCTL_RESOURCE_GLB_BUSY_MASK;
586 }
587
588 /**
589 * @brief Check if specific target is busy
590 *
591 * @param[in] ptr SYSCTL_Type base address
592 * @param[in] resource target resource index
593 * @return true if target resource is busy
594 */
sysctl_resource_target_is_busy(SYSCTL_Type * ptr,sysctl_resource_t resource)595 static inline bool sysctl_resource_target_is_busy(SYSCTL_Type *ptr, sysctl_resource_t resource)
596 {
597 return ptr->RESOURCE[resource] & SYSCTL_RESOURCE_LOC_BUSY_MASK;
598 }
599
600 /**
601 * @brief Set target mode
602 *
603 * @param[in] ptr SYSCTL_Type base address
604 * @param[in] resource target resource index
605 * @param[in] mode target resource mode
606 */
sysctl_resource_target_set_mode(SYSCTL_Type * ptr,sysctl_resource_t resource,sysctl_resource_mode_t mode)607 static inline void sysctl_resource_target_set_mode(SYSCTL_Type *ptr,
608 sysctl_resource_t resource,
609 sysctl_resource_mode_t mode)
610 {
611 ptr->RESOURCE[resource] =
612 (ptr->RESOURCE[resource] & ~SYSCTL_RESOURCE_MODE_MASK) |
613 SYSCTL_RESOURCE_MODE_SET(mode);
614 }
615
616 /**
617 * @brief Get target mode
618 *
619 * @param[in] ptr SYSCTL_Type base address
620 * @param[in] resource target resource index
621 * @return target resource mode
622 */
sysctl_resource_target_get_mode(SYSCTL_Type * ptr,sysctl_resource_t resource)623 static inline uint8_t sysctl_resource_target_get_mode(SYSCTL_Type *ptr,
624 sysctl_resource_t resource)
625 {
626 return SYSCTL_RESOURCE_MODE_GET(ptr->RESOURCE[resource]);
627 }
628
629 /**
630 * @brief Disable resource retention when specific CPU enters stop mode
631 *
632 * @param[in] ptr SYSCTL_Type base address
633 * @param[in] cpu_index cpu index
634 * @param[in] mask bit mask to clear
635 */
sysctl_clear_cpu_lp_retention_with_mask(SYSCTL_Type * ptr,uint8_t cpu_index,uint32_t mask)636 static inline void sysctl_clear_cpu_lp_retention_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t mask)
637 {
638 ptr->RETENTION[cpu_index].CLEAR = mask;
639 }
640
641 /**
642 * @brief Disable resource retention when CPU0 enters stop mode
643 *
644 * @param[in] ptr SYSCTL_Type base address
645 * @param[in] mask bit mask to clear
646 */
sysctl_clear_cpu0_lp_retention_with_mask(SYSCTL_Type * ptr,uint32_t mask)647 static inline void sysctl_clear_cpu0_lp_retention_with_mask(SYSCTL_Type *ptr, uint32_t mask)
648 {
649 sysctl_clear_cpu_lp_retention_with_mask(ptr, 0, mask);
650 }
651
652 /**
653 * @brief Disable resource retention when CPU1 enters stop mode
654 *
655 * @param[in] ptr SYSCTL_Type base address
656 * @param[in] mask bit mask to clear
657 */
sysctl_clear_cpu1_lp_retention_with_mask(SYSCTL_Type * ptr,uint32_t mask)658 static inline void sysctl_clear_cpu1_lp_retention_with_mask(SYSCTL_Type *ptr, uint32_t mask)
659 {
660 sysctl_clear_cpu_lp_retention_with_mask(ptr, 1, mask);
661 }
662
663 /**
664 * @brief Enable resource retention when specific CPU enters stop mode
665 *
666 * @param[in] ptr SYSCTL_Type base address
667 * @param[in] cpu_index cpu index
668 * @param[in] mask bit mask to set
669 */
sysctl_set_cpu_lp_retention_with_mask(SYSCTL_Type * ptr,uint8_t cpu_index,uint32_t mask)670 static inline void sysctl_set_cpu_lp_retention_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t mask)
671 {
672 ptr->RETENTION[cpu_index].SET = mask;
673 }
674
675 /**
676 * @brief Enable resource retention when CPU0 enters stop mode
677 *
678 * @param[in] ptr SYSCTL_Type base address
679 * @param[in] mask bit mask to set
680 */
sysctl_set_cpu0_lp_retention_with_mask(SYSCTL_Type * ptr,uint32_t mask)681 static inline void sysctl_set_cpu0_lp_retention_with_mask(SYSCTL_Type *ptr, uint32_t mask)
682 {
683 sysctl_set_cpu_lp_retention_with_mask(ptr, 0, mask);
684 }
685
686 /**
687 * @brief Enable resource retention when CPU1 enters stop mode
688 *
689 * @param[in] ptr SYSCTL_Type base address
690 * @param[in] mask bit mask to set
691 */
sysctl_set_cpu1_lp_retention_with_mask(SYSCTL_Type * ptr,uint32_t mask)692 static inline void sysctl_set_cpu1_lp_retention_with_mask(SYSCTL_Type *ptr, uint32_t mask)
693 {
694 sysctl_set_cpu_lp_retention_with_mask(ptr, 1, mask);
695 }
696
697 /**
698 * @brief Enable resource retention when specific CPU enters stop mode
699 *
700 * @param[in] ptr SYSCTL_Type base address
701 * @param[in] cpu_index cpu index
702 * @param[in] value value to be set
703 */
sysctl_set_cpu_lp_retention(SYSCTL_Type * ptr,uint8_t cpu_index,uint32_t value)704 static inline void sysctl_set_cpu_lp_retention(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t value)
705 {
706 ptr->RETENTION[cpu_index].VALUE = value;
707 }
708
709 /**
710 * @brief Enable resource retention when CPU0 enters stop mode
711 *
712 * @param[in] ptr SYSCTL_Type base address
713 * @param[in] value value to be set
714 */
sysctl_set_cpu0_lp_retention(SYSCTL_Type * ptr,uint32_t value)715 static inline void sysctl_set_cpu0_lp_retention(SYSCTL_Type *ptr, uint32_t value)
716 {
717 sysctl_set_cpu_lp_retention(ptr, 0, value);
718 }
719
720 /**
721 * @brief Enable resource retention when CPU1 enters stop mode
722 *
723 * @param[in] ptr SYSCTL_Type base address
724 * @param[in] value value to be set
725 */
sysctl_set_cpu1_lp_retention(SYSCTL_Type * ptr,uint32_t value)726 static inline void sysctl_set_cpu1_lp_retention(SYSCTL_Type *ptr, uint32_t value)
727 {
728 sysctl_set_cpu_lp_retention(ptr, 1, value);
729 }
730
731 /**
732 * @brief Retain target domain for specific CPU
733 *
734 * @param[in] ptr SYSCTL_Type base address
735 * @param[in] cpu_index CPU index
736 * @param[in] domain target domain power to be retained
737 * @param[in] retain_mem set true to retain memory/register of target domain
738 */
sysctl_set_cpu_lp_retain_domain(SYSCTL_Type * ptr,uint8_t cpu_index,sysctl_retention_domain_t domain,bool retain_mem)739 static inline void sysctl_set_cpu_lp_retain_domain(SYSCTL_Type *ptr,
740 uint8_t cpu_index,
741 sysctl_retention_domain_t domain,
742 bool retain_mem)
743 {
744 uint8_t set_mask = 0x1;
745 if (domain < sysctl_retention_domain_xtal24m) {
746 set_mask = retain_mem ? 0x3 : 0x1;
747 }
748 ptr->RETENTION[cpu_index].SET = (set_mask << domain);
749 }
750
751 /**
752 * @brief Retain target domain for specific CPU0
753 *
754 * @param[in] ptr SYSCTL_Type base address
755 * @param[in] domain target domain power to be retained
756 * @param[in] retain_mem set true to retain memory/register of target domain
757 */
sysctl_set_cpu0_lp_retain_domain(SYSCTL_Type * ptr,sysctl_retention_domain_t domain,bool retain_mem)758 static inline void sysctl_set_cpu0_lp_retain_domain(SYSCTL_Type *ptr,
759 sysctl_retention_domain_t domain,
760 bool retain_mem)
761 {
762 sysctl_set_cpu_lp_retain_domain(ptr, 0, domain, retain_mem);
763 }
764
765 /**
766 * @brief Retain target domain for specific CPU
767 *
768 * @param[in] ptr SYSCTL_Type base address
769 * @param[in] domain target domain power to be retained
770 * @param[in] retain_mem set true to retain memory/register of target domain
771 */
sysctl_set_cpu1_lp_retain_domain(SYSCTL_Type * ptr,sysctl_retention_domain_t domain,bool retain_mem)772 static inline void sysctl_set_cpu1_lp_retain_domain(SYSCTL_Type *ptr,
773 sysctl_retention_domain_t domain,
774 bool retain_mem)
775 {
776 sysctl_set_cpu_lp_retain_domain(ptr, 1, domain, retain_mem);
777 }
778
779 /**
780 * @brief Check if cpu clock is busy
781 *
782 * @param[in] ptr SYSCTL_Type base address
783 * @return true if any clock is busy
784 */
sysctl_cpu_clock_any_is_busy(SYSCTL_Type * ptr)785 static inline bool sysctl_cpu_clock_any_is_busy(SYSCTL_Type *ptr)
786 {
787 return ptr->CLOCK_CPU[0] & SYSCTL_CLOCK_CPU_GLB_BUSY_MASK;
788 }
789
790 /**
791 * @brief Check if any clock is busy
792 *
793 * @param[in] ptr SYSCTL_Type base address
794 * @return true if any clock is busy
795 */
sysctl_clock_any_is_busy(SYSCTL_Type * ptr)796 static inline bool sysctl_clock_any_is_busy(SYSCTL_Type *ptr)
797 {
798 return ptr->CLOCK[0] & SYSCTL_CLOCK_GLB_BUSY_MASK;
799 }
800
801 /**
802 * @brief Check if target clock is busy
803 *
804 * @param[in] ptr SYSCTL_Type base address
805 * @param[in] clock target clock
806 * @return true if target clock is busy
807 */
sysctl_clock_target_is_busy(SYSCTL_Type * ptr,uint32_t clock)808 static inline bool sysctl_clock_target_is_busy(SYSCTL_Type *ptr, uint32_t clock)
809 {
810 return ptr->CLOCK[clock] & SYSCTL_CLOCK_LOC_BUSY_MASK;
811 }
812
813 /**
814 * @brief Set clock preset
815 *
816 * @param[in] ptr SYSCTL_Type base address
817 * @param[in] preset preset
818 */
sysctl_clock_set_preset(SYSCTL_Type * ptr,sysctl_preset_t preset)819 static inline void sysctl_clock_set_preset(SYSCTL_Type *ptr, sysctl_preset_t preset)
820 {
821 ptr->GLOBAL00 = (ptr->GLOBAL00 & ~SYSCTL_GLOBAL00_MUX_MASK) | SYSCTL_GLOBAL00_MUX_SET(preset);
822 }
823
824 /**
825 * @brief Check if target reset domain wakeup status
826 *
827 * @param[in] ptr SYSCTL_Type base address
828 * @param[in] domain target domain to be checked
829 * @return true if target domain was taken wakeup reset
830 */
sysctl_reset_check_target_domain_wakeup_flag(SYSCTL_Type * ptr,sysctl_reset_domain_t domain)831 static inline bool sysctl_reset_check_target_domain_wakeup_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain)
832 {
833 return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK;
834 }
835
836 /**
837 * @brief Clear target reset domain wakeup status
838 *
839 * @param[in] ptr SYSCTL_Type base address
840 * @param[in] domain target domain to be checked
841 */
sysctl_reset_clear_target_domain_wakeup_flag(SYSCTL_Type * ptr,sysctl_reset_domain_t domain)842 static inline void sysctl_reset_clear_target_domain_wakeup_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain)
843 {
844 ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK;
845 }
846
847 /**
848 * @brief Clear target reset domain reset status
849 *
850 * @param[in] ptr SYSCTL_Type base address
851 * @param[in] domain target domain to be checked
852 * @return true if target domain was taken reset
853 */
sysctl_reset_check_target_domain_flag(SYSCTL_Type * ptr,sysctl_reset_domain_t domain)854 static inline bool sysctl_reset_check_target_domain_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain)
855 {
856 return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_MASK;
857 }
858
859 /**
860 * @brief Clear target reset domain reset status
861 *
862 * @param[in] ptr SYSCTL_Type base address
863 * @param[in] domain target domain to be checked
864 */
sysctl_reset_clear_target_domain_flag(SYSCTL_Type * ptr,sysctl_reset_domain_t domain)865 static inline void sysctl_reset_clear_target_domain_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain)
866 {
867 ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK;
868 }
869
870 /**
871 * @brief Clear target reset domain for all reset status
872 *
873 * @param[in] ptr SYSCTL_Type base address
874 * @param[in] domain target domain to be checked
875 */
sysctl_reset_clear_target_domain_all_flags(SYSCTL_Type * ptr,sysctl_reset_domain_t domain)876 static inline void sysctl_reset_clear_target_domain_all_flags(SYSCTL_Type *ptr, sysctl_reset_domain_t domain)
877 {
878 ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK | SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK;
879 }
880
881 /**
882 * @brief Get target CPU wakeup source status
883 *
884 * @param[in] ptr SYSCTL_Type base address
885 * @param[in] cpu_index CPU index
886 * @param[in] status_index wakeup status index 0 - 7
887 * @return wakeup source status mask
888 */
sysctl_get_wakeup_source_status(SYSCTL_Type * ptr,uint8_t cpu_index,uint8_t status_index)889 static inline uint32_t sysctl_get_wakeup_source_status(SYSCTL_Type *ptr, uint8_t cpu_index, uint8_t status_index)
890 {
891 return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index];
892 }
893
894 /**
895 * @brief Get target CPU0 wakeup source status
896 *
897 * @param[in] ptr SYSCTL_Type base address
898 * @param[in] status_index wakeup status index 0 - 7
899 * @return wakeup source status mask
900 */
sysctl_get_cpu0_wakeup_source_status(SYSCTL_Type * ptr,uint8_t status_index)901 static inline uint32_t sysctl_get_cpu0_wakeup_source_status(SYSCTL_Type *ptr, uint8_t status_index)
902 {
903 return sysctl_get_wakeup_source_status(ptr, 0, status_index);
904 }
905
906 /**
907 * @brief Get target CPU1 wakeup source status
908 *
909 * @param[in] ptr SYSCTL_Type base address
910 * @param[in] status_index wakeup status index 0 - 7
911 * @return wakeup source status mask
912 */
sysctl_get_cpu1_wakeup_source_status(SYSCTL_Type * ptr,uint8_t status_index)913 static inline uint32_t sysctl_get_cpu1_wakeup_source_status(SYSCTL_Type *ptr, uint8_t status_index)
914 {
915 return sysctl_get_wakeup_source_status(ptr, 1, status_index);
916 }
917
918 /**
919 * @brief Check wakeup source status with mask
920 *
921 * @param[in] ptr SYSCTL_Type base address
922 * @param[in] cpu_index CPU index
923 * @param[in] status_index wakeup status index 0 - 7
924 * @param[in] mask expected status mask
925 * @return wakeup status according to given bit mask
926 */
sysctl_check_wakeup_source_status_with_mask(SYSCTL_Type * ptr,uint8_t cpu_index,uint8_t status_index,uint32_t mask)927 static inline uint32_t sysctl_check_wakeup_source_status_with_mask(SYSCTL_Type *ptr,
928 uint8_t cpu_index,
929 uint8_t status_index,
930 uint32_t mask)
931 {
932 return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index] & mask;
933 }
934
935 /**
936 * @brief Check CPU0 wakeup source status with mask
937 *
938 * @param[in] ptr SYSCTL_Type base address
939 * @param[in] status_index wakeup status index 0 - 7
940 * @param[in] mask expected status mask
941 * @return wakeup status according to given bit mask
942 */
sysctl_check_cpu0_wakeup_source_status_with_mask(SYSCTL_Type * ptr,uint8_t status_index,uint32_t mask)943 static inline uint32_t sysctl_check_cpu0_wakeup_source_status_with_mask(SYSCTL_Type *ptr,
944 uint8_t status_index,
945 uint32_t mask)
946 {
947 return sysctl_check_wakeup_source_status_with_mask(ptr, 0, status_index, mask);
948 }
949
950 /**
951 * @brief Check CPU1 wakeup source status with mask
952 *
953 * @param[in] ptr SYSCTL_Type base address
954 * @param[in] status_index wakeup status index 0 - 7
955 * @param[in] mask expected status mask
956 * @return wakeup status according to given bit mask
957 */
sysctl_check_cpu1_wakeup_source_status_with_mask(SYSCTL_Type * ptr,uint8_t status_index,uint32_t mask)958 static inline uint32_t sysctl_check_cpu1_wakeup_source_status_with_mask(SYSCTL_Type *ptr,
959 uint8_t status_index,
960 uint32_t mask)
961 {
962 return sysctl_check_wakeup_source_status_with_mask(ptr, 1, status_index, mask);
963 }
964
965 /**
966 * @brief Enable wakeup source status with mask
967 *
968 * @param[in] ptr SYSCTL_Type base address
969 * @param[in] cpu_index CPU index
970 * @param[in] enable_index wakeup enable index 0 - 7
971 * @param[in] mask expected status mask
972 */
sysctl_enable_wakeup_source_with_mask(SYSCTL_Type * ptr,uint8_t cpu_index,uint8_t enable_index,uint32_t mask)973 static inline void sysctl_enable_wakeup_source_with_mask(SYSCTL_Type *ptr,
974 uint8_t cpu_index,
975 uint8_t enable_index,
976 uint32_t mask)
977 {
978 ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] |= mask;
979 }
980
981 /**
982 * @brief Enable CPU0 wakeup source status with mask
983 *
984 * @param[in] ptr SYSCTL_Type base address
985 * @param[in] enable_index wakeup enable index 0 - 7
986 * @param[in] mask expected status mask
987 */
sysctl_enable_cpu0_wakeup_source_with_mask(SYSCTL_Type * ptr,uint8_t enable_index,uint32_t mask)988 static inline void sysctl_enable_cpu0_wakeup_source_with_mask(SYSCTL_Type *ptr,
989 uint8_t enable_index,
990 uint32_t mask)
991 {
992 ptr->CPU[0].WAKEUP_ENABLE[enable_index] |= mask;
993 }
994
995 /**
996 * @brief Enable CPU1 wakeup source status with mask
997 *
998 * @param[in] ptr SYSCTL_Type base address
999 * @param[in] enable_index wakeup enable index 0 - 7
1000 * @param[in] mask expected status mask
1001 */
sysctl_enable_cpu1_wakeup_source_with_mask(SYSCTL_Type * ptr,uint8_t enable_index,uint32_t mask)1002 static inline void sysctl_enable_cpu1_wakeup_source_with_mask(SYSCTL_Type *ptr,
1003 uint8_t enable_index,
1004 uint32_t mask)
1005 {
1006 ptr->CPU[1].WAKEUP_ENABLE[enable_index] |= mask;
1007 }
1008
1009 /**
1010 * @brief Disable wakeup source status with mask
1011 *
1012 * @param[in] ptr SYSCTL_Type base address
1013 * @param[in] cpu_index CPU index
1014 * @param[in] enable_index wakeup enable index 0 - 7
1015 * @param[in] mask expected status mask
1016 */
sysctl_disable_wakeup_source_with_mask(SYSCTL_Type * ptr,uint8_t cpu_index,uint8_t enable_index,uint32_t mask)1017 static inline void sysctl_disable_wakeup_source_with_mask(SYSCTL_Type *ptr,
1018 uint8_t cpu_index,
1019 uint8_t enable_index,
1020 uint32_t mask)
1021 {
1022 ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] &= ~mask;
1023 }
1024
1025 /**
1026 * @brief Disable CPU0 wakeup source status with mask
1027 *
1028 * @param[in] ptr SYSCTL_Type base address
1029 * @param[in] enable_index wakeup enable index 0 - 7
1030 * @param[in] mask expected status mask
1031 */
sysctl_disable_cpu0_wakeup_source_with_mask(SYSCTL_Type * ptr,uint8_t enable_index,uint32_t mask)1032 static inline void sysctl_disable_cpu0_wakeup_source_with_mask(SYSCTL_Type *ptr,
1033 uint8_t enable_index,
1034 uint32_t mask)
1035 {
1036 sysctl_disable_wakeup_source_with_mask(ptr, 0, enable_index, mask);
1037 }
1038
1039
1040 /**
1041 * @brief Disable CPU1 wakeup source status with mask
1042 *
1043 * @param[in] ptr SYSCTL_Type base address
1044 * @param[in] enable_index wakeup enable index 0 - 7
1045 * @param[in] mask expected status mask
1046 */
sysctl_disable_cpu1_wakeup_source_with_mask(SYSCTL_Type * ptr,uint8_t enable_index,uint32_t mask)1047 static inline void sysctl_disable_cpu1_wakeup_source_with_mask(SYSCTL_Type *ptr,
1048 uint8_t enable_index,
1049 uint32_t mask)
1050 {
1051 sysctl_disable_wakeup_source_with_mask(ptr, 1, enable_index, mask);
1052 }
1053
1054 /**
1055 * @brief Disable wakeup source status with irq
1056 *
1057 * @param[in] ptr SYSCTL_Type base address
1058 * @param[in] cpu_index CPU index
1059 * @param[in] irq_num irq number to be disabled as wakeup source
1060 */
sysctl_disable_wakeup_source_with_irq(SYSCTL_Type * ptr,uint8_t cpu_index,uint16_t irq_num)1061 static inline void sysctl_disable_wakeup_source_with_irq(SYSCTL_Type *ptr,
1062 uint8_t cpu_index,
1063 uint16_t irq_num)
1064 {
1065 ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num >> 2] &= ~(1UL << (irq_num % 32));
1066 }
1067
1068 /**
1069 * @brief Disable CPU0 wakeup source status with irq
1070 *
1071 * @param[in] ptr SYSCTL_Type base address
1072 * @param[in] irq_num irq number to be disabled as wakeup source
1073 */
sysctl_disable_cpu0_wakeup_source_with_irq(SYSCTL_Type * ptr,uint16_t irq_num)1074 static inline void sysctl_disable_cpu0_wakeup_source_with_irq(SYSCTL_Type *ptr, uint16_t irq_num)
1075 {
1076 sysctl_disable_wakeup_source_with_irq(ptr, 0, irq_num);
1077 }
1078
1079
1080 /**
1081 * @brief Disable CPU1 wakeup source status with irq
1082 *
1083 * @param[in] ptr SYSCTL_Type base address
1084 * @param[in] irq_num irq number to be disabled as wakeup source
1085 */
sysctl_disable_cpu1_wakeup_source_with_irq(SYSCTL_Type * ptr,uint16_t irq_num)1086 static inline void sysctl_disable_cpu1_wakeup_source_with_irq(SYSCTL_Type *ptr, uint16_t irq_num)
1087 {
1088 sysctl_disable_wakeup_source_with_irq(ptr, 1, irq_num);
1089 }
1090
1091 /**
1092 * @brief Enable wakeup source status with irq
1093 *
1094 * @param[in] ptr SYSCTL_Type base address
1095 * @param[in] cpu_index CPU index
1096 * @param[in] irq_num irq number to be set as wakeup source
1097 */
sysctl_enable_wakeup_source_with_irq(SYSCTL_Type * ptr,uint8_t cpu_index,uint16_t irq_num)1098 static inline void sysctl_enable_wakeup_source_with_irq(SYSCTL_Type *ptr, uint8_t cpu_index, uint16_t irq_num)
1099 {
1100 ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num / 32] |= 1UL << (irq_num & 0x1F);
1101 }
1102
1103 /**
1104 * @brief Enable CPU0 wakeup source status with irq
1105 *
1106 * @param[in] ptr SYSCTL_Type base address
1107 * @param[in] irq_num irq number to be set as wakeup source
1108 */
sysctl_enable_cpu0_wakeup_source_with_irq(SYSCTL_Type * ptr,uint16_t irq_num)1109 static inline void sysctl_enable_cpu0_wakeup_source_with_irq(SYSCTL_Type *ptr, uint16_t irq_num)
1110 {
1111 sysctl_enable_wakeup_source_with_irq(ptr, 0, irq_num);
1112 }
1113
1114 /**
1115 * @brief Enable CPU1 wakeup source status with irq
1116 *
1117 * @param[in] ptr SYSCTL_Type base address
1118 * @param[in] irq_num irq number to be set as wakeup source
1119 */
sysctl_enable_cpu1_wakeup_source_with_irq(SYSCTL_Type * ptr,uint16_t irq_num)1120 static inline void sysctl_enable_cpu1_wakeup_source_with_irq(SYSCTL_Type *ptr, uint16_t irq_num)
1121 {
1122 sysctl_enable_wakeup_source_with_irq(ptr, 1, irq_num);
1123 }
1124
1125 /**
1126 * @brief Lock CPU gpr with mask
1127 *
1128 * @param[in] ptr SYSCTL_Type base address
1129 * @param[in] cpu_index CPU index
1130 * @param[in] gpr_mask bit mask of gpr registers to be locked
1131 */
sysctl_cpu_lock_gpr_with_mask(SYSCTL_Type * ptr,uint8_t cpu_index,uint16_t gpr_mask)1132 static inline void sysctl_cpu_lock_gpr_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint16_t gpr_mask)
1133 {
1134 ptr->CPU[cpu_index].LOCK |= SYSCTL_CPU_LOCK_GPR_SET(gpr_mask);
1135 }
1136
1137
1138 /**
1139 * @brief Lock CPU0 gpr with mask
1140 *
1141 * @param[in] ptr SYSCTL_Type base address
1142 * @param[in] gpr_mask bit mask of gpr registers to be locked
1143 */
sysctl_cpu0_lock_gpr_with_mask(SYSCTL_Type * ptr,uint16_t gpr_mask)1144 static inline void sysctl_cpu0_lock_gpr_with_mask(SYSCTL_Type *ptr, uint16_t gpr_mask)
1145 {
1146 sysctl_cpu_lock_gpr_with_mask(ptr, 0, gpr_mask);
1147 }
1148
1149 /**
1150 * @brief Lock CPU1 gpr with mask
1151 *
1152 * @param[in] ptr SYSCTL_Type base address
1153 * @param[in] gpr_mask bit mask of gpr registers to be locked
1154 */
sysctl_cpu1_lock_gpr_with_mask(SYSCTL_Type * ptr,uint16_t gpr_mask)1155 static inline void sysctl_cpu1_lock_gpr_with_mask(SYSCTL_Type *ptr, uint16_t gpr_mask)
1156 {
1157 sysctl_cpu_lock_gpr_with_mask(ptr, 1, gpr_mask);
1158 }
1159
1160 /**
1161 * @brief Lock CPU lock
1162 *
1163 * @param[in] ptr SYSCTL_Type base address
1164 * @param[in] cpu_index CPU index
1165 */
sysctl_cpu_lock(SYSCTL_Type * ptr,uint8_t cpu_index)1166 static inline void sysctl_cpu_lock(SYSCTL_Type *ptr, uint8_t cpu_index)
1167 {
1168 ptr->CPU[cpu_index].LOCK |= SYSCTL_CPU_LOCK_LOCK_MASK;
1169 }
1170
1171 /**
1172 * @brief Lock CPU0 lock
1173 *
1174 * @param[in] ptr SYSCTL_Type base address
1175 */
sysctl_cpu0_lock(SYSCTL_Type * ptr)1176 static inline void sysctl_cpu0_lock(SYSCTL_Type *ptr)
1177 {
1178 sysctl_cpu_lock(ptr, 0);
1179 }
1180
1181 /**
1182 * @brief Lock CPU1 lock
1183 *
1184 * @param[in] ptr SYSCTL_Type base address
1185 */
sysctl_cpu1_lock(SYSCTL_Type * ptr)1186 static inline void sysctl_cpu1_lock(SYSCTL_Type *ptr)
1187 {
1188 sysctl_cpu_lock(ptr, 1);
1189 }
1190
1191 /**
1192 * @brief Set CPU low power mode
1193 *
1194 * @param[in] ptr SYSCTL_Type base address
1195 * @param[in] cpu_index CPU index
1196 * @param[in] mode target mode to set
1197 */
sysctl_set_cpu_lp_mode(SYSCTL_Type * ptr,uint8_t cpu_index,cpu_lp_mode_t mode)1198 static inline void sysctl_set_cpu_lp_mode(SYSCTL_Type *ptr, uint8_t cpu_index, cpu_lp_mode_t mode)
1199 {
1200 ptr->CPU[cpu_index].LP = (ptr->CPU[cpu_index].LP & ~(SYSCTL_CPU_LP_MODE_MASK)) | (mode);
1201 }
1202
1203 /**
1204 * @brief Set CPU0 low power mode
1205 *
1206 * @param[in] ptr SYSCTL_Type base address
1207 * @param[in] mode target mode to set
1208 */
sysctl_set_cpu0_lp_mode(SYSCTL_Type * ptr,cpu_lp_mode_t mode)1209 static inline void sysctl_set_cpu0_lp_mode(SYSCTL_Type *ptr, cpu_lp_mode_t mode)
1210 {
1211 sysctl_set_cpu_lp_mode(ptr, 0, mode);
1212 }
1213
1214 /**
1215 * @brief Set CPU1 low power mode
1216 *
1217 * @param[in] ptr SYSCTL_Type base address
1218 * @param[in] mode target mode to set
1219 */
sysctl_set_cpu1_lp_mode(SYSCTL_Type * ptr,cpu_lp_mode_t mode)1220 static inline void sysctl_set_cpu1_lp_mode(SYSCTL_Type *ptr, cpu_lp_mode_t mode)
1221 {
1222 sysctl_set_cpu_lp_mode(ptr, 1, mode);
1223 }
1224
1225 /**
1226 * @brief Clear CPU event flags
1227 *
1228 * @param[in] ptr SYSCTL_Type base address
1229 * @param[in] cpu_index CPU index
1230 * @param[in] flags flag mask to be cleared
1231 */
sysctl_clear_cpu_flags(SYSCTL_Type * ptr,uint8_t cpu_index,cpu_event_flag_mask_t flags)1232 static inline void sysctl_clear_cpu_flags(SYSCTL_Type *ptr, uint8_t cpu_index, cpu_event_flag_mask_t flags)
1233 {
1234 ptr->CPU[cpu_index].LP |=
1235 ((SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK | SYSCTL_CPU_LP_RESET_FLAG_MASK) & flags);
1236 }
1237
1238 /**
1239 * @brief Clear CPU0 event flags
1240 *
1241 * @param[in] ptr SYSCTL_Type base address
1242 * @param[in] flags flag mask to be cleared
1243 */
sysctl_clear_cpu0_flags(SYSCTL_Type * ptr,cpu_event_flag_mask_t flags)1244 static inline void sysctl_clear_cpu0_flags(SYSCTL_Type *ptr, cpu_event_flag_mask_t flags)
1245 {
1246 sysctl_clear_cpu_flags(ptr, 0, flags);
1247 }
1248
1249 /**
1250 * @brief Clear CPU1 event flags
1251 *
1252 * @param[in] ptr SYSCTL_Type base address
1253 * @param[in] flags flag mask to be cleared
1254 */
sysctl_clear_cpu1_flags(SYSCTL_Type * ptr,cpu_event_flag_mask_t flags)1255 static inline void sysctl_clear_cpu1_flags(SYSCTL_Type *ptr, cpu_event_flag_mask_t flags)
1256 {
1257 sysctl_clear_cpu_flags(ptr, 1, flags);
1258 }
1259
1260 /**
1261 * @brief Get CPU event flags
1262 *
1263 * @param[in] ptr SYSCTL_Type base address
1264 * @param[in] cpu_index CPU index
1265 * @retval event flag mask
1266 */
sysctl_get_cpu_flags(SYSCTL_Type * ptr,uint8_t cpu_index)1267 static inline uint32_t sysctl_get_cpu_flags(SYSCTL_Type *ptr, uint8_t cpu_index)
1268 {
1269 return ptr->CPU[cpu_index].LP &
1270 (SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK | SYSCTL_CPU_LP_RESET_FLAG_MASK);
1271 }
1272
1273 /**
1274 * @brief Get CPU0 event flags
1275 *
1276 * @param[in] ptr SYSCTL_Type base address
1277 * @retval event flag mask
1278 */
sysctl_get_cpu0_flags(SYSCTL_Type * ptr)1279 static inline uint32_t sysctl_get_cpu0_flags(SYSCTL_Type *ptr)
1280 {
1281 return sysctl_get_cpu_flags(ptr, 0);
1282 }
1283
1284 /**
1285 * @brief Get CPU1 event flags
1286 *
1287 * @param[in] ptr SYSCTL_Type base address
1288 * @retval event flag mask
1289 */
sysctl_get_cpu1_flags(SYSCTL_Type * ptr)1290 static inline uint32_t sysctl_get_cpu1_flags(SYSCTL_Type *ptr)
1291 {
1292 return sysctl_get_cpu_flags(ptr, 1);
1293 }
1294
1295 /**
1296 * @brief Release cpu
1297 *
1298 * @param[in] ptr SYSCTL_Type base address
1299 * @param[in] cpu_index CPU index
1300 */
sysctl_release_cpu(SYSCTL_Type * ptr,uint8_t cpu_index)1301 static inline void sysctl_release_cpu(SYSCTL_Type *ptr, uint8_t cpu_index)
1302 {
1303 ptr->CPU[cpu_index].LP &= ~SYSCTL_CPU_LP_HALT_MASK;
1304 }
1305
1306 /**
1307 * @brief Release cpu1
1308 *
1309 * @param[in] ptr SYSCTL_Type base address
1310 */
sysctl_release_cpu1(SYSCTL_Type * ptr)1311 static inline void sysctl_release_cpu1(SYSCTL_Type *ptr)
1312 {
1313 sysctl_release_cpu(ptr, 1);
1314 }
1315
1316 /**
1317 * @brief Check whether CPU is released or not
1318 *
1319 * @param [in] ptr SYSCTL_Type base address
1320 * @param[in] cpu_index CPU index
1321 * @retval true CPU is released
1322 * @retval false CPU is on-hold
1323 */
sysctl_is_cpu_released(SYSCTL_Type * ptr,uint8_t cpu_index)1324 static inline bool sysctl_is_cpu_released(SYSCTL_Type *ptr, uint8_t cpu_index)
1325 {
1326 return ((ptr->CPU[cpu_index].LP & SYSCTL_CPU_LP_HALT_MASK) == 0U);
1327 }
1328
1329 /**
1330 * @brief Check whether CPU1 is released or not
1331 *
1332 * @param [in] ptr SYSCTL_Type base address
1333 * @retval true CPU1 is released
1334 * @retval false CPU1 is on-hold
1335 */
sysctl_is_cpu1_released(SYSCTL_Type * ptr)1336 static inline bool sysctl_is_cpu1_released(SYSCTL_Type *ptr)
1337 {
1338 return sysctl_is_cpu_released(ptr, 1);
1339 }
1340
1341 /**
1342 * @brief Config lock
1343 *
1344 * @param[in] ptr SYSCTL_Type base address
1345 * @param[in] node clock node to be configured
1346 * @param[in] source clock source to be used
1347 * @param[in] divide_by clock frequency divider
1348 * @return status_success if everything is okay
1349 */
1350 hpm_stat_t sysctl_config_clock(SYSCTL_Type *ptr, clock_node_t node, clock_source_t source, uint32_t divide_by);
1351
1352 /**
1353 * @brief Configure CPU domain clock
1354 * @param ptr SYSCTL base address
1355 * @param source clock source to be used
1356 * @param cpu_div CPU divider
1357 * @param axi_sub_div AXI BUS divider based on divided CPU clock
1358 * @param ahb_sub_div AHB BUS divider based on divided CPU clock
1359 * @return status_success if everything is okay
1360 */
1361 hpm_stat_t sysctl_config_cpu0_domain_clock(SYSCTL_Type *ptr,
1362 clock_source_t source,
1363 uint32_t cpu_div,
1364 uint32_t axi_sub_div,
1365 uint32_t ahb_sub_div);
1366
1367 /**
1368 * @brief Set ADC clock mux
1369 *
1370 * @param[in] ptr SYSCTL_Type base address
1371 * @param[in] node clock node to be configured
1372 * @param[in] source clock source to be used
1373 * @return status_success if everything is okay
1374 */
1375 hpm_stat_t sysctl_set_adc_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_adc_t source);
1376
1377
1378 /**
1379 * @brief Set DAC clock mux
1380 *
1381 * @param[in] ptr SYSCTL_Type base address
1382 * @param[in] node clock node to be configured
1383 * @param[in] source clock source to be used
1384 * @return status_success if everything is okay
1385 */
1386 hpm_stat_t sysctl_set_dac_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_dac_t source);
1387
1388 /**
1389 * @brief Enable group resource
1390 *
1391 * @param[in] ptr SYSCTL_Type base address
1392 * @param[in] group target group to be modified
1393 * @param[in] resource target resource to be added/removed from group
1394 * @param[in] enable set true to add resource, remove otherwise
1395 * @return status_success if everything is okay
1396 */
1397 hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr,
1398 uint8_t group,
1399 sysctl_resource_t resource,
1400 bool enable);
1401
1402 /**
1403 * @brief Check group resource enable status
1404 *
1405 * @param[in] ptr SYSCTL_Type base address
1406 * @param[in] group target group to be checked
1407 * @param[in] resource target resource to be checked from group
1408 * @return enable true if resource enable, false if resource disable
1409 */
1410 bool sysctl_check_group_resource_enable(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t linkable_resource);
1411
1412 /**
1413 * @brief Get group resource value
1414 *
1415 * @param[in] ptr SYSCTL_Type base address
1416 * @param[in] group target group to be getted
1417 * @param[in] index target group index
1418 * @return group index value
1419 */
1420 uint32_t sysctl_get_group_resource_value(SYSCTL_Type *ptr, uint8_t group, uint8_t index);
1421
1422 /**
1423 * @brief Add resource to CPU0
1424 *
1425 * @param[in] ptr SYSCTL_Type base address
1426 * @param[in] resource resource to be added to CPU0
1427 * @return status_success if everything is okay
1428 */
1429 hpm_stat_t sysctl_add_resource_to_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource);
1430
1431 /**
1432 * @brief Remove resource from CPU0
1433 *
1434 * @param[in] ptr SYSCTL_Type base address
1435 * @param[in] resource Resource to be removed to CPU0
1436 * @return status_success if everything is okay
1437 */
1438 hpm_stat_t sysctl_remove_resource_from_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource);
1439
1440 /**
1441 * @brief Add resource to CPU1
1442 *
1443 * @param[in] ptr SYSCTL_Type base address
1444 * @param[in] resource Resource to be added to CPU1
1445 * @return status_success if everything is okay
1446 */
1447 hpm_stat_t sysctl_add_resource_to_cpu1(SYSCTL_Type *ptr, sysctl_resource_t resource);
1448
1449 /**
1450 * @brief Remove resource from CPU1
1451 *
1452 * @param[in] ptr SYSCTL_Type base address
1453 * @param[in] resource Resource to be removed to CPU1
1454 * @return status_success if everything is okay
1455 */
1456 hpm_stat_t sysctl_remove_resource_from_cpu1(SYSCTL_Type *ptr, sysctl_resource_t resource);
1457
1458 /**
1459 * @brief Get default monitor config
1460 *
1461 * @param[in] ptr SYSCTL_Type base address
1462 * @param[in] config Monitor config structure pointer
1463 */
1464 void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *config);
1465
1466 /**
1467 * @brief Initialize Monitor
1468 *
1469 * @param[in] ptr SYSCTL_Type base address
1470 * @param[in] monitor_index Monitor instance to be initialized
1471 * @param[in] config Monitor config structure pointer
1472 */
1473 void sysctl_monitor_init(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_config_t *config);
1474
1475 /**
1476 * @brief Save data to CPU0 GPR starting from given index
1477 *
1478 * @param[in] ptr SYSCTL_Type base address
1479 * @param[in] start Starting GPR index
1480 * @param[in] count Number of GPR registers to set
1481 * @param[in] data Pointer to data buffer
1482 * @param[in] lock Set true to lock written GPR registers after setting
1483 * @return status_success if everything is okay
1484 */
1485 hpm_stat_t sysctl_cpu0_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock);
1486
1487 /**
1488 * @brief Get data saved from CPU0 GPR starting from given index
1489 *
1490 * @param[in] ptr SYSCTL_Type base address
1491 * @param[in] start Starting GPR index
1492 * @param[in] count Number of GPR registers to set
1493 * @param[out] data Pointer of buffer to save data
1494 * @return status_success if everything is okay
1495 */
1496 hpm_stat_t sysctl_cpu0_get_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data);
1497
1498 /**
1499 * @brief Set data to CPU1 GPR starting from given index
1500 *
1501 * @param[in] ptr SYSCTL_Type base address
1502 * @param[in] start Starting GPR index
1503 * @param[in] count Number of GPR registers to set
1504 * @param[in] data Pointer to data buffer
1505 * @param[in] lock Set true to lock written GPR registers after setting
1506 * @return status_success if everything is okay
1507 */
1508 hpm_stat_t sysctl_cpu1_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock);
1509
1510 /**
1511 * @brief Get data saved in CPU1 GPR starting from given index
1512 *
1513 * @param[in] ptr SYSCTL_Type base address
1514 * @param[in] start Starting GPR index
1515 * @param[in] count Number of GPR registers to set
1516 * @param[out] data Pointer of buffer to save data
1517 * @return status_success if everything is okay
1518 */
1519 hpm_stat_t sysctl_get_cpu1_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data);
1520
1521 /**
1522 * @brief Set entry point on CPU boot or wakeup
1523 *
1524 * @param[in] ptr SYSCTL_Type base address
1525 * @param[in] cpu CPU index
1526 * @param[in] entry Entry address for CPU
1527 * @return status_success if everything is okay
1528 */
1529 hpm_stat_t sysctl_set_cpu_entry(SYSCTL_Type *ptr, uint8_t cpu, uint32_t entry);
1530
1531 /**
1532 * @brief Set entry point on CPU0 wakeup
1533 *
1534 * @param[in] ptr SYSCTL_Type base address
1535 * @param[in] entry Entry address for CPU0 on its wakeup
1536 * @return status_success if everything is okay
1537 */
1538 hpm_stat_t sysctl_set_cpu0_wakeup_entry(SYSCTL_Type *ptr, uint32_t entry);
1539
1540 /**
1541 * @brief Set entry point on either CPU1 boot or wakeup
1542 *
1543 * @param[in] ptr SYSCTL_Type base address
1544 * @param[in] entry Entry address for CPU1
1545 * @return status_success if everything is okay
1546 */
1547 hpm_stat_t sysctl_set_cpu1_entry(SYSCTL_Type *ptr, uint32_t entry);
1548
1549 #ifdef __cplusplus
1550 }
1551 #endif
1552 /**
1553 * @}
1554 */
1555 #endif /* HPM_SYSCTL_DRV_H */
1556