1 /**
2 * Copyright (c) 2021 HPMicro
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7
8 #ifndef HPM_SYSCTL_DRV_H
9 #define HPM_SYSCTL_DRV_H
10
11 #include "hpm_common.h"
12 #include "hpm_sysctl_regs.h"
13
14 /**
15 *
16 * @brief SYSCTL driver APIs
17 * @defgroup sysctl_interface SYSCTL driver APIs
18 * @ingroup io_interfaces
19 * @{
20 */
21
22 /**
23 * @brief Retention domains
24 */
25 typedef enum {
26 sysctl_retention_domain_sys = 0,
27 sysctl_retention_domain_cpu0 = 2,
28 sysctl_retention_domain_cpu1 = 4,
29 sysctl_retention_domain_conn = 6,
30 sysctl_retention_domain_vis = 8,
31 sysctl_retention_domain_xtal24m = 10,
32 sysctl_retention_domain_pll0 = 11,
33 sysctl_retention_domain_pll1 = 12,
34 sysctl_retention_domain_pll2 = 13,
35 sysctl_retention_domain_pll3 = 14,
36 sysctl_retention_domain_pll4 = 15,
37 } sysctl_retention_domain_t;
38
39 /**
40 * @brief Clock presets
41 */
42 typedef enum {
43 sysctl_preset_0 = 1 << 0,
44 sysctl_preset_1 = 1 << 1,
45 sysctl_preset_2 = 1 << 2,
46 sysctl_preset_3 = 1 << 3,
47 } sysctl_preset_t;
48
49 /**
50 * @brief Reset domains
51 */
52 typedef enum {
53 sysctl_reset_domain_soc = 0,
54 sysctl_reset_domain_con,
55 sysctl_reset_domain_vis,
56 sysctl_reset_domain_cpu0,
57 sysctl_reset_domain_cpu1,
58 } sysctl_reset_domain_t;
59
60 /**
61 * @brief Resource
62 */
63 typedef enum {
64 sysctl_resource_cpu0 = 0,
65 sysctl_resource_cpx0 = 1,
66 sysctl_resource_exe0 = 2,
67 sysctl_resource_wak0 = 3,
68 sysctl_resource_cpu0_per = 4,
69 sysctl_resource_cpu1 = 8,
70 sysctl_resource_cpx1 = 9,
71 sysctl_resource_exe1 = 10,
72 sysctl_resource_wak1 = 11,
73 sysctl_resource_cpu1_per = 12,
74 sysctl_resource_logic0 = 16,
75 sysctl_resource_logic1 = 17,
76 sysctl_resource_logic2 = 18,
77 sysctl_resource_logic3 = 19,
78 sysctl_resource_pmic = 20,
79 sysctl_resource_pow_con = 21,
80 sysctl_resource_pow_vis = 22,
81 sysctl_resource_pow_cpu0 = 23,
82 sysctl_resource_pow_cpu1 = 24,
83 sysctl_resource_rst_soc = 25,
84 sysctl_resource_rst_con = 26,
85 sysctl_resource_rst_vis = 27,
86 sysctl_resource_rst_cpu0 = 28,
87 sysctl_resource_rst_cpu1 = 29,
88 sysctl_resource_xtal = 32,
89 sysctl_resource_pll0 = 33,
90 sysctl_resource_clk0_pll0 = 34,
91 sysctl_resource_pll1 = 35,
92 sysctl_resource_clk0_pll1 = 36,
93 sysctl_resource_clk1_pll1 = 37,
94 sysctl_resource_pll2 = 38,
95 sysctl_resource_clk0_pll2 = 39,
96 sysctl_resource_clk1_pll2 = 40,
97 sysctl_resource_pll3 = 41,
98 sysctl_resource_clk0_pll3 = 42,
99 sysctl_resource_pll4 = 43,
100 sysctl_resource_clk0_pll4 = 44,
101 sysctl_resource_mbist_soc = 48,
102 sysctl_resource_mbist_cpu = 49,
103 sysctl_resource_mbist_cpu1 = 50,
104 sysctl_resource_mbist_con = 51,
105 sysctl_resource_mbist_vis = 52,
106 sysctl_resource_clk_top_cpu0 = 64,
107 sysctl_resource_clk_top_mchtmr0 = 65,
108 sysctl_resource_clk_top_cpu1 = 66,
109 sysctl_resource_clk_top_mchtmr1 = 67,
110 sysctl_resource_clk_top_axi0 = 68,
111 sysctl_resource_clk_top_axi1 = 69,
112 sysctl_resource_clk_top_axi2 = 70,
113 sysctl_resource_clk_top_ahb0 = 71,
114 sysctl_resource_clk_top_femc = 72,
115 sysctl_resource_clk_top_xpi0 = 73,
116 sysctl_resource_clk_top_xpi1 = 74,
117 sysctl_resource_clk_top_gptmr0 = 75,
118 sysctl_resource_clk_top_gptmr1 = 76,
119 sysctl_resource_clk_top_gptmr2 = 77,
120 sysctl_resource_clk_top_gptmr3 = 78,
121 sysctl_resource_clk_top_gptmr4 = 79,
122 sysctl_resource_clk_top_gptmr5 = 80,
123 sysctl_resource_clk_top_gptmr6 = 81,
124 sysctl_resource_clk_top_gptmr7 = 82,
125 sysctl_resource_clk_top_uart0 = 83,
126 sysctl_resource_clk_top_uart1 = 84,
127 sysctl_resource_clk_top_uart2 = 85,
128 sysctl_resource_clk_top_uart3 = 86,
129 sysctl_resource_clk_top_uart4 = 87,
130 sysctl_resource_clk_top_uart5 = 88,
131 sysctl_resource_clk_top_uart6 = 89,
132 sysctl_resource_clk_top_uart7 = 90,
133 sysctl_resource_clk_top_uart8 = 91,
134 sysctl_resource_clk_top_uart9 = 92,
135 sysctl_resource_clk_top_uarta = 93,
136 sysctl_resource_clk_top_uartb = 94,
137 sysctl_resource_clk_top_uartc = 95,
138 sysctl_resource_clk_top_uartd = 96,
139 sysctl_resource_clk_top_uarte = 97,
140 sysctl_resource_clk_top_uartf = 98,
141 sysctl_resource_clk_top_i2c0 = 99,
142 sysctl_resource_clk_top_i2c1 = 100,
143 sysctl_resource_clk_top_i2c2 = 101,
144 sysctl_resource_clk_top_i2c3 = 102,
145 sysctl_resource_clk_top_spi0 = 103,
146 sysctl_resource_clk_top_spi1 = 104,
147 sysctl_resource_clk_top_spi2 = 105,
148 sysctl_resource_clk_top_spi3 = 106,
149 sysctl_resource_clk_top_can0 = 107,
150 sysctl_resource_clk_top_can1 = 108,
151 sysctl_resource_clk_top_can2 = 109,
152 sysctl_resource_clk_top_can3 = 110,
153 sysctl_resource_clk_top_ptpc = 111,
154 sysctl_resource_clk_top_ana0 = 112,
155 sysctl_resource_clk_top_ana1 = 113,
156 sysctl_resource_clk_top_ana2 = 114,
157 sysctl_resource_clk_top_aud0 = 115,
158 sysctl_resource_clk_top_aud1 = 116,
159 sysctl_resource_clk_top_aud2 = 117,
160 sysctl_resource_clk_top_dis0 = 118,
161 sysctl_resource_clk_top_cam0 = 119,
162 sysctl_resource_clk_top_cam1 = 120,
163 sysctl_resource_clk_top_eth0 = 121,
164 sysctl_resource_clk_top_eth1 = 122,
165 sysctl_resource_clk_top_ptp0 = 123,
166 sysctl_resource_clk_top_ptp1 = 124,
167 sysctl_resource_clk_top_ref0 = 125,
168 sysctl_resource_clk_top_ref1 = 126,
169 sysctl_resource_clk_top_ntmr0 = 127,
170 sysctl_resource_clk_top_ntmr1 = 128,
171 sysctl_resource_clk_top_sdxc0 = 129,
172 sysctl_resource_clk_top_sdxc1 = 130,
173 sysctl_resource_clk_top_adc0 = 192,
174 sysctl_resource_clk_top_adc1 = 193,
175 sysctl_resource_clk_top_adc2 = 194,
176 sysctl_resource_clk_top_adc3 = 195,
177 sysctl_resource_clk_top_i2s0 = 196,
178 sysctl_resource_clk_top_i2s1 = 197,
179 sysctl_resource_clk_top_i2s2 = 198,
180 sysctl_resource_clk_top_i2s3 = 199,
181
182 sysctl_resource_linkable_start = 256,
183 sysctl_resource_ahbp = 256,
184 sysctl_resource_axis = 257,
185 sysctl_resource_axic = 258,
186 sysctl_resource_axiv = 259,
187 sysctl_resource_femc = 260,
188 sysctl_resource_rom0 = 261,
189 sysctl_resource_lmm0 = 262,
190 sysctl_resource_lmm1 = 263,
191 sysctl_resource_mchtmr0 = 264,
192 sysctl_resource_mchtmr1 = 265,
193 sysctl_resource_ram0 = 266,
194 sysctl_resource_ram1 = 267,
195 sysctl_resource_xpi0 = 268,
196 sysctl_resource_xpi1 = 269,
197 sysctl_resource_sdp0 = 270,
198 sysctl_resource_rng0 = 271,
199 sysctl_resource_kman = 272,
200 sysctl_resource_dma0 = 273,
201 sysctl_resource_dma1 = 274,
202 sysctl_resource_gpio = 275,
203 sysctl_resource_mbx0 = 276,
204 sysctl_resource_mbx1 = 277,
205 sysctl_resource_wdg0 = 278,
206 sysctl_resource_wdg1 = 279,
207 sysctl_resource_wdg2 = 280,
208 sysctl_resource_wdg3 = 281,
209 sysctl_resource_gptmr0 = 282,
210 sysctl_resource_gptmr1 = 283,
211 sysctl_resource_gptmr2 = 284,
212 sysctl_resource_gptmr3 = 285,
213 sysctl_resource_gptmr4 = 286,
214 sysctl_resource_gptmr5 = 287,
215 sysctl_resource_gptmr6 = 288,
216 sysctl_resource_gptmr7 = 289,
217 sysctl_resource_uart0 = 290,
218 sysctl_resource_uart1 = 291,
219 sysctl_resource_uart2 = 292,
220 sysctl_resource_uart3 = 293,
221 sysctl_resource_uart4 = 294,
222 sysctl_resource_uart5 = 295,
223 sysctl_resource_uart6 = 296,
224 sysctl_resource_uart7 = 297,
225 sysctl_resource_uart8 = 298,
226 sysctl_resource_uart9 = 299,
227 sysctl_resource_uarta = 300,
228 sysctl_resource_uartb = 301,
229 sysctl_resource_uartc = 302,
230 sysctl_resource_uartd = 303,
231 sysctl_resource_uarte = 304,
232 sysctl_resource_uartf = 305,
233 sysctl_resource_i2c0 = 306,
234 sysctl_resource_i2c1 = 307,
235 sysctl_resource_i2c2 = 308,
236 sysctl_resource_i2c3 = 309,
237 sysctl_resource_spi0 = 310,
238 sysctl_resource_spi1 = 311,
239 sysctl_resource_spi2 = 312,
240 sysctl_resource_spi3 = 313,
241 sysctl_resource_can0 = 314,
242 sysctl_resource_can1 = 315,
243 sysctl_resource_can2 = 316,
244 sysctl_resource_can3 = 317,
245 sysctl_resource_ptpc = 318,
246 sysctl_resource_adc0 = 319,
247 sysctl_resource_adc1 = 320,
248 sysctl_resource_adc2 = 321,
249 sysctl_resource_adc3 = 322,
250 sysctl_resource_acmp = 323,
251 sysctl_resource_i2s0 = 324,
252 sysctl_resource_i2s1 = 325,
253 sysctl_resource_i2s2 = 326,
254 sysctl_resource_i2s3 = 327,
255 sysctl_resource_i2spdm0 = 328,
256 sysctl_resource_i2sdao = 329,
257 sysctl_resource_msyn = 330,
258 sysctl_resource_mot0 = 331,
259 sysctl_resource_mot1 = 332,
260 sysctl_resource_mot2 = 333,
261 sysctl_resource_mot3 = 334,
262 sysctl_resource_dis0 = 335,
263 sysctl_resource_cam0 = 336,
264 sysctl_resource_cam1 = 337,
265 sysctl_resource_jpeg = 338,
266 sysctl_resource_pdma = 339,
267 sysctl_resource_eth0 = 340,
268 sysctl_resource_eth1 = 341,
269 sysctl_resource_ntmr0 = 342,
270 sysctl_resource_ntmr1 = 343,
271 sysctl_resource_sdxc0 = 344,
272 sysctl_resource_sdxc1 = 345,
273 sysctl_resource_usb0 = 346,
274 sysctl_resource_usb1 = 347,
275 sysctl_resource_ref0 = 348,
276 sysctl_resource_ref1 = 349,
277 sysctl_resource_linkable_end,
278 sysctl_resource_end = sysctl_resource_linkable_end,
279 } sysctl_resource_t;
280
281 /**
282 * @brief Resource modes
283 */
284 typedef enum {
285 sysctl_resource_mode_auto = 0,
286 sysctl_resource_mode_force_on,
287 sysctl_resource_mode_force_off,
288 } sysctl_resource_mode_t;
289
290 /**
291 * @brief Clock nodes
292 */
293 typedef enum {
294 clock_node_cpu0 = 0,
295 clock_node_mchtmr0 = 1,
296 clock_node_cpu1 = 2,
297 clock_node_mchtmr1 = 3,
298 clock_node_axi0 = 4,
299 clock_node_axi1 = 5,
300 clock_node_axi2 = 6,
301 clock_node_ahb0 = 7,
302 clock_node_femc = 8,
303 clock_node_xpi0 = 9,
304 clock_node_xpi1 = 10,
305 clock_node_gptmr0 = 11,
306 clock_node_gptmr1 = 12,
307 clock_node_gptmr2 = 13,
308 clock_node_gptmr3 = 14,
309 clock_node_gptmr4 = 15,
310 clock_node_gptmr5 = 16,
311 clock_node_gptmr6 = 17,
312 clock_node_gptmr7 = 18,
313 clock_node_uart0 = 19,
314 clock_node_uart1 = 20,
315 clock_node_uart2 = 21,
316 clock_node_uart3 = 22,
317 clock_node_uart4 = 23,
318 clock_node_uart5 = 24,
319 clock_node_uart6 = 25,
320 clock_node_uart7 = 26,
321 clock_node_uart8 = 27,
322 clock_node_uart9 = 28,
323 clock_node_uarta = 29,
324 clock_node_uartb = 30,
325 clock_node_uartc = 31,
326 clock_node_uartd = 32,
327 clock_node_uarte = 33,
328 clock_node_uartf = 34,
329 clock_node_i2c0 = 35,
330 clock_node_i2c1 = 36,
331 clock_node_i2c2 = 37,
332 clock_node_i2c3 = 38,
333 clock_node_spi0 = 39,
334 clock_node_spi1 = 40,
335 clock_node_spi2 = 41,
336 clock_node_spi3 = 42,
337 clock_node_can0 = 43,
338 clock_node_can1 = 44,
339 clock_node_can2 = 45,
340 clock_node_can3 = 46,
341 clock_node_ptpc = 47,
342 clock_node_ana0 = 48,
343 clock_node_ana1 = 49,
344 clock_node_ana2 = 50,
345 clock_node_aud0 = 51,
346 clock_node_aud1 = 52,
347 clock_node_aud2 = 53,
348 clock_node_dis0 = 54,
349 clock_node_cam0 = 55,
350 clock_node_cam1 = 56,
351 clock_node_eth0 = 57,
352 clock_node_eth1 = 58,
353 clock_node_ptp0 = 59,
354 clock_node_ptp1 = 60,
355 clock_node_ref0 = 61,
356 clock_node_ref1 = 62,
357 clock_node_ntmr0 = 63,
358 clock_node_ntmr1 = 64,
359 clock_node_sdxc0 = 65,
360 clock_node_sdxc1 = 66,
361
362 clock_node_adc_i2s_start,
363 clock_node_adc0 = clock_node_adc_i2s_start,
364 clock_node_adc1,
365 clock_node_adc2,
366 clock_node_adc3,
367
368 clock_node_i2s0,
369 clock_node_i2s1,
370 clock_node_i2s2,
371 clock_node_i2s3,
372 clock_node_end,
373 } clock_node_t;
374
375 /**
376 * @brief General clock sources
377 */
378 typedef enum {
379 clock_source_osc0_clk0 = 0,
380 clock_source_pll0_clk0 = 1,
381 clock_source_pll1_clk0 = 2,
382 clock_source_pll1_clk1 = 3,
383 clock_source_pll2_clk0 = 4,
384 clock_source_pll2_clk1 = 5,
385 clock_source_pll3_clk0 = 6,
386 clock_source_pll4_clk0 = 7,
387 clock_source_general_source_end,
388 } clock_source_t;
389
390 /**
391 * @brief ADC/I2S clock sources
392 */
393 typedef enum {
394 clock_source_adc_i2s_ahb_clk = 0,
395 clock_source_adc_ana0_clk = 1,
396 clock_source_i2s_aud0_clk = 1,
397 clock_source_adc_ana1_clk = 2,
398 clock_source_i2s_aud1_clk = 2,
399 clock_source_adc_ana2_clk = 3,
400 clock_source_i2s_aud2_clk = 3,
401 clock_source_adc_i2s_clk_end,
402 } clock_source_adc_i2s_t;
403
404 /**
405 * @brief CPU low power mode
406 */
407 typedef enum {
408 cpu_lp_mode_gate_cpu_clock = 0,
409 cpu_lp_mode_trigger_system_lp = 0x1,
410 cpu_lp_mode_ungate_cpu_clock = 0x2,
411 } cpu_lp_mode_t;
412
413 /**
414 * @brief Monitor targets
415 */
416 typedef enum {
417 monitor_target_clk_32k = 0,
418 monitor_target_clk_irc24m = 1,
419 monitor_target_clk_xtal_24m = 2,
420 monitor_target_clk_usb0_phy = 3,
421 monitor_target_clk_usb1_phy = 4,
422 monitor_target_osc0_clk0 = 8,
423 monitor_target_pll0_clk0 = 9,
424 monitor_target_pll1_clk0 = 10,
425 monitor_target_pll1_clk1 = 11,
426 monitor_target_pll2_clk0 = 12,
427 monitor_target_pll2_clk1 = 13,
428 monitor_target_pll3_clk0 = 14,
429 monitor_target_pll4_clk0 = 15,
430 monitor_target_clk_top_cpu0 = 128,
431 monitor_target_clk_top_mchtmr0 = 129,
432 monitor_target_clk_top_cpu1 = 130,
433 monitor_target_clk_top_mchtmr1 = 131,
434 monitor_target_clk_top_axi0 = 132,
435 monitor_target_clk_top_axi1 = 133,
436 monitor_target_clk_top_axi2 = 134,
437 monitor_target_clk_top_ahb0 = 135,
438 monitor_target_clk_top_femc = 136,
439 monitor_target_clk_top_xpi0 = 137,
440 monitor_target_clk_top_xpi1 = 138,
441 monitor_target_clk_top_gptmr0 = 139,
442 monitor_target_clk_top_gptmr1 = 140,
443 monitor_target_clk_top_gptmr2 = 141,
444 monitor_target_clk_top_gptmr3 = 142,
445 monitor_target_clk_top_gptmr4 = 143,
446 monitor_target_clk_top_gptmr5 = 144,
447 monitor_target_clk_top_gptmr6 = 145,
448 monitor_target_clk_top_gptmr7 = 146,
449 monitor_target_clk_top_uart0 = 147,
450 monitor_target_clk_top_uart1 = 148,
451 monitor_target_clk_top_uart2 = 149,
452 monitor_target_clk_top_uart3 = 150,
453 monitor_target_clk_top_uart4 = 151,
454 monitor_target_clk_top_uart5 = 152,
455 monitor_target_clk_top_uart6 = 153,
456 monitor_target_clk_top_uart7 = 154,
457 monitor_target_clk_top_uart8 = 155,
458 monitor_target_clk_top_uart9 = 156,
459 monitor_target_clk_top_uarta = 157,
460 monitor_target_clk_top_uartb = 158,
461 monitor_target_clk_top_uartc = 159,
462 monitor_target_clk_top_uartd = 160,
463 monitor_target_clk_top_uarte = 161,
464 monitor_target_clk_top_uartf = 162,
465 monitor_target_clk_top_i2c0 = 163,
466 monitor_target_clk_top_i2c1 = 164,
467 monitor_target_clk_top_i2c2 = 165,
468 monitor_target_clk_top_i2c3 = 166,
469 monitor_target_clk_top_spi0 = 167,
470 monitor_target_clk_top_spi1 = 168,
471 monitor_target_clk_top_spi2 = 169,
472 monitor_target_clk_top_spi3 = 170,
473 monitor_target_clk_top_can0 = 171,
474 monitor_target_clk_top_can1 = 172,
475 monitor_target_clk_top_can2 = 173,
476 monitor_target_clk_top_can3 = 174,
477 monitor_target_clk_top_ptpc = 175,
478 monitor_target_clk_top_ana0 = 176,
479 monitor_target_clk_top_ana1 = 177,
480 monitor_target_clk_top_ana2 = 178,
481 monitor_target_clk_top_aud0 = 179,
482 monitor_target_clk_top_aud1 = 180,
483 monitor_target_clk_top_aud2 = 181,
484 monitor_target_clk_top_dis0 = 182,
485 monitor_target_clk_top_cam0 = 183,
486 monitor_target_clk_top_cam1 = 184,
487 monitor_target_clk_top_eth0 = 185,
488 monitor_target_clk_top_eth1 = 186,
489 monitor_target_clk_top_ptp0 = 187,
490 monitor_target_clk_top_ptp1 = 188,
491 monitor_target_clk_top_ref0 = 189,
492 monitor_target_clk_top_ref1 = 190,
493 monitor_target_clk_top_ntmr0 = 191,
494 monitor_target_clk_top_ntmr1 = 192,
495 monitor_target_clk_top_sdxc0 = 193,
496 monitor_target_clk_top_sdxc1 = 194,
497 } monitor_target_t;
498
499 /**
500 * @brief Monitor work mode
501 */
502 typedef enum {
503 monitor_work_mode_compare = 0,
504 monitor_work_mode_record = 1,
505 } monitor_work_mode_t;
506
507 /**
508 * @brief Monitor accuracy
509 */
510 typedef enum {
511 monitor_accuracy_1khz = 0,
512 monitor_accuracy_1hz = 1,
513 } monitor_accuracy_t;
514
515 /**
516 * @brief Monitor reference clock source
517 */
518 typedef enum {
519 monitor_reference_32khz = 0,
520 monitor_reference_24mhz = 1,
521 } monitor_reference_t;
522
523 typedef enum {
524 cpu_event_flag_mask_reset = SYSCTL_CPU_LP_RESET_FLAG_MASK,
525 cpu_event_flag_mask_sleep = SYSCTL_CPU_LP_SLEEP_FLAG_MASK,
526 cpu_event_flag_mask_wake = SYSCTL_CPU_LP_WAKE_FLAG_MASK,
527 cpu_event_flag_mask_all = SYSCTL_CPU_LP_RESET_FLAG_MASK | SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK,
528 } cpu_event_flag_mask_t;
529
530 /**
531 * @brief Monitor config
532 */
533 typedef struct monitor_config {
534 uint8_t divide_by; /**< Divider to be used for OBS output to pads */
535 monitor_work_mode_t mode; /**< Monitor work mode */
536 monitor_accuracy_t accuracy; /**< Monitor reference accuracy */
537 monitor_reference_t reference; /**< Monitor reference clock source */
538 monitor_target_t target; /**< Monitor target */
539 bool start_measure; /**< Start flag */
540 bool enable_output; /**< Enable output to pads if true */
541 uint32_t high_limit; /**< Maximum frequency at compare mode */
542 uint32_t low_limit; /**< Minimum frequency at compare mode */
543 } monitor_config_t;
544
545 #ifdef __cplusplus
546 extern "C" {
547 #endif
548
549 /**
550 * @brief Check if monitor result is valid
551 *
552 * @param[in] ptr SYSCTL_Type base address
553 * @param[in] monitor_index specific monitor instance to be used
554 *
555 * @return true if it is valid
556 */
sysctl_monitor_result_is_valid(SYSCTL_Type * ptr,uint8_t monitor_index)557 static inline bool sysctl_monitor_result_is_valid(SYSCTL_Type *ptr, uint8_t monitor_index)
558 {
559 return SYSCTL_MONITOR_CONTROL_VALID_GET(ptr->MONITOR[monitor_index].CONTROL);
560 }
561
562 /**
563 * @brief Get target monitor instance result
564 *
565 * @param[in] ptr SYSCTL_Type base address
566 * @param[in] monitor_index specific monitor instance to be used
567 * @return value of monitor result measured
568 */
sysctl_monitor_get_current_result(SYSCTL_Type * ptr,uint8_t monitor_index)569 static inline uint32_t sysctl_monitor_get_current_result(SYSCTL_Type *ptr,
570 uint8_t monitor_index)
571 {
572 while (!sysctl_monitor_result_is_valid(ptr, monitor_index)) {
573 }
574 return ptr->MONITOR[monitor_index].CURRENT;
575 }
576
577 /**
578 * @brief Set work mode for target monitor instance
579 *
580 * @param[in] ptr SYSCTL_Type base address
581 * @param[in] monitor_index specific monitor instance to be used
582 * @param[in] mode monitor_work_mode_compare, monitor_work_mode_record
583 */
sysctl_monitor_set_work_mode(SYSCTL_Type * ptr,uint8_t monitor_index,monitor_work_mode_t mode)584 static inline void sysctl_monitor_set_work_mode(SYSCTL_Type *ptr,
585 uint8_t monitor_index,
586 monitor_work_mode_t mode)
587 {
588 ptr->MONITOR[monitor_index].CONTROL =
589 (ptr->MONITOR[monitor_index].CONTROL & ~SYSCTL_MONITOR_CONTROL_MODE_MASK)
590 | (SYSCTL_MONITOR_CONTROL_MODE_SET(mode));
591 }
592
593 /**
594 * @brief Set minimum frequency for target monitor instance
595 *
596 * @param[in] ptr SYSCTL_Type base address
597 * @param[in] monitor_index specific monitor instance to be used
598 * @param[in] limit measurement low limit
599 */
sysctl_monitor_set_limit_low(SYSCTL_Type * ptr,uint8_t monitor_index,uint32_t limit)600 static inline hpm_stat_t sysctl_monitor_set_limit_low(SYSCTL_Type *ptr,
601 uint8_t monitor_index,
602 uint32_t limit)
603 {
604 if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) {
605 return status_invalid_argument;
606 }
607 ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(limit);
608 return status_success;
609 }
610
611 /**
612 * @brief Set maximum frequency for target monitor instance
613 *
614 * @param[in] ptr SYSCTL_Type base address
615 * @param[in] monitor_index specific monitor instance to be used
616 * @param[in] limit measurement high limit
617 */
sysctl_monitor_set_limit_high(SYSCTL_Type * ptr,uint8_t monitor_index,uint32_t limit)618 static inline hpm_stat_t sysctl_monitor_set_limit_high(SYSCTL_Type *ptr,
619 uint8_t monitor_index,
620 uint32_t limit)
621 {
622 if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) {
623 return status_invalid_argument;
624 }
625 ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(limit);
626 return status_success;
627 }
628
629 /**
630 * @brief Set frequency limit for target monitor instance
631 *
632 * @param[in] ptr SYSCTL_Type base address
633 * @param[in] monitor_index specific monitor instance to be used
634 * @param[in] limit_high measurement high limit
635 * @param[in] limit_low measurement low limit
636 */
sysctl_monitor_set_limit(SYSCTL_Type * ptr,uint8_t monitor_index,uint32_t limit_high,uint32_t limit_low)637 static inline hpm_stat_t sysctl_monitor_set_limit(SYSCTL_Type *ptr,
638 uint8_t monitor_index,
639 uint32_t limit_high,
640 uint32_t limit_low)
641 {
642 if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) {
643 return status_invalid_argument;
644 }
645 ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(limit_high);
646 ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(limit_low);
647 return status_success;
648 }
649
650 /**
651 * @brief Get maximum frequency for target monitor instance
652 *
653 * @param[in] ptr SYSCTL_Type base address
654 * @param[in] monitor_index specific monitor instance to be used
655 * @return current high limit value
656 */
sysctl_monitor_get_limit_high(SYSCTL_Type * ptr,uint32_t monitor_index)657 static inline uint32_t sysctl_monitor_get_limit_high(SYSCTL_Type *ptr, uint32_t monitor_index)
658 {
659 return SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(ptr->MONITOR[monitor_index].HIGH_LIMIT);
660 }
661
662 /**
663 * @brief Get minimum frequency for target monitor instance
664 *
665 * @param[in] ptr SYSCTL_Type base address
666 * @param[in] monitor_index specific monitor instance to be used
667 * @return current low limit value
668 */
sysctl_monitor_get_limit_low(SYSCTL_Type * ptr,uint32_t monitor_index)669 static inline uint32_t sysctl_monitor_get_limit_low(SYSCTL_Type *ptr, uint32_t monitor_index)
670 {
671 return SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(ptr->MONITOR[monitor_index].LOW_LIMIT);
672 }
673
674 /**
675 * @brief Measure specific target frequency
676 *
677 * @param[in] ptr SYSCTL_Type base address
678 * @param[in] monitor_index specific monitor instance to be used
679 * @param[in] target monitor target to be measured
680 * @param[in] enable_output enable clock obs output
681 * @return frequency of monitor target measured
682 */
683 uint32_t sysctl_monitor_measure_frequency(SYSCTL_Type *ptr,
684 uint8_t monitor_index,
685 monitor_target_t target,
686 bool enable_output);
687
688 /**
689 * @brief Link current CPU core its own group
690 *
691 * Once it is linked, peripherals state in that group will keep on as long as this core is not in low power mode
692 *
693 * @param[in] ptr SYSCTL_Type base address
694 * @param[in] cpu_index cpu index to enable its own affiliated group
695 */
sysctl_set_enable_cpu_affiliate(SYSCTL_Type * ptr,uint8_t cpu_index)696 static inline void sysctl_set_enable_cpu_affiliate(SYSCTL_Type *ptr, uint8_t cpu_index)
697 {
698 ptr->AFFILIATE[cpu_index].SET = 1 << cpu_index;
699 }
700
701 /**
702 * @brief Unlink current CPU core with its own group
703 *
704 * @param[in] ptr SYSCTL_Type base address
705 * @param[in] cpu_index cpu index to enable its own affiliated group
706 */
sysctl_set_disable_cpu_affiliate(SYSCTL_Type * ptr,uint8_t cpu_index)707 static inline void sysctl_set_disable_cpu_affiliate(SYSCTL_Type *ptr, uint8_t cpu_index)
708 {
709 ptr->AFFILIATE[cpu_index].CLEAR = 1 << cpu_index;
710 }
711
712 /**
713 * @brief Check if any resource is busy
714 *
715 * @param[in] ptr SYSCTL_Type base address
716 * @return true if any resource is busy
717 */
sysctl_resource_any_is_busy(SYSCTL_Type * ptr)718 static inline bool sysctl_resource_any_is_busy(SYSCTL_Type *ptr)
719 {
720 return ptr->RESOURCE[0] & SYSCTL_RESOURCE_GLB_BUSY_MASK;
721 }
722
723 /**
724 * @brief Check if specific target is busy
725 *
726 * @param[in] ptr SYSCTL_Type base address
727 * @param[in] resource target resource index
728 * @return true if target resource is busy
729 */
sysctl_resource_target_is_busy(SYSCTL_Type * ptr,sysctl_resource_t resource)730 static inline bool sysctl_resource_target_is_busy(SYSCTL_Type *ptr, sysctl_resource_t resource)
731 {
732 return ptr->RESOURCE[resource] & SYSCTL_RESOURCE_LOC_BUSY_MASK;
733 }
734
735 /**
736 * @brief Set target mode
737 *
738 * @param[in] ptr SYSCTL_Type base address
739 * @param[in] resource target resource index
740 * @param[in] mode target resource mode
741 */
sysctl_resource_target_set_mode(SYSCTL_Type * ptr,sysctl_resource_t resource,sysctl_resource_mode_t mode)742 static inline void sysctl_resource_target_set_mode(SYSCTL_Type *ptr,
743 sysctl_resource_t resource,
744 sysctl_resource_mode_t mode)
745 {
746 ptr->RESOURCE[resource] =
747 (ptr->RESOURCE[resource] & ~SYSCTL_RESOURCE_MODE_MASK) |
748 SYSCTL_RESOURCE_MODE_SET(mode);
749 }
750
751 /**
752 * @brief Get target mode
753 *
754 * @param[in] ptr SYSCTL_Type base address
755 * @param[in] resource target resource index
756 * @return target resource mode
757 */
sysctl_resource_target_get_mode(SYSCTL_Type * ptr,sysctl_resource_t resource)758 static inline uint8_t sysctl_resource_target_get_mode(SYSCTL_Type *ptr,
759 sysctl_resource_t resource)
760 {
761 return SYSCTL_RESOURCE_MODE_GET(ptr->RESOURCE[resource]);
762 }
763
764 /**
765 * @brief Disable resource retention when specific CPU enters stop mode
766 *
767 * @param[in] ptr SYSCTL_Type base address
768 * @param[in] cpu_index cpu index
769 * @param[in] mask bit mask to clear
770 */
sysctl_clear_cpu_lp_retention_with_mask(SYSCTL_Type * ptr,uint8_t cpu_index,uint32_t mask)771 static inline void sysctl_clear_cpu_lp_retention_with_mask(SYSCTL_Type *ptr,
772 uint8_t cpu_index,
773 uint32_t mask)
774 {
775 ptr->RETENTION[cpu_index].CLEAR = mask;
776 }
777
778 /**
779 * @brief Disable resource retention when CPU0 enters stop mode
780 *
781 * @param[in] ptr SYSCTL_Type base address
782 * @param[in] mask bit mask to clear
783 */
sysctl_clear_cpu0_lp_retention_with_mask(SYSCTL_Type * ptr,uint32_t mask)784 static inline void sysctl_clear_cpu0_lp_retention_with_mask(SYSCTL_Type *ptr,
785 uint32_t mask)
786 {
787 sysctl_clear_cpu_lp_retention_with_mask(ptr, 0, mask);
788 }
789
790 /**
791 * @brief Disable resource retention when CPU1 enters stop mode
792 *
793 * @param[in] ptr SYSCTL_Type base address
794 * @param[in] mask bit mask to clear
795 */
sysctl_clear_cpu1_lp_retention_with_mask(SYSCTL_Type * ptr,uint32_t mask)796 static inline void sysctl_clear_cpu1_lp_retention_with_mask(SYSCTL_Type *ptr,
797 uint32_t mask)
798 {
799 sysctl_clear_cpu_lp_retention_with_mask(ptr, 1, mask);
800 }
801
802 /**
803 * @brief Enable resource retention when specific CPU enters stop mode
804 *
805 * @param[in] ptr SYSCTL_Type base address
806 * @param[in] cpu_index cpu index
807 * @param[in] mask bit mask to set
808 */
sysctl_set_cpu_lp_retention_with_mask(SYSCTL_Type * ptr,uint8_t cpu_index,uint32_t mask)809 static inline void sysctl_set_cpu_lp_retention_with_mask(SYSCTL_Type *ptr,
810 uint8_t cpu_index,
811 uint32_t mask)
812 {
813 ptr->RETENTION[cpu_index].SET = mask;
814 }
815
816 /**
817 * @brief Enable resource retention when CPU0 enters stop mode
818 *
819 * @param[in] ptr SYSCTL_Type base address
820 * @param[in] mask bit mask to set
821 */
sysctl_set_cpu0_lp_retention_with_mask(SYSCTL_Type * ptr,uint32_t mask)822 static inline void sysctl_set_cpu0_lp_retention_with_mask(SYSCTL_Type *ptr,
823 uint32_t mask)
824 {
825 sysctl_set_cpu_lp_retention_with_mask(ptr, 0, mask);
826 }
827
828 /**
829 * @brief Enable resource retention when CPU1 enters stop mode
830 *
831 * @param[in] ptr SYSCTL_Type base address
832 * @param[in] mask bit mask to set
833 */
sysctl_set_cpu1_lp_retention_with_mask(SYSCTL_Type * ptr,uint32_t mask)834 static inline void sysctl_set_cpu1_lp_retention_with_mask(SYSCTL_Type *ptr,
835 uint32_t mask)
836 {
837 sysctl_set_cpu_lp_retention_with_mask(ptr, 1, mask);
838 }
839
840 /**
841 * @brief Enable resource retention when specific CPU enters stop mode
842 *
843 * @param[in] ptr SYSCTL_Type base address
844 * @param[in] cpu_index cpu index
845 * @param[in] value value to be set
846 */
sysctl_set_cpu_lp_retention(SYSCTL_Type * ptr,uint8_t cpu_index,uint32_t value)847 static inline void sysctl_set_cpu_lp_retention(SYSCTL_Type *ptr,
848 uint8_t cpu_index,
849 uint32_t value)
850 {
851 ptr->RETENTION[cpu_index].VALUE = value;
852 }
853
854 /**
855 * @brief Enable resource retention when CPU0 enters stop mode
856 *
857 * @param[in] ptr SYSCTL_Type base address
858 * @param[in] value value to be set
859 */
sysctl_set_cpu0_lp_retention(SYSCTL_Type * ptr,uint32_t value)860 static inline void sysctl_set_cpu0_lp_retention(SYSCTL_Type *ptr, uint32_t value)
861 {
862 sysctl_set_cpu_lp_retention(ptr, 0, value);
863 }
864
865 /**
866 * @brief Enable resource retention when CPU1 enters stop mode
867 *
868 * @param[in] ptr SYSCTL_Type base address
869 * @param[in] value value to be set
870 */
sysctl_set_cpu1_lp_retention(SYSCTL_Type * ptr,uint32_t value)871 static inline void sysctl_set_cpu1_lp_retention(SYSCTL_Type *ptr, uint32_t value)
872 {
873 sysctl_set_cpu_lp_retention(ptr, 1, value);
874 }
875
876 /**
877 * @brief Retain target domain for specific CPU
878 *
879 * @param[in] ptr SYSCTL_Type base address
880 * @param[in] cpu_index CPU index
881 * @param[in] domain target domain power to be retained
882 * @param[in] retain_mem set true to retain memory/register of target domain
883 */
sysctl_set_cpu_lp_retain_domain(SYSCTL_Type * ptr,uint8_t cpu_index,sysctl_retention_domain_t domain,bool retain_mem)884 static inline void sysctl_set_cpu_lp_retain_domain(SYSCTL_Type *ptr,
885 uint8_t cpu_index,
886 sysctl_retention_domain_t domain,
887 bool retain_mem)
888 {
889 uint8_t set_mask = 0x1;
890 if (domain < sysctl_retention_domain_xtal24m) {
891 set_mask = retain_mem ? 0x3 : 0x1;
892 }
893 ptr->RETENTION[cpu_index].SET = (set_mask << domain);
894 }
895
896 /**
897 * @brief Retain target domain for specific CPU0
898 *
899 * @param[in] ptr SYSCTL_Type base address
900 * @param[in] domain target domain power to be retained
901 * @param[in] retain_mem set true to retain memory/register of target domain
902 */
sysctl_set_cpu0_lp_retain_domain(SYSCTL_Type * ptr,sysctl_retention_domain_t domain,bool retain_mem)903 static inline void sysctl_set_cpu0_lp_retain_domain(SYSCTL_Type *ptr,
904 sysctl_retention_domain_t domain,
905 bool retain_mem)
906 {
907 sysctl_set_cpu_lp_retain_domain(ptr, 0, domain, retain_mem);
908 }
909
910 /**
911 * @brief Retain target domain for specific CPU
912 *
913 * @param[in] ptr SYSCTL_Type base address
914 * @param[in] domain target domain power to be retained
915 * @param[in] retain_mem set true to retain memory/register of target domain
916 */
sysctl_set_cpu1_lp_retain_domain(SYSCTL_Type * ptr,sysctl_retention_domain_t domain,bool retain_mem)917 static inline void sysctl_set_cpu1_lp_retain_domain(SYSCTL_Type *ptr,
918 sysctl_retention_domain_t domain,
919 bool retain_mem)
920 {
921 sysctl_set_cpu_lp_retain_domain(ptr, 1, domain, retain_mem);
922 }
923
924 /**
925 * @brief Check if any clock is busy
926 *
927 * @param[in] ptr SYSCTL_Type base address
928 * @return true if any clock is busy
929 */
sysctl_clock_any_is_busy(SYSCTL_Type * ptr)930 static inline bool sysctl_clock_any_is_busy(SYSCTL_Type *ptr)
931 {
932 return ptr->CLOCK[0] & SYSCTL_CLOCK_GLB_BUSY_MASK;
933 }
934
935 /**
936 * @brief Check if target clock is busy
937 *
938 * @param[in] ptr SYSCTL_Type base address
939 * @param[in] clock target clock
940 * @return true if target clock is busy
941 */
sysctl_clock_target_is_busy(SYSCTL_Type * ptr,uint32_t clock)942 static inline bool sysctl_clock_target_is_busy(SYSCTL_Type *ptr,
943 uint32_t clock)
944 {
945 return ptr->CLOCK[clock] & SYSCTL_CLOCK_LOC_BUSY_MASK;
946 }
947
948 /**
949 * @brief Set clock preset
950 *
951 * @param[in] ptr SYSCTL_Type base address
952 * @param[in] preset preset
953 */
sysctl_clock_set_preset(SYSCTL_Type * ptr,sysctl_preset_t preset)954 static inline void sysctl_clock_set_preset(SYSCTL_Type *ptr,
955 sysctl_preset_t preset)
956 {
957 ptr->GLOBAL00 = (ptr->GLOBAL00 & ~SYSCTL_GLOBAL00_PRESET_MASK)
958 | SYSCTL_GLOBAL00_PRESET_SET(preset);
959 }
960
961 /**
962 * @brief Check if target reset domain wakeup status
963 *
964 * @param[in] ptr SYSCTL_Type base address
965 * @param[in] domain target domain to be checked
966 * @return true if target domain was taken wakeup reset
967 */
sysctl_reset_check_target_domain_wakeup_flag(SYSCTL_Type * ptr,sysctl_reset_domain_t domain)968 static inline bool sysctl_reset_check_target_domain_wakeup_flag(SYSCTL_Type *ptr,
969 sysctl_reset_domain_t domain)
970 {
971 return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK;
972 }
973
974 /**
975 * @brief Clear target reset domain wakeup status
976 *
977 * @param[in] ptr SYSCTL_Type base address
978 * @param[in] domain target domain to be checked
979 */
sysctl_reset_clear_target_domain_wakeup_flag(SYSCTL_Type * ptr,sysctl_reset_domain_t domain)980 static inline void sysctl_reset_clear_target_domain_wakeup_flag(SYSCTL_Type *ptr,
981 sysctl_reset_domain_t domain)
982 {
983 ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK;
984 }
985
986 /**
987 * @brief Clear target reset domain reset status
988 *
989 * @param[in] ptr SYSCTL_Type base address
990 * @param[in] domain target domain to be checked
991 * @return true if target domain was taken reset
992 */
sysctl_reset_check_target_domain_flag(SYSCTL_Type * ptr,sysctl_reset_domain_t domain)993 static inline bool sysctl_reset_check_target_domain_flag(SYSCTL_Type *ptr,
994 sysctl_reset_domain_t domain)
995 {
996 return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_MASK;
997 }
998
999 /**
1000 * @brief Clear target reset domain reset status
1001 *
1002 * @param[in] ptr SYSCTL_Type base address
1003 * @param[in] domain target domain to be checked
1004 */
sysctl_reset_clear_target_domain_flag(SYSCTL_Type * ptr,sysctl_reset_domain_t domain)1005 static inline void sysctl_reset_clear_target_domain_flag(SYSCTL_Type *ptr,
1006 sysctl_reset_domain_t domain)
1007 {
1008 ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK;
1009 }
1010
1011 /**
1012 * @brief Clear target reset domain for all reset status
1013 *
1014 * @param[in] ptr SYSCTL_Type base address
1015 * @param[in] domain target domain to be checked
1016 */
sysctl_reset_clear_target_domain_all_flags(SYSCTL_Type * ptr,sysctl_reset_domain_t domain)1017 static inline void sysctl_reset_clear_target_domain_all_flags(SYSCTL_Type *ptr,
1018 sysctl_reset_domain_t domain)
1019 {
1020 ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK | SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK;
1021 }
1022
1023 /**
1024 * @brief Get target CPU wakeup source status
1025 *
1026 * @param[in] ptr SYSCTL_Type base address
1027 * @param[in] cpu_index CPU index
1028 * @param[in] status_index wakeup status index 0 - 7
1029 * @return wakeup source status mask
1030 */
sysctl_get_wakeup_source_status(SYSCTL_Type * ptr,uint8_t cpu_index,uint8_t status_index)1031 static inline uint32_t sysctl_get_wakeup_source_status(SYSCTL_Type *ptr,
1032 uint8_t cpu_index,
1033 uint8_t status_index)
1034 {
1035 return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index];
1036 }
1037
1038 /**
1039 * @brief Get target CPU0 wakeup source status
1040 *
1041 * @param[in] ptr SYSCTL_Type base address
1042 * @param[in] status_index wakeup status index 0 - 7
1043 * @return wakeup source status mask
1044 */
sysctl_get_cpu0_wakeup_source_status(SYSCTL_Type * ptr,uint8_t status_index)1045 static inline uint32_t sysctl_get_cpu0_wakeup_source_status(SYSCTL_Type *ptr,
1046 uint8_t status_index)
1047 {
1048 return sysctl_get_wakeup_source_status(ptr, 0, status_index);
1049 }
1050
1051 /**
1052 * @brief Get target CPU1 wakeup source status
1053 *
1054 * @param[in] ptr SYSCTL_Type base address
1055 * @param[in] status_index wakeup status index 0 - 7
1056 * @return wakeup source status mask
1057 */
sysctl_get_cpu1_wakeup_source_status(SYSCTL_Type * ptr,uint8_t status_index)1058 static inline uint32_t sysctl_get_cpu1_wakeup_source_status(SYSCTL_Type *ptr,
1059 uint8_t status_index)
1060 {
1061 return sysctl_get_wakeup_source_status(ptr, 1, status_index);
1062 }
1063
1064 /**
1065 * @brief Check wakeup source status with mask
1066 *
1067 * @param[in] ptr SYSCTL_Type base address
1068 * @param[in] cpu_index CPU index
1069 * @param[in] status_index wakeup status index 0 - 7
1070 * @param[in] mask expected status mask
1071 * @return wakeup status according to given bit mask
1072 */
1073 static inline
sysctl_check_wakeup_source_status_with_mask(SYSCTL_Type * ptr,uint8_t cpu_index,uint8_t status_index,uint32_t mask)1074 uint32_t sysctl_check_wakeup_source_status_with_mask(SYSCTL_Type *ptr,
1075 uint8_t cpu_index,
1076 uint8_t status_index,
1077 uint32_t mask)
1078 {
1079 return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index] & mask;
1080 }
1081
1082 /**
1083 * @brief Check CPU0 wakeup source status with mask
1084 *
1085 * @param[in] ptr SYSCTL_Type base address
1086 * @param[in] status_index wakeup status index 0 - 7
1087 * @param[in] mask expected status mask
1088 * @return wakeup status according to given bit mask
1089 */
1090 static inline
sysctl_check_cpu0_wakeup_source_status_with_mask(SYSCTL_Type * ptr,uint8_t status_index,uint32_t mask)1091 uint32_t sysctl_check_cpu0_wakeup_source_status_with_mask(SYSCTL_Type *ptr,
1092 uint8_t status_index,
1093 uint32_t mask)
1094 {
1095 return sysctl_check_wakeup_source_status_with_mask(ptr, 0, status_index, mask);
1096 }
1097
1098 /**
1099 * @brief Check CPU1 wakeup source status with mask
1100 *
1101 * @param[in] ptr SYSCTL_Type base address
1102 * @param[in] status_index wakeup status index 0 - 7
1103 * @param[in] mask expected status mask
1104 * @return wakeup status according to given bit mask
1105 */
1106 static inline
sysctl_check_cpu1_wakeup_source_status_with_mask(SYSCTL_Type * ptr,uint8_t status_index,uint32_t mask)1107 uint32_t sysctl_check_cpu1_wakeup_source_status_with_mask(SYSCTL_Type *ptr,
1108 uint8_t status_index,
1109 uint32_t mask)
1110 {
1111 return sysctl_check_wakeup_source_status_with_mask(ptr, 1, status_index, mask);
1112 }
1113
1114 /**
1115 * @brief Enable wakeup source status with mask
1116 *
1117 * @param[in] ptr SYSCTL_Type base address
1118 * @param[in] cpu_index CPU index
1119 * @param[in] enable_index wakeup enable index 0 - 7
1120 * @param[in] mask expected status mask
1121 */
1122 static inline
sysctl_enable_wakeup_source_with_mask(SYSCTL_Type * ptr,uint8_t cpu_index,uint8_t enable_index,uint32_t mask)1123 void sysctl_enable_wakeup_source_with_mask(SYSCTL_Type *ptr,
1124 uint8_t cpu_index,
1125 uint8_t enable_index,
1126 uint32_t mask)
1127 {
1128 ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] |= mask;
1129 }
1130
1131 /**
1132 * @brief Enable CPU0 wakeup source status with mask
1133 *
1134 * @param[in] ptr SYSCTL_Type base address
1135 * @param[in] enable_index wakeup enable index 0 - 7
1136 * @param[in] mask expected status mask
1137 */
sysctl_enable_cpu0_wakeup_source_with_mask(SYSCTL_Type * ptr,uint8_t enable_index,uint32_t mask)1138 static inline void sysctl_enable_cpu0_wakeup_source_with_mask(SYSCTL_Type *ptr,
1139 uint8_t enable_index,
1140 uint32_t mask)
1141 {
1142 ptr->CPU[0].WAKEUP_ENABLE[enable_index] |= mask;
1143 }
1144
1145 /**
1146 * @brief Enable CPU1 wakeup source status with mask
1147 *
1148 * @param[in] ptr SYSCTL_Type base address
1149 * @param[in] enable_index wakeup enable index 0 - 7
1150 * @param[in] mask expected status mask
1151 */
sysctl_enable_cpu1_wakeup_source_with_mask(SYSCTL_Type * ptr,uint8_t enable_index,uint32_t mask)1152 static inline void sysctl_enable_cpu1_wakeup_source_with_mask(SYSCTL_Type *ptr,
1153 uint8_t enable_index,
1154 uint32_t mask)
1155 {
1156 ptr->CPU[1].WAKEUP_ENABLE[enable_index] |= mask;
1157 }
1158
1159 /**
1160 * @brief Disable wakeup source status with mask
1161 *
1162 * @param[in] ptr SYSCTL_Type base address
1163 * @param[in] cpu_index CPU index
1164 * @param[in] enable_index wakeup enable index 0 - 7
1165 * @param[in] mask expected status mask
1166 */
1167 static inline
sysctl_disable_wakeup_source_with_mask(SYSCTL_Type * ptr,uint8_t cpu_index,uint8_t enable_index,uint32_t mask)1168 void sysctl_disable_wakeup_source_with_mask(SYSCTL_Type *ptr,
1169 uint8_t cpu_index,
1170 uint8_t enable_index,
1171 uint32_t mask)
1172 {
1173 ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] &= ~mask;
1174 }
1175
1176 /**
1177 * @brief Disable CPU0 wakeup source status with mask
1178 *
1179 * @param[in] ptr SYSCTL_Type base address
1180 * @param[in] enable_index wakeup enable index 0 - 7
1181 * @param[in] mask expected status mask
1182 */
sysctl_disable_cpu0_wakeup_source_with_mask(SYSCTL_Type * ptr,uint8_t enable_index,uint32_t mask)1183 static inline void sysctl_disable_cpu0_wakeup_source_with_mask(SYSCTL_Type *ptr,
1184 uint8_t enable_index,
1185 uint32_t mask)
1186 {
1187 sysctl_disable_wakeup_source_with_mask(ptr, 0, enable_index, mask);
1188 }
1189
1190
1191 /**
1192 * @brief Disable CPU1 wakeup source status with mask
1193 *
1194 * @param[in] ptr SYSCTL_Type base address
1195 * @param[in] enable_index wakeup enable index 0 - 7
1196 * @param[in] mask expected status mask
1197 */
sysctl_disable_cpu1_wakeup_source_with_mask(SYSCTL_Type * ptr,uint8_t enable_index,uint32_t mask)1198 static inline void sysctl_disable_cpu1_wakeup_source_with_mask(SYSCTL_Type *ptr,
1199 uint8_t enable_index,
1200 uint32_t mask)
1201 {
1202 sysctl_disable_wakeup_source_with_mask(ptr, 1, enable_index, mask);
1203 }
1204
1205 /**
1206 * @brief Disable wakeup source status with irq
1207 *
1208 * @param[in] ptr SYSCTL_Type base address
1209 * @param[in] cpu_index CPU index
1210 * @param[in] irq_num irq number to be disabled as wakeup source
1211 */
sysctl_disable_wakeup_source_with_irq(SYSCTL_Type * ptr,uint8_t cpu_index,uint16_t irq_num)1212 static inline void sysctl_disable_wakeup_source_with_irq(SYSCTL_Type *ptr,
1213 uint8_t cpu_index,
1214 uint16_t irq_num)
1215 {
1216 ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num >> 2] &= ~(1UL << (irq_num % 32));
1217 }
1218
1219 /**
1220 * @brief Disable CPU0 wakeup source status with irq
1221 *
1222 * @param[in] ptr SYSCTL_Type base address
1223 * @param[in] irq_num irq number to be disabled as wakeup source
1224 */
sysctl_disable_cpu0_wakeup_source_with_irq(SYSCTL_Type * ptr,uint16_t irq_num)1225 static inline void sysctl_disable_cpu0_wakeup_source_with_irq(SYSCTL_Type *ptr,
1226 uint16_t irq_num)
1227 {
1228 sysctl_disable_wakeup_source_with_irq(ptr, 0, irq_num);
1229 }
1230
1231
1232 /**
1233 * @brief Disable CPU1 wakeup source status with irq
1234 *
1235 * @param[in] ptr SYSCTL_Type base address
1236 * @param[in] irq_num irq number to be disabled as wakeup source
1237 */
sysctl_disable_cpu1_wakeup_source_with_irq(SYSCTL_Type * ptr,uint16_t irq_num)1238 static inline void sysctl_disable_cpu1_wakeup_source_with_irq(SYSCTL_Type *ptr,
1239 uint16_t irq_num)
1240 {
1241 sysctl_disable_wakeup_source_with_irq(ptr, 1, irq_num);
1242 }
1243
1244 /**
1245 * @brief Enable wakeup source status with irq
1246 *
1247 * @param[in] ptr SYSCTL_Type base address
1248 * @param[in] cpu_index CPU index
1249 * @param[in] irq_num irq number to be set as wakeup source
1250 */
sysctl_enable_wakeup_source_with_irq(SYSCTL_Type * ptr,uint8_t cpu_index,uint16_t irq_num)1251 static inline void sysctl_enable_wakeup_source_with_irq(SYSCTL_Type *ptr,
1252 uint8_t cpu_index,
1253 uint16_t irq_num)
1254 {
1255 ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num / 32] |= 1UL << (irq_num & 0x1F);
1256 }
1257
1258 /**
1259 * @brief Enable CPU0 wakeup source status with irq
1260 *
1261 * @param[in] ptr SYSCTL_Type base address
1262 * @param[in] irq_num irq number to be set as wakeup source
1263 */
sysctl_enable_cpu0_wakeup_source_with_irq(SYSCTL_Type * ptr,uint16_t irq_num)1264 static inline void sysctl_enable_cpu0_wakeup_source_with_irq(SYSCTL_Type *ptr,
1265 uint16_t irq_num)
1266 {
1267 sysctl_enable_wakeup_source_with_irq(ptr, 0, irq_num);
1268 }
1269
1270 /**
1271 * @brief Enable CPU1 wakeup source status with irq
1272 *
1273 * @param[in] ptr SYSCTL_Type base address
1274 * @param[in] irq_num irq number to be set as wakeup source
1275 */
sysctl_enable_cpu1_wakeup_source_with_irq(SYSCTL_Type * ptr,uint16_t irq_num)1276 static inline void sysctl_enable_cpu1_wakeup_source_with_irq(SYSCTL_Type *ptr,
1277 uint16_t irq_num)
1278 {
1279 sysctl_enable_wakeup_source_with_irq(ptr, 1, irq_num);
1280 }
1281
1282 /**
1283 * @brief Lock CPU gpr with mask
1284 *
1285 * @param[in] ptr SYSCTL_Type base address
1286 * @param[in] cpu_index CPU index
1287 * @param[in] gpr_mask bit mask of gpr registers to be locked
1288 */
sysctl_cpu_lock_gpr_with_mask(SYSCTL_Type * ptr,uint8_t cpu_index,uint16_t gpr_mask)1289 static inline void sysctl_cpu_lock_gpr_with_mask(SYSCTL_Type *ptr,
1290 uint8_t cpu_index,
1291 uint16_t gpr_mask)
1292 {
1293 ptr->CPU[cpu_index].LOCK |= SYSCTL_CPU_LOCK_GPR_SET(gpr_mask);
1294 }
1295
1296
1297 /**
1298 * @brief Lock CPU0 gpr with mask
1299 *
1300 * @param[in] ptr SYSCTL_Type base address
1301 * @param[in] gpr_mask bit mask of gpr registers to be locked
1302 */
sysctl_cpu0_lock_gpr_with_mask(SYSCTL_Type * ptr,uint16_t gpr_mask)1303 static inline void sysctl_cpu0_lock_gpr_with_mask(SYSCTL_Type *ptr,
1304 uint16_t gpr_mask)
1305 {
1306 sysctl_cpu_lock_gpr_with_mask(ptr, 0, gpr_mask);
1307 }
1308
1309 /**
1310 * @brief Lock CPU1 gpr with mask
1311 *
1312 * @param[in] ptr SYSCTL_Type base address
1313 * @param[in] gpr_mask bit mask of gpr registers to be locked
1314 */
sysctl_cpu1_lock_gpr_with_mask(SYSCTL_Type * ptr,uint16_t gpr_mask)1315 static inline void sysctl_cpu1_lock_gpr_with_mask(SYSCTL_Type *ptr,
1316 uint16_t gpr_mask)
1317 {
1318 sysctl_cpu_lock_gpr_with_mask(ptr, 1, gpr_mask);
1319 }
1320
1321 /**
1322 * @brief Lock CPU lock
1323 *
1324 * @param[in] ptr SYSCTL_Type base address
1325 * @param[in] cpu_index CPU index
1326 */
sysctl_cpu_lock(SYSCTL_Type * ptr,uint8_t cpu_index)1327 static inline void sysctl_cpu_lock(SYSCTL_Type *ptr, uint8_t cpu_index)
1328 {
1329 ptr->CPU[cpu_index].LOCK |= SYSCTL_CPU_LOCK_LOCK_MASK;
1330 }
1331
1332 /**
1333 * @brief Lock CPU0 lock
1334 *
1335 * @param[in] ptr SYSCTL_Type base address
1336 */
sysctl_cpu0_lock(SYSCTL_Type * ptr)1337 static inline void sysctl_cpu0_lock(SYSCTL_Type *ptr)
1338 {
1339 sysctl_cpu_lock(ptr, 0);
1340 }
1341
1342 /**
1343 * @brief Lock CPU1 lock
1344 *
1345 * @param[in] ptr SYSCTL_Type base address
1346 */
sysctl_cpu1_lock(SYSCTL_Type * ptr)1347 static inline void sysctl_cpu1_lock(SYSCTL_Type *ptr)
1348 {
1349 sysctl_cpu_lock(ptr, 1);
1350 }
1351
1352 /**
1353 * @brief Set CPU low power mode
1354 *
1355 * @param[in] ptr SYSCTL_Type base address
1356 * @param[in] cpu_index CPU index
1357 * @param[in] mode target mode to set
1358 */
sysctl_set_cpu_lp_mode(SYSCTL_Type * ptr,uint8_t cpu_index,cpu_lp_mode_t mode)1359 static inline void sysctl_set_cpu_lp_mode(SYSCTL_Type *ptr, uint8_t cpu_index, cpu_lp_mode_t mode)
1360 {
1361 ptr->CPU[cpu_index].LP = (ptr->CPU[cpu_index].LP & ~(SYSCTL_CPU_LP_MODE_MASK)) | (mode);
1362 }
1363
1364 /**
1365 * @brief Set CPU0 low power mode
1366 *
1367 * @param[in] ptr SYSCTL_Type base address
1368 * @param[in] mode target mode to set
1369 */
sysctl_set_cpu0_lp_mode(SYSCTL_Type * ptr,cpu_lp_mode_t mode)1370 static inline void sysctl_set_cpu0_lp_mode(SYSCTL_Type *ptr, cpu_lp_mode_t mode)
1371 {
1372 sysctl_set_cpu_lp_mode(ptr, 0, mode);
1373 }
1374
1375 /**
1376 * @brief Set CPU1 low power mode
1377 *
1378 * @param[in] ptr SYSCTL_Type base address
1379 * @param[in] mode target mode to set
1380 */
sysctl_set_cpu1_lp_mode(SYSCTL_Type * ptr,cpu_lp_mode_t mode)1381 static inline void sysctl_set_cpu1_lp_mode(SYSCTL_Type *ptr, cpu_lp_mode_t mode)
1382 {
1383 sysctl_set_cpu_lp_mode(ptr, 1, mode);
1384 }
1385
1386 /**
1387 * @brief Clear CPU event flags
1388 *
1389 * @param[in] ptr SYSCTL_Type base address
1390 * @param[in] cpu_index CPU index
1391 * @param[in] flags flag mask to be cleared
1392 */
sysctl_clear_cpu_flags(SYSCTL_Type * ptr,uint8_t cpu_index,cpu_event_flag_mask_t flags)1393 static inline void sysctl_clear_cpu_flags(SYSCTL_Type *ptr, uint8_t cpu_index, cpu_event_flag_mask_t flags)
1394 {
1395 ptr->CPU[cpu_index].LP |= ((SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK | SYSCTL_CPU_LP_RESET_FLAG_MASK) & flags);
1396 }
1397
1398 /**
1399 * @brief Clear CPU0 event flags
1400 *
1401 * @param[in] ptr SYSCTL_Type base address
1402 * @param[in] flags flag mask to be cleared
1403 */
sysctl_clear_cpu0_flags(SYSCTL_Type * ptr,cpu_event_flag_mask_t flags)1404 static inline void sysctl_clear_cpu0_flags(SYSCTL_Type *ptr, cpu_event_flag_mask_t flags)
1405 {
1406 sysctl_clear_cpu_flags(ptr, 0, flags);
1407 }
1408
1409 /**
1410 * @brief Clear CPU1 event flags
1411 *
1412 * @param[in] ptr SYSCTL_Type base address
1413 * @param[in] flags flag mask to be cleared
1414 */
sysctl_clear_cpu1_flags(SYSCTL_Type * ptr,cpu_event_flag_mask_t flags)1415 static inline void sysctl_clear_cpu1_flags(SYSCTL_Type *ptr, cpu_event_flag_mask_t flags)
1416 {
1417 sysctl_clear_cpu_flags(ptr, 1, flags);
1418 }
1419
1420 /**
1421 * @brief Get CPU event flags
1422 *
1423 * @param[in] ptr SYSCTL_Type base address
1424 * @param[in] cpu_index CPU index
1425 * @retval event flag mask
1426 */
sysctl_get_cpu_flags(SYSCTL_Type * ptr,uint8_t cpu_index)1427 static inline uint32_t sysctl_get_cpu_flags(SYSCTL_Type *ptr, uint8_t cpu_index)
1428 {
1429 return ptr->CPU[cpu_index].LP & (SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK | SYSCTL_CPU_LP_RESET_FLAG_MASK);
1430 }
1431
1432 /**
1433 * @brief Get CPU0 event flags
1434 *
1435 * @param[in] ptr SYSCTL_Type base address
1436 * @retval event flag mask
1437 */
sysctl_get_cpu0_flags(SYSCTL_Type * ptr)1438 static inline uint32_t sysctl_get_cpu0_flags(SYSCTL_Type *ptr)
1439 {
1440 return sysctl_get_cpu_flags(ptr, 0);
1441 }
1442
1443 /**
1444 * @brief Get CPU1 event flags
1445 *
1446 * @param[in] ptr SYSCTL_Type base address
1447 * @retval event flag mask
1448 */
sysctl_get_cpu1_flags(SYSCTL_Type * ptr)1449 static inline uint32_t sysctl_get_cpu1_flags(SYSCTL_Type *ptr)
1450 {
1451 return sysctl_get_cpu_flags(ptr, 1);
1452 }
1453
1454 /**
1455 * @brief Release cpu
1456 *
1457 * @param[in] ptr SYSCTL_Type base address
1458 * @param[in] cpu_index CPU index
1459 */
sysctl_release_cpu(SYSCTL_Type * ptr,uint8_t cpu_index)1460 static inline void sysctl_release_cpu(SYSCTL_Type *ptr, uint8_t cpu_index)
1461 {
1462 ptr->CPU[cpu_index].LP &= ~SYSCTL_CPU_LP_HALT_MASK;
1463 }
1464
1465 /**
1466 * @brief Release cpu1
1467 *
1468 * @param[in] ptr SYSCTL_Type base address
1469 */
sysctl_release_cpu1(SYSCTL_Type * ptr)1470 static inline void sysctl_release_cpu1(SYSCTL_Type *ptr)
1471 {
1472 sysctl_release_cpu(ptr, 1);
1473 }
1474
1475 /**
1476 * @brief Check whether CPU is released or not
1477 *
1478 * @param [in] ptr SYSCTL_Type base address
1479 * @param[in] cpu_index CPU index
1480 * @retval true CPU is released
1481 * @retval false CPU is on-hold
1482 */
sysctl_is_cpu_released(SYSCTL_Type * ptr,uint8_t cpu_index)1483 static inline bool sysctl_is_cpu_released(SYSCTL_Type *ptr, uint8_t cpu_index)
1484 {
1485 return ((ptr->CPU[cpu_index].LP & SYSCTL_CPU_LP_HALT_MASK) == 0U);
1486 }
1487
1488 /**
1489 * @brief Check whether CPU1 is released or not
1490 *
1491 * @param [in] ptr SYSCTL_Type base address
1492 * @retval true CPU1 is released
1493 * @retval false CPU1 is on-hold
1494 */
sysctl_is_cpu1_released(SYSCTL_Type * ptr)1495 static inline bool sysctl_is_cpu1_released(SYSCTL_Type *ptr)
1496 {
1497 return sysctl_is_cpu_released(ptr, 1);
1498 }
1499
1500 /**
1501 * @brief Config lock
1502 *
1503 * @param[in] ptr SYSCTL_Type base address
1504 * @param[in] node clock node to be configured
1505 * @param[in] source clock source to be used
1506 * @param[in] divide_by clock frequency divider
1507 * @return status_success if everything is okay
1508 */
1509 hpm_stat_t sysctl_config_clock(SYSCTL_Type *ptr,
1510 clock_node_t node,
1511 clock_source_t source,
1512 uint32_t divide_by);
1513
1514 /**
1515 * @brief Set ADC/I2S clock mux
1516 *
1517 * @param[in] ptr SYSCTL_Type base address
1518 * @param[in] node clock node to be configured
1519 * @param[in] source clock source to be used
1520 * @return status_success if everything is okay
1521 */
1522 hpm_stat_t sysctl_set_adc_i2s_clock_mux(SYSCTL_Type *ptr,
1523 clock_node_t node,
1524 clock_source_adc_i2s_t source);
1525
1526 /**
1527 * @brief Enable group resource
1528 *
1529 * @param[in] ptr SYSCTL_Type base address
1530 * @param[in] group target group to be modified
1531 * @param[in] resource target resource to be added/removed from group
1532 * @param[in] enable set true to add resource, remove otherwise
1533 * @return status_success if everything is okay
1534 */
1535 hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr,
1536 uint8_t group,
1537 sysctl_resource_t resource,
1538 bool enable);
1539
1540 /**
1541 * @brief Check group resource enable status
1542 *
1543 * @param[in] ptr SYSCTL_Type base address
1544 * @param[in] group target group to be checked
1545 * @param[in] resource target resource to be checked from group
1546 * @return enable true if resource enable, false if resource disable
1547 */
1548 bool sysctl_check_group_resource_enable(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t linkable_resource);
1549
1550 /**
1551 * @brief Get group resource value
1552 *
1553 * @param[in] ptr SYSCTL_Type base address
1554 * @param[in] group target group to be getted
1555 * @param[in] index target group index
1556 * @return group index value
1557 */
1558 uint32_t sysctl_get_group_resource_value(SYSCTL_Type *ptr, uint8_t group, uint8_t index);
1559
1560 /**
1561 * @brief Add resource to CPU0
1562 *
1563 * @param[in] ptr SYSCTL_Type base address
1564 * @param[in] resource resource to be added to CPU0
1565 * @return status_success if everything is okay
1566 */
1567 hpm_stat_t sysctl_add_resource_to_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource);
1568
1569 /**
1570 * @brief Remove resource from CPU0
1571 *
1572 * @param[in] ptr SYSCTL_Type base address
1573 * @param[in] resource Resource to be removed to CPU0
1574 * @return status_success if everything is okay
1575 */
1576 hpm_stat_t sysctl_remove_resource_from_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource);
1577
1578 /**
1579 * @brief Add resource to CPU1
1580 *
1581 * @param[in] ptr SYSCTL_Type base address
1582 * @param[in] resource Resource to be added to CPU1
1583 * @return status_success if everything is okay
1584 */
1585 hpm_stat_t sysctl_add_resource_to_cpu1(SYSCTL_Type *ptr, sysctl_resource_t resource);
1586
1587 /**
1588 * @brief Remove resource from CPU1
1589 *
1590 * @param[in] ptr SYSCTL_Type base address
1591 * @param[in] resource Resource to be removed to CPU1
1592 * @return status_success if everything is okay
1593 */
1594 hpm_stat_t sysctl_remove_resource_from_cpu1(SYSCTL_Type *ptr, sysctl_resource_t resource);
1595
1596 /**
1597 * @brief Get default monitor config
1598 *
1599 * @param[in] ptr SYSCTL_Type base address
1600 * @param[in] config Monitor config structure pointer
1601 */
1602 void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *config);
1603
1604 /**
1605 * @brief Initialize Monitor
1606 *
1607 * @param[in] ptr SYSCTL_Type base address
1608 * @param[in] monitor_index Monitor instance to be initialized
1609 * @param[in] config Monitor config structure pointer
1610 */
1611 void sysctl_monitor_init(SYSCTL_Type *ptr,
1612 uint8_t monitor_index,
1613 monitor_config_t *config);
1614
1615 /**
1616 * @brief Save data to CPU0 GPR starting from given index
1617 *
1618 * @param[in] ptr SYSCTL_Type base address
1619 * @param[in] start Starting GPR index
1620 * @param[in] count Number of GPR registers to set
1621 * @param[in] data Pointer to data buffer
1622 * @param[in] lock Set true to lock written GPR registers after setting
1623 * @return status_success if everything is okay
1624 */
1625 hpm_stat_t sysctl_cpu0_set_gpr(SYSCTL_Type *ptr,
1626 uint8_t start,
1627 uint8_t count,
1628 uint32_t *data,
1629 bool lock);
1630
1631 /**
1632 * @brief Get data saved from CPU0 GPR starting from given index
1633 *
1634 * @param[in] ptr SYSCTL_Type base address
1635 * @param[in] start Starting GPR index
1636 * @param[in] count Number of GPR registers to set
1637 * @param[out] data Pointer of buffer to save data
1638 * @return status_success if everything is okay
1639 */
1640 hpm_stat_t sysctl_cpu0_get_gpr(SYSCTL_Type *ptr,
1641 uint8_t start,
1642 uint8_t count,
1643 uint32_t *data);
1644
1645 /**
1646 * @brief Set data to CPU1 GPR starting from given index
1647 *
1648 * @param[in] ptr SYSCTL_Type base address
1649 * @param[in] start Starting GPR index
1650 * @param[in] count Number of GPR registers to set
1651 * @param[in] data Pointer to data buffer
1652 * @param[in] lock Set true to lock written GPR registers after setting
1653 * @return status_success if everything is okay
1654 */
1655 hpm_stat_t sysctl_cpu1_set_gpr(SYSCTL_Type *ptr,
1656 uint8_t start,
1657 uint8_t count,
1658 uint32_t *data,
1659 bool lock);
1660
1661 /**
1662 * @brief Get data saved in CPU1 GPR starting from given index
1663 *
1664 * @param[in] ptr SYSCTL_Type base address
1665 * @param[in] start Starting GPR index
1666 * @param[in] count Number of GPR registers to set
1667 * @param[out] data Pointer of buffer to save data
1668 * @return status_success if everything is okay
1669 */
1670 hpm_stat_t sysctl_get_cpu1_gpr(SYSCTL_Type *ptr,
1671 uint8_t start,
1672 uint8_t count,
1673 uint32_t *data);
1674
1675 /**
1676 * @brief Set entry point on CPU boot or wakeup
1677 *
1678 * @param[in] ptr SYSCTL_Type base address
1679 * @param[in] cpu CPU index
1680 * @param[in] entry Entry address for CPU
1681 * @return status_success if everything is okay
1682 */
1683 hpm_stat_t sysctl_set_cpu_entry(SYSCTL_Type *ptr, uint8_t cpu, uint32_t entry);
1684
1685 /**
1686 * @brief Set entry point on CPU0 wakeup
1687 *
1688 * @param[in] ptr SYSCTL_Type base address
1689 * @param[in] entry Entry address for CPU0 on its wakeup
1690 * @return status_success if everything is okay
1691 */
1692 hpm_stat_t sysctl_set_cpu0_wakeup_entry(SYSCTL_Type *ptr, uint32_t entry);
1693
1694 /**
1695 * @brief Set entry point on either CPU1 boot or wakeup
1696 *
1697 * @param[in] ptr SYSCTL_Type base address
1698 * @param[in] entry Entry address for CPU1
1699 * @return status_success if everything is okay
1700 */
1701 hpm_stat_t sysctl_set_cpu1_entry(SYSCTL_Type *ptr, uint32_t entry);
1702
1703 #ifdef __cplusplus
1704 }
1705 #endif
1706 /**
1707 * @}
1708 */
1709 #endif /* HPM_SYSCTL_DRV_H */
1710