1 /*
2 * combo csi module
3 *
4 * Copyright (c) 2019 by Allwinnertech Co., Ltd. http://www.allwinnertech.com
5 *
6 * Authors: Zheng Zequn <zequnzheng@allwinnertech.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include "combo_csi_reg_i.h"
14 #include "combo_csi_reg.h"
15 #include "../../utility/vin_io.h"
16 #include "../../platform/platform_cfg.h"
17
18 static unsigned char cmb_phy_lane[3][4] = {
19 /*phyA*/ /*phyB*/ /*phyC*/
20 {0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11} /*ch*/
21 };
22
23 volatile void *cmb_csi_top_base_addr;
24 volatile void *cmb_csi_phy_base_addr[VIN_MAX_MIPI];
25 volatile void *cmb_csi_port_base_addr[VIN_MAX_MIPI];
26
cmb_csi_set_top_base_addr(unsigned long addr)27 int cmb_csi_set_top_base_addr(unsigned long addr)
28 {
29 cmb_csi_top_base_addr = (volatile void *)addr;
30
31 return 0;
32 }
33
cmb_csi_set_phy_base_addr(unsigned int sel,unsigned long addr)34 int cmb_csi_set_phy_base_addr(unsigned int sel, unsigned long addr)
35 {
36 if (sel > VIN_MAX_MIPI - 1)
37 return -1;
38 cmb_csi_phy_base_addr[sel] = (volatile void *)addr;
39
40 return 0;
41 }
42
cmb_csi_set_port_base_addr(unsigned int sel,unsigned long addr)43 int cmb_csi_set_port_base_addr(unsigned int sel, unsigned long addr)
44 {
45 if (sel > VIN_MAX_MIPI - 1)
46 return -1;
47 cmb_csi_port_base_addr[sel] = (volatile void *)addr;
48
49 return 0;
50 }
51
52 /*
53 * Detail function information of registers----PHY TOP
54 */
cmb_phy_reset_assert(void)55 void cmb_phy_reset_assert(void)
56 {
57 vin_reg_clr_set(cmb_csi_top_base_addr + CMB_PHY_TOP_REG_OFF,
58 CMB_PHY_RSTN_MASK, 0 << CMB_PHY_RSTN);
59 vin_reg_clr_set(cmb_csi_top_base_addr + CMB_PHY_TOP_REG_OFF,
60 CMB_PHY_PWDNZ_MASK, 0 << CMB_PHY_PWDNZ);
61 }
62
cmb_phy_reset_deassert(void)63 void cmb_phy_reset_deassert(void)
64 {
65 vin_reg_clr_set(cmb_csi_top_base_addr + CMB_PHY_TOP_REG_OFF,
66 CMB_PHY_PWDNZ_MASK, 1 << CMB_PHY_PWDNZ);
67 vin_reg_clr_set(cmb_csi_top_base_addr + CMB_PHY_TOP_REG_OFF,
68 CMB_PHY_RSTN_MASK, 1 << CMB_PHY_RSTN);
69 }
70
cmb_phy_power_enable(void)71 void cmb_phy_power_enable(void)
72 {
73 vin_reg_clr_set(cmb_csi_top_base_addr + CMB_PHY_TOP_REG_OFF,
74 CMB_PHY_VREF_EN_MASK, 1 << CMB_PHY_VREF_EN);
75 vin_reg_clr_set(cmb_csi_top_base_addr + CMB_PHY_TOP_REG_OFF,
76 CMB_PHY_LVLDO_EN_MASK, 1 << CMB_PHY_LVLDO_EN);
77 }
78
cmb_phy_power_disable(void)79 void cmb_phy_power_disable(void)
80 {
81 vin_reg_clr_set(cmb_csi_top_base_addr + CMB_PHY_TOP_REG_OFF,
82 CMB_PHY_VREF_EN_MASK, 0 << CMB_PHY_VREF_EN);
83 vin_reg_clr_set(cmb_csi_top_base_addr + CMB_PHY_TOP_REG_OFF,
84 CMB_PHY_LVLDO_EN_MASK, 0 << CMB_PHY_LVLDO_EN);
85 }
86
cmb_phy_set_vref_0p9(unsigned int step)87 void cmb_phy_set_vref_0p9(unsigned int step)
88 {
89 vin_reg_clr_set(cmb_csi_top_base_addr + CMB_PHY_TOP_REG_OFF,
90 CMB_PHY_VREF_OP9_MASK, step << CMB_PHY_VREF_OP9);
91 }
92
cmb_phy_set_vref_0p2(unsigned int step)93 void cmb_phy_set_vref_0p2(unsigned int step)
94 {
95 vin_reg_clr_set(cmb_csi_top_base_addr + CMB_PHY_TOP_REG_OFF,
96 CMB_PHY_VREF_OP2_MASK, step << CMB_PHY_VREF_OP2);
97 }
98
cmb_phy_set_trescal(unsigned int val)99 void cmb_phy_set_trescal(unsigned int val)
100 {
101 vin_reg_clr_set(cmb_csi_top_base_addr + CMB_TRESCAL_REG_OFF,
102 CMB_PHYA_TRESCAL_AUTO_MASK, 0x1 << CMB_PHYA_TRESCAL_AUTO);
103 vin_reg_clr_set(cmb_csi_top_base_addr + CMB_TRESCAL_REG_OFF,
104 CMB_PHYA_TRESCAL_SOFT_MASK, 0x0 << CMB_PHYA_TRESCAL_SOFT);
105 vin_reg_clr_set(cmb_csi_top_base_addr + CMB_TRESCAL_REG_OFF,
106 CMB_PHYA_TRESCAL_SET_MASK, val << CMB_PHYA_TRESCAL_SET);
107 }
108
cmb_phya_trescal_reset_assert(void)109 void cmb_phya_trescal_reset_assert(void)
110 {
111 vin_reg_clr_set(cmb_csi_top_base_addr + CMB_TRESCAL_REG_OFF,
112 CMB_PHYA_TRESCAL_RESETN_MASK, 0x0 << CMB_PHYA_TRESCAL_RESETN);
113 }
114
cmb_phya_trescal_reset_deassert(void)115 void cmb_phya_trescal_reset_deassert(void)
116 {
117 vin_reg_clr_set(cmb_csi_top_base_addr + CMB_TRESCAL_REG_OFF,
118 CMB_PHYA_TRESCAL_RESETN_MASK, 0x1 << CMB_PHYA_TRESCAL_RESETN);
119 }
120
cmb_phy_top_enable(void)121 void cmb_phy_top_enable(void)
122 {
123 cmb_phy_set_vref_0p9(0x1);
124 cmb_phy_set_vref_0p2(0x2);
125 cmb_phy_set_trescal(0xe);
126 cmb_phy_reset_deassert();
127 cmb_phy_power_enable();
128
129 cmb_phya_trescal_reset_assert();
130 cmb_phya_trescal_reset_deassert();
131 }
132
cmb_phy_top_disable(void)133 void cmb_phy_top_disable(void)
134 {
135 cmb_phy_reset_assert();
136 cmb_phy_power_disable();
137 }
138
139 /*
140 * Detail function information of registers----PHYA/B
141 */
cmb_phy0_en(unsigned int sel,unsigned int en)142 void cmb_phy0_en(unsigned int sel, unsigned int en)
143 {
144 vin_reg_clr_set(cmb_csi_phy_base_addr[sel] + CMB_PHY_CTL_REG_OFF,
145 CMB_PHY0_EN_MASK, en << CMB_PHY0_EN);
146 }
147
cmb_phy_lane_num_en(unsigned int sel,struct phy_lane_cfg phy_lane_cfg)148 void cmb_phy_lane_num_en(unsigned int sel, struct phy_lane_cfg phy_lane_cfg)
149 {
150 vin_reg_clr_set(cmb_csi_phy_base_addr[sel] + CMB_PHY_CTL_REG_OFF,
151 CMB_PHY_LANEDT_EN_MASK, phy_lane_cfg.phy_lanedt_en << CMB_PHY_LANEDT_EN);
152 vin_reg_clr_set(cmb_csi_phy_base_addr[sel] + CMB_PHY_CTL_REG_OFF,
153 CMB_PHY_LANECK_EN_MASK, phy_lane_cfg.phy_laneck_en << CMB_PHY_LANECK_EN);
154 }
155
cmb_phy0_work_mode(unsigned int sel,unsigned int mode)156 void cmb_phy0_work_mode(unsigned int sel, unsigned int mode) /* mode 0 --mipi, mode 1 --sub-lvds/hispi*/
157 {
158 vin_reg_clr_set(cmb_csi_phy_base_addr[sel] + CMB_PHY_CTL_REG_OFF,
159 CMB_PHY0_IBIAS_EN_MASK, 1 << CMB_PHY0_IBIAS_EN);
160 vin_reg_clr_set(cmb_csi_phy_base_addr[sel] + CMB_PHY_CTL_REG_OFF,
161 CMB_PHY0_LP_PEFI_MASK, 1 << CMB_PHY0_LP_PEFI);
162 if (mode == 0) {
163 vin_reg_clr_set(cmb_csi_phy_base_addr[sel] + CMB_PHY_CTL_REG_OFF,
164 CMB_PHY0_HS_PEFI_MASK, 0x4 << CMB_PHY0_HS_PEFI);
165 vin_reg_clr_set(cmb_csi_phy_base_addr[sel] + CMB_PHY_CTL_REG_OFF,
166 CMB_PHY0_WORK_MODE_MASK, 0 << CMB_PHY0_WORK_MODE);
167 } else {
168 vin_reg_clr_set(cmb_csi_phy_base_addr[sel] + CMB_PHY_CTL_REG_OFF,
169 CMB_PHY0_HS_PEFI_MASK, 0x2 << CMB_PHY0_HS_PEFI);
170 vin_reg_clr_set(cmb_csi_phy_base_addr[sel] + CMB_PHY_CTL_REG_OFF,
171 CMB_PHY0_WORK_MODE_MASK, 1 << CMB_PHY0_WORK_MODE);
172 }
173 }
174
cmb_phy0_ofscal_cfg(unsigned int sel)175 void cmb_phy0_ofscal_cfg(unsigned int sel)
176 {
177 vin_reg_clr_set(cmb_csi_phy_base_addr[sel] + CMB_PHY_OFSCAL0_OFF,
178 CMB_PHY0_OFSCAL_AUTO_MASK, 0 << CMB_PHY0_OFSCAL_AUTO);
179 vin_reg_clr_set(cmb_csi_phy_base_addr[sel] + CMB_PHY_OFSCAL0_OFF,
180 CMB_PHY0_OFSCAL_SOFT_MASK, 1 << CMB_PHY0_OFSCAL_SOFT);
181 vin_reg_clr_set(cmb_csi_phy_base_addr[sel] + CMB_PHY_OFSCAL1_OFF,
182 CMB_PHY0_OFSCAL_SET_MASK, 0x13 << CMB_PHY0_OFSCAL_SET);
183 }
184
cmb_phy_deskew_en(unsigned int sel,struct phy_lane_cfg phy_lane_cfg)185 void cmb_phy_deskew_en(unsigned int sel, struct phy_lane_cfg phy_lane_cfg)
186 {
187 vin_reg_clr_set(cmb_csi_phy_base_addr[sel] + CMB_PHY_DESKEW0_OFF,
188 CMB_PHY_DESKEW_EN_MASK, phy_lane_cfg.phy_deskew_en << CMB_PHY_DESKEW_EN);
189 vin_reg_clr_set(cmb_csi_phy_base_addr[sel] + CMB_PHY_DESKEW0_OFF,
190 CMB_PHY_DESKEW_PERIOD_EN_MASK, phy_lane_cfg.phy_deskew_period_en << CMB_PHY_DESKEW_PERIOD_EN);
191 }
192
cmb_phy0_term_dly(unsigned int sel,unsigned int dly)193 void cmb_phy0_term_dly(unsigned int sel, unsigned int dly)
194 {
195 vin_reg_clr_set(cmb_csi_phy_base_addr[sel] + CMB_PHY_TERM_CTL_REG_OFF,
196 CMB_PHY0_TERM_EN_DLY_MASK, dly << CMB_PHY0_TERM_EN_DLY);
197 }
198
cmb_phy_mipi_termnum_en(unsigned int sel,struct phy_lane_cfg phy_lane_cfg)199 void cmb_phy_mipi_termnum_en(unsigned int sel, struct phy_lane_cfg phy_lane_cfg)
200 {
201 vin_reg_clr_set(cmb_csi_phy_base_addr[sel] + CMB_PHY_TERM_CTL_REG_OFF,
202 CMB_PHY_TERMDT_EN_MASK, phy_lane_cfg.phy_termdt_en << CMB_PHY_TERMDT_EN);
203 vin_reg_clr_set(cmb_csi_phy_base_addr[sel] + CMB_PHY_TERM_CTL_REG_OFF,
204 CMB_PHY_TERMCK_EN_MASK, phy_lane_cfg.phy_termck_en << CMB_PHY_TERMCK_EN);
205 }
206
cmb_term_ctl(unsigned int sel,struct phy_lane_cfg phy_lane_cfg)207 void cmb_term_ctl(unsigned int sel, struct phy_lane_cfg phy_lane_cfg)
208 {
209 cmb_phy0_term_dly(sel, 0);
210 cmb_phy_mipi_termnum_en(sel, phy_lane_cfg);
211 }
212
cmb_phy0_hs_dly(unsigned int sel,unsigned int dly)213 void cmb_phy0_hs_dly(unsigned int sel, unsigned int dly)
214 {
215 vin_reg_clr_set(cmb_csi_phy_base_addr[sel] + CMB_PHY_HS_CTL_REG_OFF,
216 CMB_PHY0_HS_DLY_MASK, dly << CMB_PHY0_HS_DLY);
217 }
218
cmb_phy_hs_en(unsigned int sel,struct phy_lane_cfg phy_lane_cfg)219 void cmb_phy_hs_en(unsigned int sel, struct phy_lane_cfg phy_lane_cfg)
220 {
221 vin_reg_clr_set(cmb_csi_phy_base_addr[sel] + CMB_PHY_HS_CTL_REG_OFF,
222 CMB_PHY_HSDT_EN_MASK, phy_lane_cfg.phy_hsdt_en << CMB_PHY_HSDT_EN);
223 vin_reg_clr_set(cmb_csi_phy_base_addr[sel] + CMB_PHY_HS_CTL_REG_OFF,
224 CMB_PHY_HSCK_EN_MASK, phy_lane_cfg.phy_hsck_en << CMB_PHY_HSCK_EN);
225 }
226
cmb_hs_ctl(unsigned int sel,struct phy_lane_cfg phy_lane_cfg)227 void cmb_hs_ctl(unsigned int sel, struct phy_lane_cfg phy_lane_cfg)
228 {
229 cmb_phy0_hs_dly(sel, 0);
230 cmb_phy_hs_en(sel, phy_lane_cfg);
231 }
232
cmb_phy_s2p_en(unsigned int sel,struct phy_lane_cfg phy_lane_cfg)233 void cmb_phy_s2p_en(unsigned int sel, struct phy_lane_cfg phy_lane_cfg)
234 {
235 vin_reg_clr_set(cmb_csi_phy_base_addr[sel] + CMB_PHY_S2P_CTL_REG_OFF,
236 CMB_PHY_S2P_EN_MASK, phy_lane_cfg.phy_s2p_en << CMB_PHY_S2P_EN);
237 }
238
cmb_phy0_s2p_width(unsigned int sel,unsigned int width)239 void cmb_phy0_s2p_width(unsigned int sel, unsigned int width)
240 {
241 vin_reg_clr_set(cmb_csi_phy_base_addr[sel] + CMB_PHY_S2P_CTL_REG_OFF,
242 CMB_PHY0_S2P_WIDTH_MASK, width << CMB_PHY0_S2P_WIDTH);
243 }
244
cmb_phy0_s2p_dly(unsigned int sel,unsigned int dly)245 void cmb_phy0_s2p_dly(unsigned int sel, unsigned int dly)
246 {
247 vin_reg_clr_set(cmb_csi_phy_base_addr[sel] + CMB_PHY_S2P_CTL_REG_OFF,
248 CMB_PHY0_S2P_DLY_MASK, dly << CMB_PHY0_S2P_DLY);
249 }
250
cmb_s2p_ctl(unsigned int sel,unsigned int dly,struct phy_lane_cfg phy_lane_cfg)251 void cmb_s2p_ctl(unsigned int sel, unsigned int dly, struct phy_lane_cfg phy_lane_cfg)
252 {
253 cmb_phy_s2p_en(sel, phy_lane_cfg);
254 cmb_phy0_s2p_width(sel, 0x3);
255 cmb_phy0_s2p_dly(sel, dly);
256 }
257
cmb_phy_mipi_lpnum_en(unsigned int sel,struct phy_lane_cfg phy_lane_cfg)258 void cmb_phy_mipi_lpnum_en(unsigned int sel, struct phy_lane_cfg phy_lane_cfg)
259 {
260 vin_reg_clr_set(cmb_csi_phy_base_addr[sel] + CMB_PHY_MIPIRX_CTL_REG_OFF,
261 CMB_PHY_MIPI_LPDT_EN_MASK, phy_lane_cfg.phy_mipi_lpdt_en << CMB_PHY_MIPI_LPDT_EN);
262 vin_reg_clr_set(cmb_csi_phy_base_addr[sel] + CMB_PHY_MIPIRX_CTL_REG_OFF,
263 CMB_PHY_MIPI_LPCK_EN_MASK, phy_lane_cfg.phy_mipi_lpck_en << CMB_PHY_MIPI_LPCK_EN);
264 }
265
cmb_phy0_mipilp_dbc_en(unsigned int sel,unsigned int en)266 void cmb_phy0_mipilp_dbc_en(unsigned int sel, unsigned int en)
267 {
268 vin_reg_clr_set(cmb_csi_phy_base_addr[sel] + CMB_PHY_MIPIRX_CTL_REG_OFF,
269 CMB_PHY0_MIPILP_DBC_EN_MASK, en << CMB_PHY0_MIPILP_DBC_EN);
270 }
271
cmb_phy0_mipihs_sync_mode(unsigned int sel,unsigned int mode)272 void cmb_phy0_mipihs_sync_mode(unsigned int sel, unsigned int mode)
273 {
274 vin_reg_clr_set(cmb_csi_phy_base_addr[sel] + CMB_PHY_MIPIRX_CTL_REG_OFF,
275 CMB_PHY0_MIPIHS_SYNC_MODE_MASK, mode << CMB_PHY0_MIPIHS_SYNC_MODE);
276 }
277
cmb_mipirx_ctl(unsigned int sel,struct phy_lane_cfg phy_lane_cfg)278 void cmb_mipirx_ctl(unsigned int sel, struct phy_lane_cfg phy_lane_cfg)
279 {
280 cmb_phy_mipi_lpnum_en(sel, phy_lane_cfg);
281 cmb_phy0_mipilp_dbc_en(sel, 1);
282 cmb_phy0_mipihs_sync_mode(sel, 0);
283 }
284
285 /*
286 * Detail function information of registers----PORT0/1
287 */
cmb_port_enable(unsigned int sel)288 void cmb_port_enable(unsigned int sel)
289 {
290 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_CTL_REG_OFF,
291 CMB_PORT_EN_MASK, 1 << CMB_PORT_EN);
292 }
293
cmb_port_disable(unsigned int sel)294 void cmb_port_disable(unsigned int sel)
295 {
296 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_CTL_REG_OFF,
297 CMB_PORT_EN_MASK, 0 << CMB_PORT_EN);
298 }
299
cmb_port_lane_num(unsigned int sel,unsigned int num)300 void cmb_port_lane_num(unsigned int sel, unsigned int num)
301 {
302 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_CTL_REG_OFF,
303 CMB_PORT_LANE_NUM_MASK, num << CMB_PORT_LANE_NUM);
304 }
305
cmb_port_out_num(unsigned int sel,enum cmb_csi_pix_num cmb_csi_pix_num)306 void cmb_port_out_num(unsigned int sel, enum cmb_csi_pix_num cmb_csi_pix_num)
307 {
308 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_CTL_REG_OFF,
309 CMB_PORT_OUT_NUM_MASK, cmb_csi_pix_num << CMB_PORT_OUT_NUM);
310 }
311
cmb_port_out_chnum(unsigned int sel,unsigned int chnum)312 void cmb_port_out_chnum(unsigned int sel, unsigned int chnum)
313 {
314 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_CTL_REG_OFF,
315 CMB_PORT_CHANNEL_NUM_MASK, chnum << CMB_PORT_CHANNEL_NUM);
316 }
317
cmb_port_set_lane_map(unsigned int phy,unsigned int ch)318 unsigned char cmb_port_set_lane_map(unsigned int phy, unsigned int ch)
319 {
320 return cmb_phy_lane[phy][ch];
321 }
322
cmb_port_lane_map(unsigned int sel,unsigned char * mipi_lane)323 void cmb_port_lane_map(unsigned int sel, unsigned char *mipi_lane)
324 {
325 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_LANE_MAP_REG0_OFF,
326 CMB_PORT_LANE0_ID_MASK, mipi_lane[0] << CMB_PORT_LANE0_ID);
327 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_LANE_MAP_REG0_OFF,
328 CMB_PORT_LANE1_ID_MASK, mipi_lane[1] << CMB_PORT_LANE1_ID);
329 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_LANE_MAP_REG0_OFF,
330 CMB_PORT_LANE2_ID_MASK, mipi_lane[2] << CMB_PORT_LANE2_ID);
331 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_LANE_MAP_REG0_OFF,
332 CMB_PORT_LANE3_ID_MASK, mipi_lane[3] << CMB_PORT_LANE3_ID);
333 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_LANE_MAP_REG0_OFF,
334 CMB_PORT_LANE4_ID_MASK, mipi_lane[4] << CMB_PORT_LANE4_ID);
335 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_LANE_MAP_REG0_OFF,
336 CMB_PORT_LANE5_ID_MASK, mipi_lane[5] << CMB_PORT_LANE5_ID);
337 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_LANE_MAP_REG0_OFF,
338 CMB_PORT_LANE6_ID_MASK, mipi_lane[6] << CMB_PORT_LANE6_ID);
339 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_LANE_MAP_REG0_OFF,
340 CMB_PORT_LANE7_ID_MASK, mipi_lane[7] << CMB_PORT_LANE7_ID);
341 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_LANE_MAP_REG1_OFF,
342 CMB_PORT_LANE8_ID_MASK, mipi_lane[8] << CMB_PORT_LANE8_ID);
343 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_LANE_MAP_REG1_OFF,
344 CMB_PORT_LANE9_ID_MASK, mipi_lane[9] << CMB_PORT_LANE9_ID);
345 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_LANE_MAP_REG1_OFF,
346 CMB_PORT_LANE10_ID_MASK, mipi_lane[10] << CMB_PORT_LANE10_ID);
347 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_LANE_MAP_REG1_OFF,
348 CMB_PORT_LANE11_ID_MASK, mipi_lane[11] << CMB_PORT_LANE11_ID);
349 }
350
cmb_port_set_wdr_mode(unsigned int sel,unsigned int mode)351 void cmb_port_set_wdr_mode(unsigned int sel, unsigned int mode)
352 {
353 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_WDR_MODE_REG_OFF,
354 CMB_PORT_WDR_MODE_MASK, mode << CMB_PORT_WDR_MODE);
355 }
356
cmb_port_set_fid_mode(unsigned int sel,unsigned int mode)357 void cmb_port_set_fid_mode(unsigned int sel, unsigned int mode)
358 {
359 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_FID_SEL_REG_OFF,
360 CMB_PORT_FID_MODE_MASK, mode << CMB_PORT_FID_MODE);
361 }
362
cmb_port_set_fid_ch_map(unsigned int sel,unsigned int ch)363 void cmb_port_set_fid_ch_map(unsigned int sel, unsigned int ch)
364 {
365 switch (ch) {
366 case 2:
367 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_FID_SEL_REG_OFF,
368 CMB_PORT_FID0_MAP_MASK, 0 << CMB_PORT_FID0_MAP);
369 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_FID_SEL_REG_OFF,
370 CMB_PORT_FID1_MAP_MASK, 1 << CMB_PORT_FID1_MAP);
371 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_FID_SEL_REG_OFF,
372 CMB_PORT_FID_MAP_EN_MASK, 0x3 << CMB_PORT_FID_MAP_EN);
373 break;
374 case 3:
375 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_FID_SEL_REG_OFF,
376 CMB_PORT_FID0_MAP_MASK, 0 << CMB_PORT_FID0_MAP);
377 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_FID_SEL_REG_OFF,
378 CMB_PORT_FID1_MAP_MASK, 1 << CMB_PORT_FID1_MAP);
379 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_FID_SEL_REG_OFF,
380 CMB_PORT_FID2_MAP_MASK, 2 << CMB_PORT_FID2_MAP);
381 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_FID_SEL_REG_OFF,
382 CMB_PORT_FID_MAP_EN_MASK, 0x7 << CMB_PORT_FID_MAP_EN);
383 break;
384 case 4:
385 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_FID_SEL_REG_OFF,
386 CMB_PORT_FID0_MAP_MASK, 0 << CMB_PORT_FID0_MAP);
387 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_FID_SEL_REG_OFF,
388 CMB_PORT_FID1_MAP_MASK, 1 << CMB_PORT_FID1_MAP);
389 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_FID_SEL_REG_OFF,
390 CMB_PORT_FID2_MAP_MASK, 2 << CMB_PORT_FID2_MAP);
391 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_FID_SEL_REG_OFF,
392 CMB_PORT_FID3_MAP_MASK, 3 << CMB_PORT_FID3_MAP);
393 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_FID_SEL_REG_OFF,
394 CMB_PORT_FID_MAP_EN_MASK, 0xf << CMB_PORT_FID_MAP_EN);
395 break;
396 default:
397 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_FID_SEL_REG_OFF,
398 CMB_PORT_FID0_MAP_MASK, 0 << CMB_PORT_FID0_MAP);
399 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_FID_SEL_REG_OFF,
400 CMB_PORT_FID1_MAP_MASK, 1 << CMB_PORT_FID1_MAP);
401 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_FID_SEL_REG_OFF,
402 CMB_PORT_FID_MAP_EN_MASK, 0x3 << CMB_PORT_FID_MAP_EN);
403 break;
404 }
405 }
406
cmb_port_mipi_unpack_enable(unsigned int sel)407 void cmb_port_mipi_unpack_enable(unsigned int sel)
408 {
409 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_MIPI_CFG_REG_OFF,
410 CMB_MIPI_UNPACK_EN_MASK, 1 << CMB_MIPI_UNPACK_EN);
411 }
412
cmb_port_mipi_unpack_disable(unsigned int sel)413 void cmb_port_mipi_unpack_disable(unsigned int sel)
414 {
415 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_MIPI_CFG_REG_OFF,
416 CMB_MIPI_UNPACK_EN_MASK, 0 << CMB_MIPI_UNPACK_EN);
417 }
418
cmb_port_mipi_yuv_seq(unsigned int sel,enum cmb_mipi_yuv_seq seq)419 void cmb_port_mipi_yuv_seq(unsigned int sel, enum cmb_mipi_yuv_seq seq)
420 {
421 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_MIPI_CFG_REG_OFF,
422 CMB_MIPI_YUV_SEQ_MASK, seq << CMB_MIPI_YUV_SEQ);
423 }
424
cmb_port_mipi_ph_bitord(unsigned int sel,unsigned int order)425 void cmb_port_mipi_ph_bitord(unsigned int sel, unsigned int order)
426 {
427 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_MIPI_CFG_REG_OFF,
428 CMB_MIPI_PH_BITOED_MASK, order << CMB_MIPI_PH_BITOED);
429 }
430
cmb_port_mipi_cfg(unsigned int sel,enum cmb_mipi_yuv_seq seq)431 void cmb_port_mipi_cfg(unsigned int sel, enum cmb_mipi_yuv_seq seq)
432 {
433 cmb_port_mipi_unpack_enable(sel);
434 cmb_port_mipi_ph_bitord(sel, 0);
435 cmb_port_mipi_yuv_seq(sel, seq);
436 }
437
cmb_port_set_mipi_datatype(unsigned int sel,struct combo_csi_cfg * combo_csi_cfg)438 void cmb_port_set_mipi_datatype(unsigned int sel, struct combo_csi_cfg *combo_csi_cfg)
439 {
440 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_MIPI_DI_REG_OFF,
441 CMB_MIPI_CH0_DT_MASK, combo_csi_cfg->mipi_datatype[0] << CMB_MIPI_CH0_DT);
442 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_MIPI_DI_REG_OFF,
443 CMB_MIPI_CH0_VC_MASK, combo_csi_cfg->vc[0] << CMB_MIPI_CH0_VC);
444 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_MIPI_DI_REG_OFF,
445 CMB_MIPI_CH1_DT_MASK, combo_csi_cfg->mipi_datatype[1] << CMB_MIPI_CH1_DT);
446 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_MIPI_DI_REG_OFF,
447 CMB_MIPI_CH1_VC_MASK, combo_csi_cfg->vc[1] << CMB_MIPI_CH1_VC);
448 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_MIPI_DI_REG_OFF,
449 CMB_MIPI_CH2_DT_MASK, combo_csi_cfg->mipi_datatype[2] << CMB_MIPI_CH2_DT);
450 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_MIPI_DI_REG_OFF,
451 CMB_MIPI_CH2_VC_MASK, combo_csi_cfg->vc[2] << CMB_MIPI_CH2_VC);
452 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_MIPI_DI_REG_OFF,
453 CMB_MIPI_CH3_DT_MASK, combo_csi_cfg->mipi_datatype[3] << CMB_MIPI_CH3_DT);
454 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_MIPI_DI_REG_OFF,
455 CMB_MIPI_CH3_VC_MASK, combo_csi_cfg->vc[3] << CMB_MIPI_CH3_VC);
456 }
457
cmb_port_mipi_ch_trigger_en(unsigned int sel,unsigned int en)458 void cmb_port_mipi_ch_trigger_en(unsigned int sel, unsigned int en)
459 {
460 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_MIPI_DI_TRIG_REG_OFF,
461 CMB_MIPI_FS_MASK, en << CMB_MIPI_FS);
462 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_MIPI_DI_TRIG_REG_OFF,
463 CMB_MIPI_FE_MASK, en << CMB_MIPI_FE);
464 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_MIPI_DI_TRIG_REG_OFF,
465 CMB_MIPI_LS_MASK, en << CMB_MIPI_LS);
466 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_MIPI_DI_TRIG_REG_OFF,
467 CMB_MIPI_LE_MASK, en << CMB_MIPI_LE);
468 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_MIPI_DI_TRIG_REG_OFF,
469 CMB_MIPI_YUV_MASK, en << CMB_MIPI_YUV);
470 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_MIPI_DI_TRIG_REG_OFF,
471 CMB_MIPI_RGB_MASK, en << CMB_MIPI_RGB);
472 vin_reg_clr_set(cmb_csi_port_base_addr[sel] + CMB_PORT_MIPI_DI_TRIG_REG_OFF,
473 CMB_MIPI_RAW_MASK, en << CMB_MIPI_RAW);
474 }
475
cmb_port_set_mipi_wdr(unsigned int sel,unsigned int mode,unsigned int ch)476 void cmb_port_set_mipi_wdr(unsigned int sel, unsigned int mode, unsigned int ch)
477 {
478 cmb_port_set_wdr_mode(sel, 2);
479 cmb_port_set_fid_ch_map(sel, ch);
480 cmb_port_set_fid_mode(sel, mode);
481 cmb_port_out_num(sel, ONE_DATA);
482 cmb_port_out_chnum(sel, ch-1);
483 }
484
485