1 /*
2 * A V4L2 driver for nvp6324 cameras and AHD Coax protocol.
3 *
4 * Copyright (c) 2017 by Allwinnertech Co., Ltd. http://www.allwinnertech.com
5 *
6 * Authors: Li Huiyu <lihuiyu@allwinnertech.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/string.h>
14 #include <linux/delay.h>
15 #include "jaguar1_common.h"
16 #include "jaguar1_video.h"
17 #include "jaguar1_video_eq.h"
18 #include "jaguar1_video_table.h"
19 #include "jaguar1_coax_protocol.h"
20 #include "jaguar1_reg_set_def.h"
21 #include "../sensor_helper.h"
22
23 #define SENSOR_NAME "nvp6324_mipi"
24
25 static unsigned char cur_bank = 0xff;
26 static int print_flag;
27
28 extern unsigned int bit8;
29
30 /**************************************************************************************
31 * Jaguar1 Video Input initialize value get from table
32 ***************************************************************************************/
__NC_VD_VI_Init_Val_Get(NC_VIVO_CH_FORMATDEF def)33 NC_VD_VI_Init_STR *__NC_VD_VI_Init_Val_Get(NC_VIVO_CH_FORMATDEF def)
34 {
35 NC_VD_VI_Init_STR *pRet = &vd_vi_init_list[def];
36 if (pRet == NULL) {
37 sensor_dbg("[DRV]vd_vi_init_list Not Supported format Yet!!!(%d)\n", def);
38 }
39 return pRet;
40 }
41
__NC_VD_VO_Init_Val_Get(NC_VIVO_CH_FORMATDEF def)42 NC_VD_VO_Init_STR *__NC_VD_VO_Init_Val_Get(NC_VIVO_CH_FORMATDEF def)
43 {
44 NC_VD_VO_Init_STR *pRet = &vd_vo_init_list[def];
45 if (pRet == NULL) {
46 sensor_dbg("[DRV]vd_vo_init_list Not Supported format Yet!!!(%d)\n", def);
47 }
48 return pRet;
49 }
50
51 /**************************************************************************************
52 * Jaguar1 Register Setting Function
53 *
54 *
55 ***************************************************************************************/
reg_val_print_flag_set(int set)56 void reg_val_print_flag_set(int set)
57 {
58 print_flag = set;
59 }
60
reg_val_print_flag_get(void)61 int reg_val_print_flag_get(void)
62 {
63 return print_flag;
64 }
65
current_bank_set(unsigned char bank)66 void current_bank_set(unsigned char bank)
67 {
68 cur_bank = bank;
69 }
70
current_bank_get(void)71 unsigned char current_bank_get(void)
72 {
73 return cur_bank;
74 }
75
vd_register_set(int dev,unsigned char bank,unsigned char addr,unsigned char val,int pos,int size)76 void vd_register_set(int dev, unsigned char bank, unsigned char addr, unsigned char val, int pos, int size)
77 {
78 unsigned char ReadVal = 0x00;
79 unsigned char Mask = 0x00;
80 unsigned char rstbit = 0x01;
81 unsigned char WriteVal = val;
82 unsigned char cur_bank = 0x00;
83 int ii = 0;
84
85 if (8 < (pos + size)) {
86 sensor_dbg("vd_register_set Error!!dev[%d] Bank[0x%02X] Addr[0x%02X] pos[%d] size[%d]\n", dev, bank, addr, pos, size);
87 }
88
89 cur_bank = current_bank_get();
90 if (cur_bank != bank) {
91 JAGUAR1_BANK_CHANGE(bank);
92 current_bank_set(bank);
93 }
94
95 if (!(pos == 0 && size == 8)) {
96 for (ii = 0; ii < size; ii++) {
97 Mask = Mask|(rstbit<<(pos+ii));
98 }
99 Mask = ~Mask;
100 WriteVal = WriteVal<<pos;
101
102 ReadVal = gpio_i2c_read(jaguar1_i2c_addr[dev], addr);
103 ReadVal = ReadVal & Mask;
104 WriteVal = WriteVal | ReadVal;
105 }
106
107 gpio_i2c_write(jaguar1_i2c_addr[dev], addr, WriteVal);
108
109 if (reg_val_print_flag_get())
110 sensor_dbg("[DRV]%Xx%02X > 0x%02X\n", current_bank_get(), addr, WriteVal);
111
112 }
113
114 /**************************************************************************************
115 * Jaguar1 Video Input Setting Function
116 *
117 *
118 ***************************************************************************************/
vd_vi_manual_set_seq1(unsigned char dev,unsigned char ch,void * p_param)119 void vd_vi_manual_set_seq1(unsigned char dev, unsigned char ch, void *p_param)
120 {
121 /*====================================================================
122 * Bank 1x7c
123 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
124 *| | | | | CLK_AUTO_4 | CLK_AUTO_3 | CLK_AUTO_2 | CLK_AUTO_1 |
125 *====================================================================*/
126 /*====================================================================
127 * Bank 0x14
128 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
129 *| | | | FLD_INV_x | CHID_VIN_x |
130 *====================================================================*/
131 /*====================================================================
132 * Bank 0x14
133 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
134 *| | | | FLD_INV_x | CHID_VIN_x |
135 *====================================================================*/
136 /*====================================================================
137 * Bank 5x32
138 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
139 *| | | FLD_DET_MODE | | | NOVID_DET_A |
140 *====================================================================*/
141 /*====================================================================
142 * Bank 13x30 ~ 33 - SK_ing
143 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
144 *| | |det_en |det_en |det_en |det_en |det_en |det_en |
145 *====================================================================*/
146 /*====================================================================
147 * Bank 9x44
148 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
149 *| | | | | | | |FSC_EXT_EN_1 |
150 *====================================================================*/
151 NC_VD_VI_Init_STR *param = (NC_VD_VI_Init_STR *)p_param;
152 unsigned char val_13x30;
153 unsigned char val_13x31;
154 unsigned char val_13x32;
155
156 if (ch == 0)
157 REG_SET_1x7C_0_1_clk_auto_1(ch, 0x0);
158 else if (ch == 1)
159 REG_SET_1x7C_1_1_clk_auto_2(ch, 0x0);
160 else if (ch == 2)
161 REG_SET_1x7C_2_1_clk_auto_3(ch, 0x0);
162 else if (ch == 3)
163 REG_SET_1x7C_3_1_clk_auto_4(ch, 0x0);
164 else
165 printk("[DRV]Clock Auto Set Fail!!:: %x\n", ch);
166
167 REG_SET_5x32_0_8_NOVIDEO_DET_A(ch, 0x10);
168 REG_SET_5xB9_0_8_HAFC_LPF_SEL(ch, 0xb2);
169
170 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xFF, 0x13);
171 val_13x30 = gpio_i2c_read(jaguar1_i2c_addr[dev], 0x30);
172 val_13x31 = gpio_i2c_read(jaguar1_i2c_addr[dev], 0x31);
173 val_13x32 = gpio_i2c_read(jaguar1_i2c_addr[dev], 0x32);
174
175 val_13x30 &= (~(1 << (ch + 4)) & (~(1 << ch)));
176 val_13x31 &= (~(1 << (ch + 4)) & (~(1 << ch)));
177 val_13x32 &= (~(1 << ch));
178
179 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x30, val_13x30);
180 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x31, val_13x31);
181 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x32, val_13x32);
182
183 REG_SET_9x44_0_8_FSC_EXT_EN(ch, 0x00);
184 REG_SET_5x6E_0_8_VBLK_END_SEL(ch, param->vblk_end_sel);
185 REG_SET_5x6F_0_8_VBLK_END_EXT(ch, param->vblk_end_ext);
186
187 }
188
vd_vi_vafe_set_seq2(unsigned char dev,unsigned char ch)189 void vd_vi_vafe_set_seq2(unsigned char dev, unsigned char ch)
190 {
191 REG_SET_5x00_0_8_A_CMP_PW_MODE(ch, 0xd0);
192 REG_SET_5x02_0_8_A_CMP_TIMEUNIT(ch, 0x0c);
193 REG_SET_5x1E_0_8_VAFEMD(ch, 0x00);
194 REG_SET_5x58_0_8_VAFE1_EQ_BAND_SEL(ch, 0x00);
195 REG_SET_5x59_0_8_LPF_BYPASS(ch, 0x00);
196 REG_SET_5x5A_0_8_VAFE_IMP_CNT(ch, 0x00);
197 REG_SET_5x5B_0_8_VAFE_DUTY(ch, 0x41);
198 REG_SET_5x5C_0_8_VAFE_B_LPF_SEL(ch, 0x78);
199 REG_SET_5x94_0_8_PWM_DELAY_H(ch, 0x00);
200 REG_SET_5x95_0_8_PWM_DELAY_L(ch, 0x00);
201 REG_SET_5x65_0_8_VAFE_CML_SPEED(ch, 0x80);
202
203 }
204
vd_vi_format_set_seq3(unsigned char dev,unsigned char ch,void * p_param)205 void vd_vi_format_set_seq3(unsigned char dev, unsigned char ch, void *p_param)
206 {
207 /*============================================================================================
208 * Bank 0x10
209 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
210 *| | BSF_MODE_1 | VIDEO_FORMAT_1 |
211 *============================================================================================*/
212 /*============================================================================================
213 * Bank 0x0c
214 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
215 *| | | | | SPECIAL_MODE |
216 *============================================================================================*/
217 /*============================================================================================
218 * Bank 0x04
219 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
220 *| | | | | SD_MD |
221 *============================================================================================*/
222 /*============================================================================================
223 * Bank 0x08
224 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
225 *| | | | | AHD_MD |
226 *============================================================================================*/
227 /*============================================================================================
228 * Bank 5x69
229 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
230 *| NO_VIDEO_OFF | | OUTPUT PATTERN_ON | MEM_EN | | | | SD_FREQ_SEL |
231 *============================================================================================*/
232 NC_VD_VI_Init_STR *param = (NC_VD_VI_Init_STR *)p_param;
233
234 if (ch > 3) {
235 printk("[DRV] %s CHID Error\n", __func__);
236 return;
237 }
238
239 REG_SET_0x10_0_8_VD_FMT(ch, param->video_format);
240 REG_SET_0x0C_0_8_SPL_MODE(ch, param->spl_mode);
241 REG_SET_0x04_0_8_SD_MODE(ch, param->sd_mode);
242 REG_SET_0x08_0_8_AHD_MODE(ch, param->ahd_mode);
243 REG_SET_5x69_0_1_SD_FREQ_SEL(ch, param->sd_freq_sel);
244 REG_SET_5x62_0_8_SYNC_SEL(ch, param->sync_sel);
245
246 }
247
vd_vi_chroma_set_seq4(unsigned char dev,unsigned char ch,void * p_param)248 void vd_vi_chroma_set_seq4(unsigned char dev, unsigned char ch, void *p_param)
249 {
250 /*============================================================================================
251 * Bank 0x5c
252 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
253 *| PAL_CM_OFF | | | COLOROFF | C_KILL |
254 *============================================================================================*/
255 /*============================================================================================
256 * Bank 5x28
257 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
258 *| CTI_CORE_MODE | S_POINT | CTI_DELAY_SEL | | | | |
259 *============================================================================================*/
260 /*============================================================================================
261 * Bank 5x25
262 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
263 *| FSC_LOCK_MODE | FSC_LOCK_SPD |
264 *============================================================================================*/
265 /*============================================================================================
266 * Bank 5x90
267 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
268 *| C_LH_SEL_1 | | YL_SEL_1 | COMB_MODE_1 |
269 *============================================================================================*/
270 NC_VD_VI_Init_STR *param = (NC_VD_VI_Init_STR *)p_param;
271
272 if (ch > 3) {
273 printk("[DRV] %s CHID Error\n", __func__);
274 return;
275 }
276
277 REG_SET_0x5C_0_8_PAL_CM_OFF(ch, param->pal_cm_off);
278 REG_SET_5x28_0_8_S_POINT(ch, param->s_point);
279 REG_SET_5x25_0_8_FSC_LOCK_MODE(ch, param->fsc_lock_mode);
280 REG_SET_5x90_0_8_COMB_MODE(ch, param->comb_mode);
281
282 }
283
vd_vi_h_timing_set_seq5(unsigned char dev,unsigned char ch,void * p_param)284 void vd_vi_h_timing_set_seq5(unsigned char dev, unsigned char ch, void *p_param)
285 {
286 /*============================================================================================
287 * Bank 0x68
288 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
289 *| H_DELAY |
290 *============================================================================================*/
291 /*============================================================================================
292 * Bank 0x60
293 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
294 *| | Y_DELAY |
295 *============================================================================================*/
296 /*============================================================================================
297 * Bank 0x78
298 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
299 *| HBLK_END |
300 *============================================================================================*/
301 /*============================================================================================
302 * Bank 5x38
303 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
304 *| | MASK_ON | MASK_SEL1 (Bank0 0x8E[3:0) |
305 *============================================================================================*/
306 /*============================================================================================
307 * Bank 0x64
308 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
309 *| DF_CDELAY | DF_YDELAY |
310 *============================================================================================*/
311 /*============================================================================================
312 * Bank 0x14
313 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
314 *| | FLD_INV | CHID_VIN |
315 *============================================================================================*/
316 /*============================================================================================
317 * Bank 5x64
318 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
319 *| | | | | MEM_RDP_01 |
320 *============================================================================================*/
321 /*============================================================================================
322 * Bank 5x47
323 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
324 *| CONTROL_MODES |
325 *============================================================================================*/
326 /*============================================================================================
327 * Bank 5xa9
328 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
329 *| SIGNED_ADV_STP_DELAY1 | ADV_STP_DELAY1 |
330 *============================================================================================*/
331 NC_VD_VI_Init_STR *param = (NC_VD_VI_Init_STR *)p_param;
332
333 if (ch > 3) {
334 sensor_dbg("[DRV] %s CHID Error\n", __func__);
335 return;
336 }
337
338 REG_SET_0x68_0_8_H_DLY_LSB(ch, param->h_delay_lsb);
339 REG_SET_0x6c_0_8_H_DLY_MSB(ch, param->h_dly_msb);
340 REG_SET_0x60_0_8_Y_DLY(ch, param->y_delay);
341 REG_SET_0x78_0_8_V_BLK_END_A(ch, param->v_blk_end_a);
342
343 REG_SET_5x38_4_1_H_MASK_ON(ch, param->h_mask_on);
344 REG_SET_5x38_0_4_H_MASK_SEL(ch, param->h_mask_sel);
345
346 REG_SET_0x64_0_8_V_BLK_END_B(ch, param->v_blk_end_b);
347 REG_SET_0x14_4_1_FLD_INV(ch, param->fld_inv);
348
349 REG_SET_5x64_0_8_MEM_RDP(ch, param->mem_rdp);
350 REG_SET_5x47_0_8_SYNC_RS(ch, param->sync_rs);
351 REG_SET_5xA9_0_8_V_BLK_END_B(ch, param->v_blk_end_b);
352
353 }
354
vd_vi_h_scaler_mode_set_seq6(unsigned char dev,unsigned char ch,void * p_param)355 void vd_vi_h_scaler_mode_set_seq6(unsigned char dev, unsigned char ch, void *p_param)
356 {
357 /*============================================================================================
358 * Bank 5x53
359 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
360 *| | | PROTECTION_OFF | BT_601_SEL | LINEMEM_MD | | C_DITHER_ON |
361 *============================================================================================*/
362 /*============================================================================================
363 * Bank 9x96
364 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
365 *| | | | CH1_H_DOWN_SCALER_EN | | | CH1_H_SCALER_TRS_SEL | CH1_H_SCALER_ENABLE |
366 *============================================================================================*/
367 /*============================================================================================
368 * Bank 9x97
369 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
370 *| CH1_H_SCALER_MODE | CH1_H_SCALER_RD_MODE | CH1_H_SCALER_AUTO_H_REF | CH1_H_SCALER_AUTO |
371 *============================================================================================*/
372 /*============================================================================================
373 * Bank 9x98
374 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
375 *| CH1_H_SCALER_H_REF_BASE[7:0] |
376 * Bank 9x99
377 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
378 *| CH1_H_SCALER_H_REF_BASE[15:8] |
379 *============================================================================================*/
380
381 NC_VD_VI_Init_STR *param = (NC_VD_VI_Init_STR *)p_param;
382
383 if (ch > 3) {
384 sensor_dbg("[DRV] %s CHID Error\n", __func__);
385 return;
386 }
387
388 REG_SET_5x53_2_2_LINEMEM_MD(ch, param->line_mem_mode);
389
390 REG_SET_9x96_0_8_H_DOWN_SCALER(ch, param->h_down_scaler);
391 REG_SET_9x97_0_8_H_SCALER_MODE(ch, param->h_scaler_mode);
392 REG_SET_9x98_0_8_REF_BASE_LSB(ch, param->ref_base_lsb);
393 REG_SET_9x99_0_8_REF_BASE_MSB(ch, param->ref_base_msb);
394 REG_SET_9x9E_0_8_H_SCALER_OUTPUT_H_ACTIVE(ch, param->h_scaler_active);
395 }
396
vd_vi_hpll_set_seq7(unsigned char dev,unsigned char ch,void * p_param)397 void vd_vi_hpll_set_seq7(unsigned char dev, unsigned char ch, void *p_param)
398 {
399 /*============================================================================================
400 * Bank 5x50
401 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
402 *| | NCO_GDF_COEFF_IV | | NCO_GDF_COEFF_OFF | Y_TEMP_SEL(5T,15T) | HPLL_MASK_ON | CONT_SUB |
403 *============================================================================================*/
404 /*============================================================================================
405 * Bank 5xb8
406 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
407 *| HAFC_BYPASS | HAFC_HCOEFF_SEL | HAFC_OP_MD |
408 *============================================================================================*/
409 /*============================================================================================
410 * Bank 5xbb
411 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
412 *| HPLL_MASK_END |
413 *============================================================================================*/
414 /*============================================================================================
415 * Bank 5xbb
416 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
417 *| HAFC_BYP_TH_S(write) |
418 *============================================================================================*/
419 NC_VD_VI_Init_STR *param = (NC_VD_VI_Init_STR *)p_param;
420
421 if (ch > 3) {
422 sensor_dbg("[DRV] %s CHID Error\n", __func__);
423 return;
424 }
425
426 REG_SET_5x50_0_8_HPLL_MASK_ON(ch, param->hpll_mask_on);
427 REG_SET_5xB8_0_8_HAFC_OP_MD(ch, param->hafc_op_md);
428 REG_SET_5xBB_0_8_HAFC_BYP_TH_E(ch, param->hafc_byp_th_e);
429 REG_SET_5xB7_0_8_HAFC_BYP_TH_S(ch, param->hafc_byp_th_s);
430
431 }
432
vd_vi_color_set_seq8(unsigned char dev,unsigned char ch,void * p_param,NC_VIVO_CH_FORMATDEF fmt)433 void vd_vi_color_set_seq8(unsigned char dev, unsigned char ch, void *p_param, NC_VIVO_CH_FORMATDEF fmt)
434 {
435 /*============================================================================================
436 * gpio_i2c_write(jaguar1_i2c_addr[dev], 0x22 + (ch*4), 0x0B ); // Raptor3
437 * Bank 0x5c
438 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
439 *| PAL_CM_OFF | | | COLOROFF | C_KILL |
440 *============================================================================================*/
441 /*============================================================================================
442 * Bank 5x26
443 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
444 *| FSC_LOCK_SENSE |
445 *============================================================================================*/
446 /*============================================================================================
447 * Bank 5xb8
448 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
449 *| HAFC_BYPASS | HAFC_HCOEFF_SEL | HAFC_OP_MD |
450 *============================================================================================*/
451 /*============================================================================================
452 * Bank 9x40
453 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
454 *| FSC_DET_ | FSC_DET_ | FSC_DET_ | FSC_DET_ | FSC_DET_ | FSC_DET_ | | FSC_RST_ |
455 *| AUTO_RST1 | UNLIM1 | AUTO1 | PRESET1 | MODE1 | REFER_AUTO1 | | STRB1 |
456 *============================================================================================*/
457
458 NC_VD_VI_Init_STR *param = (NC_VD_VI_Init_STR *)p_param;
459
460 REG_SET_0x20_0_8_BRIGHTNESS(ch, param->brightnees);
461 REG_SET_0x24_0_8_CONTARST(ch, param->contrast);
462 REG_SET_0x28_0_8_BLACK_LEVEL(ch, param->black_level);
463 REG_SET_0x58_0_8_SATURATION_A(ch, param->saturation_a);
464 REG_SET_0x40_0_8_HUE(ch, param->hue);
465 REG_SET_0x44_0_8_U_GAIN(ch, param->u_gain);
466 REG_SET_0x48_0_8_V_GAIN(ch, param->v_gain);
467 REG_SET_0x4C_0_8_U_OFFSET(ch, param->u_offset);
468 REG_SET_0x50_0_8_V_OFFSET(ch, param->v_offset);
469 REG_SET_5x2B_0_8_SATURATION_B(ch, param->saturation_b);
470 REG_SET_5x24_0_8_BURSET_DEC_A(ch, param->burst_dec_a);
471 REG_SET_5x5F_0_8_BURSET_DEC_B(ch, param->burst_dec_b);
472 REG_SET_5xD1_0_8_BURSET_DEC_C(ch, param->burst_dec_c);
473
474 REG_SET_9x44_0_8_FSC_EXT_EN(ch, 0x00);
475 REG_SET_9x50_0_8_FSC_EXT_VAL_7_0(ch, 0x30);
476 REG_SET_9x51_0_8_FSC_EXT_VAL_15_8(ch, 0x6f);
477 REG_SET_9x52_0_8_FSC_EXT_VAL_23_16(ch, 0x67);
478 REG_SET_9x53_0_8_FSC_EXT_VAL_31_24(ch, 0x48);
479
480 if (fmt == TVI_5M_12_5P) {
481 REG_SET_5x26_0_8_FSC_LOCK_SENSE(ch, 0x20);
482 } else
483 REG_SET_5x26_0_8_FSC_LOCK_SENSE(ch, 0x40);
484
485 if (fmt == AHD20_SD_H960_2EX_Btype_NT || fmt == AHD20_SD_H960_2EX_Btype_PAL) {
486 REG_SET_5xB8_0_8_HPLL_MASK_END(ch, 0xb8);
487 REG_SET_9x40_0_8_FSC_DET_MODE(ch, 0x00);
488 } else {
489 REG_SET_5xB8_0_8_HPLL_MASK_END(ch, 0x39);
490 REG_SET_9x40_0_8_FSC_DET_MODE(ch, 0x00);
491
492 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xff, 0x05 + ch);
493 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xb5, 0x80);
494 }
495
496 }
497
vd_vi_clock_set_seq9(unsigned char dev,unsigned char ch,void * p_param)498 void vd_vi_clock_set_seq9(unsigned char dev, unsigned char ch, void *p_param)
499 {
500 /*============================================================================================
501 * Bank 1x84
502 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
503 *| VADC_CLK1_DLY_SEL | VADC_CLK1_SEL |
504 *============================================================================================*/
505 /*============================================================================================
506 * Bank 1x88
507 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
508 *| | | | | | | DEC_PRECLK |
509 * Bank 1x8c
510 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
511 *| | | | | | | DEC_POSTCLK |
512 *============================================================================================*/
513 /*============================================================================================
514 * ADC -> PRE -> POST -> VCLK
515 * ADC_CLK 1x84[3:0]
516 * 0 ~ 3 : 37.125 MHz
517 * 4 ~ 5 : 74.25 MHz
518 * 8 ~ 9 : 148.5 MHz
519 * Pre_Clock 1x88 / Post Clock 1x8C
520 * 0 : 37.125
521 * 1 : 74.25
522 * 2 : 148.5
523 * VCLK 1xCC[7:4]
524 * 4 ~ 5 : 74.25 MHz
525 * 6 ~ 7 : 148.5 MHz
526 *============================================================================================*/
527
528 NC_VD_VI_Init_STR *param = (NC_VD_VI_Init_STR *)p_param;
529
530 REG_SET_1x84_0_8_CLK_ADC(ch, param->clk_adc);
531 REG_SET_1x88_0_8_CLK_PRE(ch, param->clk_pre);
532 REG_SET_1x8c_0_8_CLK_POST(ch, param->clk_post);
533
534 REG_SET_5x01_0_8_CML_MODE(ch, param->cml_mode);
535 REG_SET_5x05_0_8_AGC_OP(ch, param->agc_op);
536 REG_SET_5x1D_0_8_G_SEL(ch, param->g_sel);
537
538 }
539
540 //==================================================================================================================
541
542 /**************************************************************************************
543 * Jaguar1 Video Output Setting Function
544 *
545 *
546 ***************************************************************************************/
vd_vo_seq_set(unsigned char dev,unsigned char ch,void * p_param)547 void vd_vo_seq_set(unsigned char dev, unsigned char ch, void *p_param)
548 {
549 /*
550 * BT656 or BT1120 Set????...
551 * */
552 NC_VD_VO_Init_STR *param = (NC_VD_VO_Init_STR *)p_param;
553
554 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xFF, 0x01);
555 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xc0 + (ch * 0x02), param->port_seq_ch01[ch]);
556 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xc1 + (ch * 0x02), param->port_seq_ch23[ch]);
557
558 }
559
vd_vo_output_seq_set(unsigned char dev,unsigned char port,unsigned char out_ch)560 void vd_vo_output_seq_set(unsigned char dev, unsigned char port, unsigned char out_ch)
561 {
562 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xFF, 0x01);
563 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xc0 + (port * 0x02), out_ch);
564 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xc1 + (port * 0x02), out_ch);
565 }
566
vd_vo_port_y_c_merge_set(unsigned char dev,unsigned char ch,void * p_param)567 void vd_vo_port_y_c_merge_set(unsigned char dev, unsigned char ch, void *p_param)
568 {
569 NC_VD_VO_Init_STR *param = (NC_VD_VO_Init_STR *)p_param;
570
571 /*============================================================================================
572 * Address: 1xec
573 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
574 *| | | | | | | | MUX_YC_MERGE1 |
575 *============================================================================================*/
576 REG_SET_1xEC_0_8_yc_merge(ch, param->mux_yc_merge);
577
578 }
579
vd_vo_port_ch_id_set(unsigned char dev,unsigned char ch,void * p_param)580 void vd_vo_port_ch_id_set(unsigned char dev, unsigned char ch, void *p_param)
581 {
582 NC_VD_VO_Init_STR *param = (NC_VD_VO_Init_STR *)p_param;
583 unsigned char val_0x14 = 0x00;
584
585 /*============================================================================================
586 * Address: 0x14
587 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
588 *| | | | FLD_INV_1 | CHID_VIN1 |
589 *============================================================================================*/
590 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xFF, 0x00);
591 val_0x14 = gpio_i2c_read(jaguar1_i2c_addr[dev], 0x14 + ch);
592 val_0x14 = val_0x14 & 0x10;
593 val_0x14 = val_0x14 | param->chid_vin;
594 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x14 + ch, val_0x14);
595
596 }
597
vd_vo_mux_mode_set(unsigned char dev,unsigned char ch,void * p_param)598 void vd_vo_mux_mode_set(unsigned char dev, unsigned char ch, void *p_param)
599 {
600 NC_VD_VO_Init_STR *param = (NC_VD_VO_Init_STR *)p_param;
601
602 /*============================================================================================
603 * Address: 1xc8
604 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
605 *| | | VCLK_1_EN | VDO_1_EN | VPORT_1_CH_OUT_SEL |
606 *============================================================================================*/
607 REG_SET_1xC8_0_8_out_sel(ch, param->vport_out_sel);
608
609 }
610
vd_vo_manual_mode_set(unsigned char dev,unsigned char ch,void * p_param)611 void vd_vo_manual_mode_set(unsigned char dev, unsigned char ch, void *p_param)
612 {
613 unsigned char val_0x30;
614 unsigned char val_0x31;
615 unsigned char val_0x32;
616
617 /*============================================================================================
618 * Address: 13x30
619 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
620 *| | | | | NOVIDEO_VFC_INIT_EN[3:0] | | | |
621 *============================================================================================*/
622 /*============================================================================================
623 * Address: 13x31
624 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
625 *| | | AHD_8M_det_en | AHD_5M_det_en | AHD_4M_det_en | AHD_3M_det_en | AHD_2M_det_en | AHD_1M_det_en |
626 *============================================================================================*/
627 /*============================================================================================
628 * Address: 13x32
629 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
630 *| | | CVI_8M_det_en | CVI_5M_det_en | CVI_4M_det_en | CVI_3M_det_en | CVI_2M_det_en | CVI_1M_det_en |
631 *============================================================================================*/
632
633 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xFF, 0x13);
634 val_0x30 = gpio_i2c_read(jaguar1_i2c_addr[dev], 0x30);
635 val_0x31 = gpio_i2c_read(jaguar1_i2c_addr[dev], 0x31);
636 val_0x32 = gpio_i2c_read(jaguar1_i2c_addr[dev], 0x32);
637
638 val_0x30 &= (~(1 << (ch + 4)) & (~(1 << ch)));
639 val_0x31 &= (~(1 << (ch + 4)) & (~(1 << ch)));
640 val_0x32 &= (~(1 << ch));
641
642 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x30, val_0x30);
643 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x31, val_0x31);
644 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x32, val_0x32);
645
646 }
647
vd_jaguar1_single_differ_set(unsigned char dev,unsigned char ch,int input)648 void vd_jaguar1_single_differ_set(unsigned char dev, unsigned char ch, int input)
649 {
650 REG_SET_0x18_0_8_EX_CBAR_ON(ch, 0x13);
651
652 if (input == DIFFERENTIAL) {
653 REG_SET_5x00_0_8_CMP(ch, 0xd0);
654 REG_SET_5x01_0_8_CML(ch, 0x2c);
655 REG_SET_5x1D_0_8_AFE(ch, 0x8c);
656 REG_SET_5x92_0_8_PWM(ch, 0x00);
657 } else if (input == SINGLE_ENDED) {
658 REG_SET_5x00_0_8_CMP(ch, 0xd0);
659 REG_SET_5x01_0_8_CML(ch, 0xa2);
660 REG_SET_5x92_0_8_PWM(ch, 0x00);
661 } else {
662 printk("Jaguar1 Analog Input Setting Fail !!!\n");
663 }
664
665 }
666
vd_jaguar1_960p_30P_test_set(unsigned char dev,unsigned char ch)667 void vd_jaguar1_960p_30P_test_set(unsigned char dev, unsigned char ch)
668 {
669 printk("[drv]vd_jaguar1_960p_30P_test_set >>> ch%d!!\n", ch);
670 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xff, 0x00);
671 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x68 + ch, 0x4E);
672 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x69 + ch, 0x80);
673 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x6a + ch, 0x80);
674 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x6b + ch, 0x80);
675 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x04 + ch, 0x00);
676 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x08 + ch, 0x02);
677 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x0c + ch, 0x00);
678 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x18 + ch, 0x01);
679 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x64 + ch, 0x06);
680
681 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xff, 0x01);
682 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x84 + ch, 0x04);
683 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x88 + ch, 0x01);
684 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x8c + ch, 0x02);
685
686 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xff, 0x05 + ch);
687 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x6e, 0x10);
688 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x6f, 0x82);
689 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x76, 0x00);
690 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x77, 0x80);
691 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x78, 0x00);
692 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x79, 0x11);
693 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xB5, 0x80);
694
695 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xff, 0x11);
696 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x00 + (ch * 0x20), 0x0f);
697 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x01 + (ch * 0x20), 0x00);
698 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x02 + (ch * 0x20), 0x9d);
699 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x03 + (ch * 0x20), 0x05);
700 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x04 + (ch * 0x20), 0x00);
701 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x05 + (ch * 0x20), 0x08);
702 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x06 + (ch * 0x20), 0xca);
703 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x0a + (ch * 0x20), 0x03);
704 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x0b + (ch * 0x20), 0xc0);
705 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x0c + (ch * 0x20), 0x04);
706 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x0d + (ch * 0x20), 0x4b);
707 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x10 + (ch * 0x20), 0x00);
708 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x11 + (ch * 0x20), 0x96);
709 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x12 + (ch * 0x20), 0x00);
710 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x13 + (ch * 0x20), 0x82);
711 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x14 + (ch * 0x20), 0x00);
712 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x15 + (ch * 0x20), 0x30);
713
714 }
715
vd_jaguar1_960p_25P_test_set(unsigned char dev,unsigned char ch)716 void vd_jaguar1_960p_25P_test_set(unsigned char dev, unsigned char ch)
717 {
718 printk("[drv]vd_jaguar1_960p_25P_test_set >>> ch%d!!\n", ch);
719 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xff, 0x00);
720 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x68 + ch, 0x59);
721 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x69 + ch, 0x80);
722 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x6a + ch, 0x80);
723 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x6b + ch, 0x80);
724 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x04 + ch, 0x00);
725 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x08 + ch, 0x03);
726 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x0c + ch, 0x00);
727 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x18 + ch, 0x01);
728 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x64 + ch, 0x06);
729
730 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xff, 0x01);
731 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x84 + ch, 0x04);
732 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x88 + ch, 0x01);
733 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x8c + ch, 0x02);
734
735 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xff, 0x05 + ch);
736 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x6e, 0x10);
737 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x6f, 0x82);
738 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x76, 0x00);
739 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x77, 0x80);
740 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x78, 0x00);
741 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x79, 0x11);
742 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xB5, 0x80);
743
744 // Only AHD20_720P_960P_25P
745 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xff, 0x09);
746 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x53 + (ch * 0x04), 0x52);
747 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x52 + (ch * 0x04), 0xd2);
748 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x51 + (ch * 0x04), 0x1c);
749 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x50 + (ch * 0x04), 0x10);
750 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x44 + ch, 0x01);
751
752 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xff, 0x11);
753 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x00 + (ch * 0x20), 0x0f);
754 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x01 + (ch * 0x20), 0x00);
755 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x02 + (ch * 0x20), 0x97);
756 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x03 + (ch * 0x20), 0x05);
757 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x04 + (ch * 0x20), 0x00);
758 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x05 + (ch * 0x20), 0x0a);
759 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x06 + (ch * 0x20), 0x8c);
760 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x0a + (ch * 0x20), 0x03);
761 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x0b + (ch * 0x20), 0xc0);
762 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x0c + (ch * 0x20), 0x04);
763 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x0d + (ch * 0x20), 0x4c);
764 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x10 + (ch * 0x20), 0x00);
765 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x11 + (ch * 0x20), 0x96);
766 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x12 + (ch * 0x20), 0x00);
767 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x13 + (ch * 0x20), 0x82);
768 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x14 + (ch * 0x20), 0x00);
769 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x15 + (ch * 0x20), 0x30);
770
771 }
772
773 /*****************************************************************************************************************************************
774 * Jaguar1 Video ioctl function
775 * video vi_vo initialize
776 *
777 ******************************************************************************************************************************************/
vd_jaguar1_vo_ch_seq_set(void * p_param)778 void vd_jaguar1_vo_ch_seq_set(void *p_param)
779 {
780 video_output_init *vo_seq = (video_output_init *)p_param;
781 unsigned char dev = 0;
782 unsigned char port = vo_seq->port;
783 unsigned char out_ch = vo_seq->out_ch;
784
785 vd_vo_output_seq_set(dev, port, out_ch);
786 }
787
vd_jaguar1_init_set(void * p_param)788 void vd_jaguar1_init_set(void *p_param)
789 {
790 video_input_init *video_init = (video_input_init *)p_param;
791 unsigned char ch = video_init->ch % 4;
792 unsigned char fmt = video_init->format;
793 int analog_input = video_init->input;
794
795 video_equalizer_info_s eq_set;
796 NC_VD_COAX_STR coax_init;
797 NC_VD_VI_Init_STR *vi_param;
798 NC_VD_VO_Init_STR *vo_param;
799
800 int dev = ch / 4 ;
801
802 vi_param = __NC_VD_VI_Init_Val_Get(fmt);
803 vo_param = __NC_VD_VO_Init_Val_Get(AHD20_1080P_30P);
804
805 REG_SET_0x00_0_8_EACH_SET(ch, 0x10);
806 /*=====================================================
807 * vd_Analog Input Setting
808 *=====================================================*/
809 vd_jaguar1_single_differ_set(dev, ch, analog_input);
810
811 /*=====================================================
812 * vd_vo Setting
813 *=====================================================*/
814 vd_vo_port_y_c_merge_set(dev, ch, vo_param);
815 vd_vo_mux_mode_set(dev, ch, vo_param);
816 vd_vo_manual_mode_set(dev, ch, vo_param);
817
818 /*=====================================================
819 * vd_vi Setting
820 *=====================================================*/
821
822 vd_vi_manual_set_seq1(dev, ch, vi_param);
823 vd_vi_vafe_set_seq2(dev, ch);
824 vd_vi_format_set_seq3(dev, ch, vi_param);
825 vd_vi_chroma_set_seq4(dev, ch, vi_param);
826 vd_vi_h_timing_set_seq5(dev, ch, vi_param);
827 vd_vi_h_scaler_mode_set_seq6(dev, ch, vi_param);
828
829 vd_vi_hpll_set_seq7(dev, ch, vi_param);
830 vd_vi_color_set_seq8(dev, ch, vi_param, fmt);
831 vd_vo_port_ch_id_set(dev, ch, vo_param);
832 vd_vi_clock_set_seq9(dev, ch, vi_param);
833
834 /*=====================================================
835 * AHD 1280x960P Test
836 *
837 *=====================================================*/
838 if (fmt == AHD20_720P_960P_30P) {
839 vd_jaguar1_960p_30P_test_set(0, ch);
840 current_bank_set(0xFF);
841 } else if (fmt == AHD20_720P_960P_25P) {
842 vd_jaguar1_960p_25P_test_set(0, ch);
843 current_bank_set(0xFF);
844 } else if (fmt == AHD20_SD_H960_2EX_Btype_PAL) {
845 REG_SET_0x70_0_8_V_DELAY(ch, 0x3F);
846 } else if (fmt == AHD20_SD_SH720_PAL || fmt == AHD20_SD_SH720_NT || fmt == AHD20_SD_H1440_PAL || fmt == AHD20_SD_H1440_NT) {
847 REG_SET_0x14_0_8_FLD_INV_CHID(ch, 0x00);
848 REG_SET_0x34_0_8_Y_FIR_MODE(ch, 0x00);
849 REG_SET_1xCC_0_8_VPORT_OCLK_SEL_VPORT_OVCLK_DLY_SEL(ch, 0x40);
850 REG_SET_1xA0_0_8_TM_CLK_EN_SET(ch, 0x10);
851 REG_SET_5x21_0_8_CONT_SUB(ch, 0x24);
852 REG_SET_5x55_0_8_C_MEM_CLK_SEL(ch, 0x00);
853 REG_SET_5x56_0_8_FREQ_MEM_CLK_SEL(ch, 0x00);
854 REG_SET_5x57_0_8_LINE_MEM_CLK_INV(ch, 0x00);
855 REG_SET_5xB5_0_8_HAFC_MASK_SEL(ch, 0x00);
856 REG_SET_5xB8_0_8_HAFC_HCOEFF_SEL(ch, 0x39);
857 REG_SET_0x7C_0_8_HZOOM(ch, 0x8F);
858 } else
859 sensor_dbg("\n");
860
861 sensor_dbg("[drv_vi]ch::%d >>> fmt::%s\n", ch, vi_param->name);
862
863 /*=====================================================
864 * EQ Stage 0 Setting
865 *
866 *=====================================================*/
867 #if 1
868 eq_set.Ch = ch;
869 eq_set.FmtDef = fmt;
870 eq_set.Cable = CABLE_A;
871 eq_set.Input = SINGLE_ENDED;
872 eq_set.stage = STAGE_0;
873 video_input_eq_val_set(&eq_set);
874 #endif
875
876 sensor_dbg("[drv_vi]ch::%d >>> fmt::%s\n", ch, vi_param->name);
877 current_bank_set(0xFF);
878
879 /*=====================================================
880 * Coaxial Initialize
881 *
882 *=====================================================*/
883 coax_init.ch = ch;
884 coax_init.vivo_fmt = fmt;
885 coax_init.vd_dev = dev;
886 coax_tx_init(&coax_init);
887 if (bit8 == 0)
888 coax_tx_16bit_init(&coax_init);
889 coax_rx_init(&coax_init);
890
891 }
892
vd_jaguar1_get_novideo(video_video_loss_s * vidloss)893 void vd_jaguar1_get_novideo(video_video_loss_s *vidloss)
894 {
895 gpio_i2c_write(jaguar1_i2c_addr[vidloss->devnum], 0xFF, 0x00);
896 vidloss->videoloss = gpio_i2c_read(jaguar1_i2c_addr[vidloss->devnum], 0xA0);
897 }
898
vd_jaguar1_sw_reset(void * p_param)899 void vd_jaguar1_sw_reset(void *p_param)
900 {
901
902 REG_SET_1x81_0_1_VPLL_RST(0, 0x1);
903 REG_SET_1x80_0_1_VPLL_C(0, 0x1);
904 REG_SET_1x80_0_1_VPLL_C(0, 0x0);
905 REG_SET_1x81_0_1_VPLL_RST(0, 0x0);
906 sensor_dbg("[drv]jaguar1_sw_reset complete!!\n");
907 }
908
909