1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #ifndef __PHYDM_CCK_PD_H__ 27 #define __PHYDM_CCK_PD_H__ 28 29 /* 2019.12.25 decrease CS_ratio in 8822C due to Lenovo test result(PCIE-5136).*/ 30 #define CCK_PD_VERSION "4.0" 31 32 /*@ 33 * 1 ============================================================ 34 * 1 Definition 35 * 1 ============================================================ 36 */ 37 #define CCK_FA_MA_RESET 0xffffffff 38 39 #define INVALID_CS_RATIO_0 0x1b /* @ only for type4 ICs*/ 40 #define INVALID_CS_RATIO_1 0x1d /* @ only for type4 ICs*/ 41 #define MAXVALID_CS_RATIO 0x1f 42 /*@Run time flag of CCK_PD HW type*/ 43 #define CCK_PD_IC_TYPE1 (ODM_RTL8188E | ODM_RTL8812 | ODM_RTL8821 |\ 44 ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8814A |\ 45 ODM_RTL8881A | ODM_RTL8822B | ODM_RTL8703B |\ 46 ODM_RTL8195A | ODM_RTL8188F) 47 48 #define CCK_PD_IC_TYPE2 (ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8723D |\ 49 ODM_RTL8710B | ODM_RTL8195B) /*extend 0xaaa*/ 50 51 #define CCK_PD_IC_TYPE3 (ODM_RTL8192F | ODM_RTL8721D | ODM_RTL8710C) 52 /*@extend for different bw & path*/ 53 54 #define CCK_PD_IC_TYPE4 ODM_IC_JGR3_SERIES /*@extend for different bw & path*/ 55 #define CCK_PD_IC_TYPE5 (ODM_RTL8723F) /*@extend for different CR*/ 56 57 /*@Compile time flag of CCK_PD HW type*/ 58 #if (RTL8188E_SUPPORT || RTL8812A_SUPPORT || RTL8821A_SUPPORT ||\ 59 RTL8192E_SUPPORT || RTL8723B_SUPPORT || RTL8814A_SUPPORT ||\ 60 RTL8881A_SUPPORT || RTL8822B_SUPPORT || RTL8703B_SUPPORT ||\ 61 RTL8195A_SUPPORT || RTL8188F_SUPPORT) 62 #define PHYDM_COMPILE_CCKPD_TYPE1 /*@only 0xa0a*/ 63 #endif 64 65 #if (RTL8197F_SUPPORT || RTL8821C_SUPPORT || RTL8723D_SUPPORT ||\ 66 RTL8710B_SUPPORT || RTL8195B_SUPPORT) 67 #define PHYDM_COMPILE_CCKPD_TYPE2 /*@extend 0xaaa*/ 68 #endif 69 70 #if (RTL8192F_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT) 71 #define PHYDM_COMPILE_CCKPD_TYPE3 /*@extend for different & path*/ 72 #endif 73 74 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT 75 #define PHYDM_COMPILE_CCKPD_TYPE4 /*@extend for different bw & path*/ 76 #endif 77 #if (RTL8723F_SUPPORT) 78 #define PHYDM_COMPILE_CCKPD_TYPE5 /*@extend for different & path*/ 79 #endif 80 81 /*@ 82 * 1 ============================================================ 83 * 1 enumeration 84 * 1 ============================================================ 85 */ 86 enum cckpd_lv { 87 CCK_PD_LV_INIT = 0xff, 88 CCK_PD_LV_0 = 0, 89 CCK_PD_LV_1 = 1, 90 CCK_PD_LV_2 = 2, 91 CCK_PD_LV_3 = 3, 92 CCK_PD_LV_4 = 4, 93 CCK_PD_LV_MAX = 5 94 }; 95 96 enum cckpd_mode { 97 CCK_BW20_1R = 0, 98 CCK_BW20_2R = 1, 99 CCK_BW20_3R = 2, 100 CCK_BW20_4R = 3, 101 CCK_BW40_1R = 4, 102 CCK_BW40_2R = 5, 103 CCK_BW40_3R = 6, 104 CCK_BW40_4R = 7 105 }; 106 107 enum dcc_mode { 108 DCC_DIG = 0, 109 DCC_CCK_PD = 1 110 }; 111 112 enum phydm_cck_pd_trend { 113 CCKPD_STABLE = 0, 114 CCKPD_INCREASING = 1, 115 CCKPD_DECREASING = 2 116 }; 117 118 /*@ 119 * 1 ============================================================ 120 * 1 structure 121 * 1 ============================================================ 122 */ 123 124 #ifdef PHYDM_SUPPORT_CCKPD 125 126 #ifdef PHYDM_DCC_ENHANCE 127 struct phydm_dcc_struct { /*DIG CCK_PD coexistence*/ 128 boolean dcc_en; 129 enum dcc_mode dcc_mode; 130 u32 dig_execute_cnt; 131 u8 dcc_ratio; 132 }; 133 #endif 134 135 struct phydm_cckpd_struct { 136 u8 cckpd_hw_type; 137 u8 cur_cck_cca_thres; /*@current cck_pd value 0xa0a*/ 138 u32 cck_fa_ma; 139 u32 rvrt_val; /*all rvrt_val for pause API must set to u32*/ 140 u8 pause_lv; 141 u8 cck_n_rx; 142 u16 cck_fa_th[2]; 143 enum channel_width cck_bw; 144 enum cckpd_lv cck_pd_lv; 145 #ifdef PHYDM_COMPILE_CCKPD_TYPE2 146 u8 cck_cca_th_aaa; /*@current cs_ratio value 0xaaa*/ 147 u8 aaa_default; /*@Init cs_ratio value - 0xaaa*/ 148 #endif 149 #ifdef PHYDM_COMPILE_CCKPD_TYPE3 150 /*Default value*/ 151 u8 cck_pd_20m_1r; 152 u8 cck_pd_20m_2r; 153 u8 cck_pd_40m_1r; 154 u8 cck_pd_40m_2r; 155 u8 cck_cs_ratio_20m_1r; 156 u8 cck_cs_ratio_20m_2r; 157 u8 cck_cs_ratio_40m_1r; 158 u8 cck_cs_ratio_40m_2r; 159 u8 cck_din_shift_opt; 160 /*Current value*/ 161 u8 cur_cck_pd_20m_1r; 162 u8 cur_cck_pd_20m_2r; 163 u8 cur_cck_pd_40m_1r; 164 u8 cur_cck_pd_40m_2r; 165 u8 cur_cck_cs_ratio_20m_1r; 166 u8 cur_cck_cs_ratio_20m_2r; 167 u8 cur_cck_cs_ratio_40m_1r; 168 u8 cur_cck_cs_ratio_40m_2r; 169 #endif 170 #ifdef PHYDM_COMPILE_CCKPD_TYPE4 171 /*@[bw][nrx][0:PD/1:CS][lv]*/ 172 u8 cckpd_jgr3[2][4][2][CCK_PD_LV_MAX]; 173 #endif 174 #ifdef PHYDM_COMPILE_CCKPD_TYPE5 175 /*@[bw][nrx][0:PD/1:CS][lv]*/ 176 u8 cck_pd_table_jgr3[2][4][2][CCK_PD_LV_MAX]; 177 #endif 178 }; 179 #endif 180 181 /*@ 182 * 1 ============================================================ 183 * 1 function prototype 184 * 1 ============================================================ 185 */ 186 void phydm_set_cckpd_val(void *dm_void, u32 *val_buf, u8 val_len); 187 188 void phydm_cck_pd_th(void *dm_void); 189 190 void phydm_cck_pd_init(void *dm_void); 191 192 #ifdef PHYDM_DCC_ENHANCE 193 void phydm_cckpd_type4_dcc(void *dm_void); 194 195 void phydm_dig_cckpd_coex(void *dm_void); 196 197 void phydm_dig_cckpd_coex_init(void *dm_void); 198 199 void phydm_dig_cckpd_coex_dbg(void *dm_void, char input[][16], u32 *_used, 200 char *output, u32 *_out_len); 201 #endif 202 #endif 203