1 // Copyright (C) 2022 Beken Corporation 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #pragma once 16 17 #include <soc/soc.h> 18 #include "system_hw.h" 19 #include "sys_ll_macro_def.h" 20 21 #ifdef __cplusplus 22 extern "C" { 23 #endif 24 25 //int_0_31_en DIRTY define 26 #define BMC32_INTERRUPT_CTRL_BIT (1 << SYS_CPU0_INT_0_31_EN_CPU0_BMC32_INT_EN_POS) 27 #define HOST_0_INTERRUPT_CTRL_BIT (1 << SYS_CPU0_INT_0_31_EN_CPU0_HOST_0_IRQ_EN_POS) 28 #define HOST_0_SEC_INTERRUPT_CTRL_BIT (1 << SYS_CPU0_INT_0_31_EN_CPU0_HOST_0_SEC_IRQ_EN_POS) 29 #define TIMER_INTERRUPT_CTRL_BIT (1 << SYS_CPU0_INT_0_31_EN_CPU0_TIMER_INT_EN_POS) 30 #define UART0_INTERRUPT_CTRL_BIT (1 << SYS_CPU0_INT_0_31_EN_CPU0_UART_INT_EN_POS) 31 #define PWM_INTERRUPT_CTRL_BIT (1 << SYS_CPU0_INT_0_31_EN_CPU0_PWM_INT_EN_POS) 32 #define I2C_INTERRUPT_CTRL_BIT (1 << SYS_CPU0_INT_0_31_EN_CPU0_I2C1_INT_EN_POS) 33 #define SPI_INTERRUPT_CTRL_BIT (1 << SYS_CPU0_INT_0_31_EN_CPU0_SPI_INT_EN_POS) 34 #define SADC_INTERRUPT_CTRL_BIT (1 << SYS_CPU0_INT_0_31_EN_CPU0_SADC_INT_EN_POS) 35 #define IRDA_INTERRUPT_CTRL_BIT (1 << SYS_CPU0_INT_0_31_EN_CPU0_IRDA_INT_EN_POS) 36 #define SDIO_INTERRUPT_CTRL_BIT (1 << SYS_CPU0_INT_0_31_EN_CPU0_SDIO_INT_EN_POS) 37 #define GDMA_INTERRUPT_CTRL_BIT (1 << SYS_CPU0_INT_0_31_EN_CPU0_GDMA_INT_EN_POS) 38 #define LA_INTERRUPT_CTRL_BIT (1 << SYS_CPU0_INT_0_31_EN_CPU0_LA_INT_EN_POS) 39 #define TIMER1_INTERRUPT_CTRL_BIT (1 << SYS_CPU0_INT_0_31_EN_CPU0_TIMER1_INT_EN_POS) 40 #define I2C1_INTERRUPT_CTRL_BIT (1 << SYS_CPU0_INT_0_31_EN_CPU0_I2C_INT_EN_POS) 41 #define UART1_INTERRUPT_CTRL_BIT (1 << SYS_CPU0_INT_0_31_EN_CPU0_UART1_INT_EN_POS) 42 #define UART2_INTERRUPT_CTRL_BIT (1 << SYS_CPU0_INT_0_31_EN_CPU0_UART2_INT_EN_POS) 43 #define SPI1_INTERRUPT_CTRL_BIT (1 << SYS_CPU0_INT_0_31_EN_CPU0_SPI1_INT_EN_POS) 44 #define CAN_INTERRUPT_CTRL_BIT (1 << SYS_CPU0_INT_0_31_EN_CPU0_CAN_INT_EN_POS) 45 #define USB_INTERRUPT_CTRL_BIT (1 << SYS_CPU0_INT_0_31_EN_CPU0_USB_INT_EN_POS) 46 #define QSPI_INTERRUPT_CTRL_BIT (1 << SYS_CPU0_INT_0_31_EN_CPU0_QSPI_INT_EN_POS) 47 #define FFT_INTERRUPT_CTRL_BIT (1 << SYS_CPU0_INT_0_31_EN_CPU0_FFT_INT_EN_POS) 48 #define SBC_INTERRUPT_CTRL_BIT (1 << SYS_CPU0_INT_0_31_EN_CPU0_SBC_INT_EN_POS) 49 #define AUD_INTERRUPT_CTRL_BIT (1 << SYS_CPU0_INT_0_31_EN_CPU0_AUD_INT_EN_POS) 50 #define I2S_INTERRUPT_CTRL_BIT (1 << SYS_CPU0_INT_0_31_EN_CPU0_I2S_INT_EN_POS) 51 #define JPEGENC_INTERRUPT_CTRL_BIT (1 << SYS_CPU0_INT_0_31_EN_CPU0_JPEGENC_INT_EN_POS) 52 #define JPEGDEC_INTERRUPT_CTRL_BIT (1 << SYS_CPU0_INT_0_31_EN_CPU0_JPEGDEC_INT_EN_POS) 53 #define LCD_INTERRUPT_CTRL_BIT (1 << SYS_CPU0_INT_0_31_EN_CPU0_LCD_INT_EN_POS) 54 #define WIFI_MODEM_EN (1 << SYS_CPU0_INT_0_31_EN_CPU0_WIFI_INT_PHY_MPB_EN_POS) 55 #define WIFI_MODEM_RC_EN (1 << SYS_CPU0_INT_0_31_EN_CPU0_WIFI_INT_PHY_RIU_EN_POS) 56 #define WIFI_MAC_TX_RX_TIMER_INT_BIT (1 << SYS_CPU0_INT_0_31_EN_CPU0_WIFI_MAC_INT_TX_RX_TIMER_EN_POS) 57 58 //int_32_63_en 59 #define WIFI_MAC_TX_RX_MISC_INT_BIT (1 << SYS_CPU0_INT_32_63_EN_CPU0_WIFI_MAC_INT_TX_RX_MISC_EN_POS) 60 #define WIFI_MAC_RX_TRIGGER_INT_BIT (1 << SYS_CPU0_INT_32_63_EN_CPU0_WIFI_MAC_INT_RX_TRIGGER_EN_POS) 61 #define WIFI_MAC_TX_TRIGGER_INT_BIT (1 << SYS_CPU0_INT_32_63_EN_CPU0_WIFI_MAC_INT_TX_TRIGGER_EN_POS) 62 #define WIFI_MAC_PORT_TRIGGER_INT_BIT (1 << SYS_CPU0_INT_32_63_EN_CPU0_WIFI_MAC_PORT_TRIGGER_EN_POS) 63 #define WIFI_MAC_GEN_INT_BIT (1 << SYS_CPU0_INT_32_63_EN_CPU0_WIFI_MAC_INT_GEN_EN_POS) 64 #define WIFI_HSU_INTERRUPT_CTRL_BIT (1 << SYS_CPU0_INT_32_63_EN_CPU0_WIFI_HSU_IRQ_EN_POS) 65 #define WIFI_MAC_WAKEUP_INT_BIT (1 << SYS_CPU0_INT_32_63_EN_CPU0_WIFI_INT_MAC_WAKEUP_EN_POS) 66 #define DM_INTERRUPT_CTRL_BIT (1 << SYS_CPU0_INT_32_63_EN_CPU0_DM_IRQ_EN_POS) 67 #define BLE_INTERRUPT_CTRL_BIT (1 << SYS_CPU0_INT_32_63_EN_CPU0_BLE_IRQ_EN_POS) 68 #define BT_INTERRUPT_CTRL_BIT (1 << SYS_CPU0_INT_32_63_EN_CPU0_BT_IRQ_EN_POS) 69 #define MBOX0_INTERRUPT_CTRL_BIT (1 << SYS_CPU0_INT_32_63_EN_CPU0_MBOX0_INT_EN_POS) 70 #define MBOX1_INTERRUPT_CTRL_BIT (1 << SYS_CPU0_INT_32_63_EN_CPU0_MBOX1_INT_EN_POS) 71 #define BMC64_INTERRUPT_CTRL_BIT (1 << SYS_CPU0_INT_32_63_EN_CPU0_BMC64_INT_EN_POS) 72 #define TOUCHED_INTERRUPT_CTRL_BIT (1 << SYS_CPU0_INT_32_63_EN_CPU0_TOUCHED_INT_EN_POS) 73 #define USBPLUG_INTERRUPT_CTRL_BIT (1 << SYS_CPU0_INT_32_63_EN_CPU0_USBPLUG_INT_EN_POS) 74 #define RTC_INTERRUPT_CTRL_BIT (1 << SYS_CPU0_INT_32_63_EN_CPU0_RTC_INT_EN_POS) 75 #define GPIO_INTERRUPT_CTRL_BIT (1 << SYS_CPU0_INT_32_63_EN_CPU0_GPIO_INT_EN_POS) 76 77 #define RTC_TICKS_PER_1MS (32) 78 #define LOW_POWER_DPLL_STABILITY_DELAY_TIME (0.5) // 0.5ms 79 #define LOW_POWER_XTAL_26M_STABILITY_DELAY_TIME_HARDWARE (0.4) // ~0.4ms(the delay time config into hardware 2+2+2+4 = 10 tick = 1/32 * 10 ms) 80 #define LOW_POWER_XTAL_DPLL_STABILITY_DELAY_TIME ((LOW_POWER_XTAL_26M_STABILITY_DELAY_TIME_HARDWARE+LOW_POWER_DPLL_STABILITY_DELAY_TIME)*1000) 81 82 typedef enum 83 { 84 UART_CLK_DIV_1 = 0, 85 UART_CLK_DIV_2, 86 UART_CLK_DIV_4, 87 UART_CLK_DIV_8, 88 }uart_clk_div_t; 89 90 typedef enum 91 { 92 FLASH_CLK_XTAL = 0, 93 FLASH_CLK_DPLL, 94 FLASH_CLK_APLL, 95 }flash_clk_src_t; 96 97 /*clock power control start*/ 98 /* 99 clock power enable for periphral unit 100 0xc[0],1:i2c0_clk enable,0,R/W 101 0xc[1],1:spi0_clk enable ,0,R/W 102 0xc[2],1:uart0_clk enable,0,R/W 103 0xc[3],1:pwm0_clk enable ,0,R/W 104 0xc[4],1:tim0_clk enable ,0,R/W 105 0xc[5],1:sadc_clk enable ,0,R/W 106 0xc[6],1:irda_clk enable ,0,R/W 107 0xc[7],1:efuse_clk enable,0,R/W 108 0xc[8],1:i2c1_clk enable ,0,R/W 109 0xc[9],1:spi1_clk enable ,0,R/W 110 0xc[10],1:uart1_clk enable,0,R/W 111 0xc[11],1:uart2_clk enable,0,R/W 112 0xc[12],1:pwm1_clk enable ,0,R/W 113 0xc[13],1:tim1_clk enable ,0,R/W 114 0xc[14],1:tim2_clk enable ,0,R/W 115 0xc[15],1:otp_clk enable ,1,R/W 116 0xc[16],1:i2s_clk enable ,0,R/W 117 0xc[17],1:usb_clk enable ,0,R/W 118 0xc[18],1:can_clk enable ,0,R/W 119 0xc[19],1:psram_clk enable,0,R/W 120 0xc[20],1:qspi0_clk enable,0,R/W 121 0xc[21],1:qspi1_clk enable,0,R/W 122 0xc[22],1:sdio_clk enable ,0,R/W 123 0xc[23],1:auxs_clk enable ,0,R/W 124 0xc[24],1:btdm_clk enable ,0,R/W 125 0xc[25],1:xvr_clk enable ,0,R/W 126 0xc[26],1:mac_clk enable ,0,R/W 127 0xc[27],1:phy_clk enable ,0,R/W 128 0xc[28],1:jpeg_clk enable ,0,R/W 129 0xc[29],1:disp_clk enable ,0,R/W 130 0xc[30],1:aud_clk enable ,0,R/W 131 0xc[31],1:wdt_clk enable ,0,R/W 132 */ 133 typedef enum //SYS TYPES index is from 1~X 134 { 135 CLK_PWR_ID_I2C2 = 0, 136 CLK_PWR_ID_SPI_1, 137 CLK_PWR_ID_UART1, 138 CLK_PWR_ID_PWM_1, 139 CLK_PWR_ID_TIMER_1, 140 CLK_PWR_ID_SARADC, 141 CLK_PWR_ID_IRDA, 142 CLK_PWR_ID_EFUSE, 143 CLK_PWR_ID_I2C1, 144 CLK_PWR_ID_SPI_2, 145 CLK_PWR_ID_UART2, 146 CLK_PWR_ID_UART3, 147 CLK_PWR_ID_PWM_2, 148 CLK_PWR_ID_TIMER_2, 149 CLK_PWR_ID_TIMER_3, 150 CLK_PWR_ID_OTP, 151 CLK_PWR_ID_I2S_1, 152 CLK_PWR_ID_USB_1, 153 CLK_PWR_ID_CAN, 154 CLK_PWR_ID_PSRAM, 155 CLK_PWR_ID_QSPI_1, 156 CLK_PWR_ID_QSPI_2, 157 CLK_PWR_ID_SDIO, 158 CLK_PWR_ID_AUXS, 159 CLK_PWR_ID_BTDM, 160 CLK_PWR_ID_XVR, 161 CLK_PWR_ID_MAC, 162 CLK_PWR_ID_PHY, 163 CLK_PWR_ID_JPEG, 164 CLK_PWR_ID_DISP, 165 CLK_PWR_ID_AUDIO, 166 CLK_PWR_ID_WDG_CPU, 167 168 CLK_PWR_ID_NONE 169 }dev_clk_pwr_id_t; 170 171 typedef enum 172 { 173 CLK_PWR_CTRL_PWR_DOWN = 0, 174 CLK_PWR_CTRL_PWR_UP, 175 }dev_clk_pwr_ctrl_t; 176 177 /* 178 clock select for periphral unit 179 */ 180 typedef enum //Just for temp build 181 { 182 CLK_SEL_ID_CORE = 4, 183 }dev_clk_select_id_t; 184 185 typedef enum 186 { 187 CLK_SEL_DCO = 0, 188 CLK_SEL_XTL_26M, 189 }dev_clk_select_t; 190 191 typedef enum 192 { 193 CLK_DCO_DIV_1 = 0, 194 CLK_DCO_DIV_2, 195 CLK_DCO_DIV_4, 196 CLK_DCO_DIV_8 197 }dev_clk_dco_div_t; 198 199 200 /*clock power control end*/ 201 202 /*power domain ctrl modules*/ 203 typedef enum 204 { 205 POWER_MODULE_NAME_MEM1 = 0, 206 POWER_MODULE_NAME_MEM2, 207 POWER_MODULE_NAME_MEM3, 208 POWER_MODULE_NAME_ENCP, 209 POWER_MODULE_NAME_BAKP, 210 POWER_MODULE_NAME_AHBP, 211 POWER_MODULE_NAME_AUDP, 212 POWER_MODULE_NAME_VIDP, 213 POWER_MODULE_NAME_BTSP, //8 214 POWER_MODULE_NAME_WIFIP_MAC, //9 215 POWER_MODULE_NAME_WIFI_PHY, 216 POWER_MODULE_NAME_CPU1 , //11 217 POWER_MODULE_NAME_APP , //12 218 POWER_MODULE_NAME_NONE 219 }power_module_name_t; 220 typedef enum 221 { 222 POWER_MODULE_STATE_ON = 0, 223 POWER_MODULE_STATE_OFF, 224 POWER_MODULE_STATE_NONE 225 }power_module_state_t; 226 typedef enum 227 { 228 POWER_MODULE_STATE_LOWVOL_ON = 0, 229 POWER_MODULE_STATE_LOWVOL_OFF, 230 POWER_MODULE_STATE_LOWVOL_NONE 231 }lowvol_module_state_t; 232 typedef enum 233 { 234 ENTER_DEEP_SLEEP_DISABLE = 0, 235 ENTER_DEEP_SLEEP_ENABLE, 236 ENTER_DEEP_SLEEP_NONE 237 }enter_deepsleep_state_t; 238 typedef enum 239 { 240 ENTER_LOW_VOLTAGE_DISABLE = 0, 241 ENTER_LOW_VOLTAGE_ENABLE, 242 ENTER_LOW_VOLTAGE_NONE 243 }enter_lowvoltage_state_t; 244 245 /*RF using owner modules*/ 246 typedef enum 247 { 248 MODULE_NAME_WIFI = 0, 249 MODULE_NAME_BT, 250 MODULE_NAME_NONE 251 }module_name_t; 252 typedef enum 253 { 254 HIGH_FREQUECY_CLOCK_MODULE_CPU0 = 0, 255 HIGH_FREQUECY_CLOCK_MODULE_CPU1, 256 HIGH_FREQUECY_CLOCK_MODULE_CPU0_MATRIX, 257 HIGH_FREQUECY_CLOCK_MODULE_CPU1_MATRIX, 258 HIGH_FREQUECY_CLOCK_MODULE_SDIO, 259 HIGH_FREQUECY_CLOCK_MODULE_QSPI, 260 HIGH_FREQUECY_CLOCK_MODULE_PSRAM, 261 HIGH_FREQUECY_CLOCK_MODULE_DISP, 262 HIGH_FREQUECY_CLOCK_MODULE_JPEG, 263 HIGH_FREQUECY_CLOCK_MODULE_FLASH, 264 HIGH_FREQUECY_CLOCK_MODULE_USB, 265 HIGH_FREQUECY_CLOCK_MODULE_NONE 266 }high_clock_module_name_t; 267 typedef enum 268 { 269 WAKEUP_SOURCE_INT_GPIO = 0, 270 WAKEUP_SOURCE_INT_RTC , 271 WAKEUP_SOURCE_INT_SYSTEM_WAKE , 272 WAKEUP_SOURCE_INT_USBPLUG , 273 WAKEUP_SOURCE_INT_TOUCHED , 274 WAKEUP_SOURCE_INT_NONE , 275 }wakeup_source_t; 276 277 typedef enum 278 { 279 CHARGE_STEP1 = 0, 280 CHARGE_STEP2, 281 CHARGE_STEP3, 282 CHARGE_STEP4, 283 } sys_drv_charge_step_t; 284 typedef enum 285 { 286 ANALOG_REG0 = 0, 287 ANALOG_REG1, 288 ANALOG_REG2, 289 ANALOG_REG3, 290 ANALOG_REG4, 291 ANALOG_REG5, 292 ANALOG_REG6, 293 ANALOG_REG7, 294 ANALOG_REG8, 295 ANALOG_REG9, 296 ANALOG_REG10, 297 ANALOG_REG11, 298 ANALOG_REG12, 299 ANALOG_REG13, 300 ANALOG_REG14, 301 ANALOG_REG15, 302 ANALOG_REG16, 303 ANALOG_REG17, 304 ANALOG_REG18, 305 ANALOG_REG19, 306 ANALOG_NONE 307 } analog_reg_t; 308 #define ANALOG_ADDRESS_MAP \ 309 { \ 310 {ANALOG_REG0, SYS_ANA_REG0_ADDR, }, \ 311 {ANALOG_REG1, SYS_ANA_REG1_ADDR, }, \ 312 {ANALOG_REG2, SYS_ANA_REG2_ADDR, }, \ 313 {ANALOG_REG3, SYS_ANA_REG3_ADDR, }, \ 314 {ANALOG_REG4, SYS_ANA_REG4_ADDR, }, \ 315 {ANALOG_REG5, SYS_ANA_REG5_ADDR, }, \ 316 {ANALOG_REG6, SYS_ANA_REG6_ADDR, }, \ 317 {ANALOG_REG7, SYS_ANA_REG7_ADDR, }, \ 318 {ANALOG_REG8, SYS_ANA_REG8_ADDR, }, \ 319 {ANALOG_REG9, SYS_ANA_REG9_ADDR, }, \ 320 {ANALOG_REG10, SYS_ANA_REG10_ADDR, }, \ 321 {ANALOG_REG11, SYS_ANA_REG11_ADDR, }, \ 322 {ANALOG_REG12, SYS_ANA_REG12_ADDR, }, \ 323 {ANALOG_REG13, SYS_ANA_REG13_ADDR, }, \ 324 {ANALOG_REG14, SYS_ANA_REG14_ADDR, }, \ 325 {ANALOG_REG15, SYS_ANA_REG15_ADDR, }, \ 326 {ANALOG_REG16, SYS_ANA_REG16_ADDR, }, \ 327 {ANALOG_REG17, SYS_ANA_REG17_ADDR, }, \ 328 {ANALOG_REG18, SYS_ANA_REG18_ADDR, }, \ 329 {ANALOG_REG19, SYS_ANA_REG19_ADDR, }, \ 330 } 331 typedef struct { 332 analog_reg_t analog_reg; 333 uint32_t analog_reg_address; 334 } analog_address_map_t; 335 336 typedef enum 337 { 338 CLK_DIV_REG0 = 0, 339 CLK_DIV_REG1, 340 CLK_DIV_REG2, 341 CLK_DIV_NONE 342 } clk_div_reg_e; 343 #define CLK_DIV_ADDRESS_MAP \ 344 { \ 345 {CLK_DIV_REG0, SYS_CPU_CLK_DIV_MODE1_ADDR, }, \ 346 {CLK_DIV_REG1, SYS_CPU_CLK_DIV_MODE2_ADDR, }, \ 347 {CLK_DIV_REG2, SYS_CPU_26M_WDT_CLK_DIV_ADDR, }, \ 348 } 349 typedef struct { 350 clk_div_reg_e clk_div_reg; 351 uint32_t reg_address; 352 } clk_div_address_map_t; 353 typedef enum 354 { 355 PMU_REG0 = 0, 356 PMU_REG1, 357 PMU_REG2, 358 PMU_REG3, 359 PMU_REG0x40, 360 PMU_REG0x41, 361 PMU_REG0x42, 362 PMU_REG0x43, 363 PMU_REG0x70, 364 PMU_REG0x71, 365 PMU_NONE 366 } pmu_reg_e; 367 #define PMU_ADDRESS_MAP \ 368 { \ 369 {PMU_REG0, AON_PMU_REG0_ADDR, }, \ 370 {PMU_REG1, AON_PMU_REG1_ADDR, }, \ 371 {PMU_REG2, AON_PMU_REG2_ADDR, }, \ 372 {PMU_REG3, AON_PMU_REG3_ADDR, }, \ 373 {PMU_REG0x40, AON_PMU_REG40_ADDR, }, \ 374 {PMU_REG0x41, AON_PMU_REG41_ADDR, }, \ 375 {PMU_REG0x42, AON_PMU_REG42_ADDR, }, \ 376 {PMU_REG0x43, AON_PMU_REG43_ADDR, }, \ 377 {PMU_REG0x70, AON_PMU_REG70_ADDR, }, \ 378 {PMU_REG0x71, AON_PMU_REG71_ADDR, }, \ 379 } 380 typedef struct { 381 pmu_reg_e pmu_reg; 382 uint32_t reg_address; 383 }pmu_address_map_t; 384 385 386 typedef enum 387 { 388 BIT_SLEEP_FLAG_DEEP_SLEEP = 16, 389 BIT_SLEEP_FLAG_LOW_VOLTAGE , 390 BIT_SLEEP_FLAG_NONE 391 } bit_sleep_flag_e; 392 393 typedef enum 394 { 395 SARADC_CLK_SRC_XTAL = 0, 396 SARADC_CLK_SRC_APLL, 397 SARADC_CLK_SRC_UNKNOW = 0xff 398 } sys_saradc_clk_sel_t; 399 400 typedef enum 401 { 402 SPI_CLK_SRC_XTAL = 0, 403 SPI_CLK_SRC_APLL, 404 SPI_CLK_SRC_UNKNOW = 0xff 405 } sys_spi_clk_sel_t; 406 407 typedef enum 408 { 409 PWM_CLK_SRC_32K = 0, 410 PWM_CLK_SRC_XTAL, 411 PWM_CLK_SRC_UNKNOW = 0xff 412 } sys_pwm_clk_sel_t; 413 414 typedef enum 415 { 416 LOW_POWER_MODE_NORMAL_SLEEP = 0, 417 LOW_POWER_MODE_LOW_VOLTAGE , 418 LOW_POWER_DEEP_SLEEP , 419 LOW_POWER_MODE_NONE 420 }low_power_sleep_mode_e; 421 #ifdef __cplusplus 422 } 423 #endif 424