1 /*
2 * linux-5.4/drivers/media/platform/sunxi-vin/vin-mipi/dphy/dphy_reg.c
3 *
4 * Copyright (c) 2007-2017 Allwinnertech Co., Ltd.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17 /*
18 * sunxi mipi dphy low-level interface
19 * Author:raymonxiu
20 */
21
22 #include <linux/delay.h>
23 #include "dphy.h"
24 #include "dphy_reg_i.h"
25 #include "dphy_reg.h"
26
27 DPHY_CTL_REG_t *dphy_ctl[MAX_MIPI_DPHY];
28 DPHY_TX_CTL_REG_t *dphy_tx_ctl[MAX_MIPI_DPHY];
29 DPHY_RX_CTL_REG_t *dphy_rx_ctl[MAX_MIPI_DPHY];
30 DPHY_TX_TIME0_REG_t *dphy_tx_time0[MAX_MIPI_DPHY];
31 DPHY_TX_TIME1_REG_t *dphy_tx_time1[MAX_MIPI_DPHY];
32 DPHY_TX_TIME2_REG_t *dphy_tx_time2[MAX_MIPI_DPHY];
33 DPHY_TX_TIME3_REG_t *dphy_tx_time3[MAX_MIPI_DPHY];
34 DPHY_TX_TIME4_REG_t *dphy_tx_time4[MAX_MIPI_DPHY];
35 DPHY_RX_TIME0_REG_t *dphy_rx_time0[MAX_MIPI_DPHY];
36 DPHY_RX_TIME1_REG_t *dphy_rx_time1[MAX_MIPI_DPHY];
37 DPHY_RX_TIME2_REG_t *dphy_rx_time2[MAX_MIPI_DPHY];
38 DPHY_RX_TIME3_REG_t *dphy_rx_time3[MAX_MIPI_DPHY];
39 DPHY_ANA0_REG_t *dphy_ana0[MAX_MIPI_DPHY];
40 DPHY_ANA1_REG_t *dphy_ana1[MAX_MIPI_DPHY];
41 DPHY_ANA2_REG_t *dphy_ana2[MAX_MIPI_DPHY];
42 DPHY_ANA3_REG_t *dphy_ana3[MAX_MIPI_DPHY];
43 DPHY_ANA4_REG_t *dphy_ana4[MAX_MIPI_DPHY];
44 DPHY_INT_EN0_REG_t *dphy_int_en0[MAX_MIPI_DPHY];
45 DPHY_INT_EN1_REG_t *dphy_int_en1[MAX_MIPI_DPHY];
46 DPHY_INT_EN2_REG_t *dphy_int_en2[MAX_MIPI_DPHY];
47 DPHY_INT_PD0_REG_t *dphy_int_pd0[MAX_MIPI_DPHY];
48 DPHY_INT_PD1_REG_t *dphy_int_pd1[MAX_MIPI_DPHY];
49 DPHY_INT_PD2_REG_t *dphy_int_pd2[MAX_MIPI_DPHY];
50 DPHY_DBG0_REG_t *dphy_dbg0[MAX_MIPI_DPHY];
51 DPHY_DBG1_REG_t *dphy_dbg1[MAX_MIPI_DPHY];
52 DPHY_DBG2_REG_t *dphy_dbg2[MAX_MIPI_DPHY];
53 DPHY_DBG3_REG_t *dphy_dbg3[MAX_MIPI_DPHY];
54 DPHY_DBG4_REG_t *dphy_dbg4[MAX_MIPI_DPHY];
55 DPHY_DBG5_REG_t *dphy_dbg5[MAX_MIPI_DPHY];
56
dphy_reg_map(unsigned int sel,unsigned long addr_base)57 int dphy_reg_map(unsigned int sel, unsigned long addr_base)
58 {
59 if (sel >= MAX_MIPI_DPHY)
60 return -1;
61
62 dphy_ctl[sel] = (DPHY_CTL_REG_t *) (addr_base + DPHY_CTL_REG_OFF);
63 dphy_tx_ctl[sel] =
64 (DPHY_TX_CTL_REG_t *) (addr_base + DPHY_TX_CTL_REG_OFF);
65 dphy_rx_ctl[sel] =
66 (DPHY_RX_CTL_REG_t *) (addr_base + DPHY_RX_CTL_REG_OFF);
67 dphy_tx_time0[sel] =
68 (DPHY_TX_TIME0_REG_t *) (addr_base + DPHY_TX_TIME0_REG_OFF);
69 dphy_tx_time1[sel] =
70 (DPHY_TX_TIME1_REG_t *) (addr_base + DPHY_TX_TIME1_REG_OFF);
71 dphy_tx_time2[sel] =
72 (DPHY_TX_TIME2_REG_t *) (addr_base + DPHY_TX_TIME2_REG_OFF);
73 dphy_tx_time3[sel] =
74 (DPHY_TX_TIME3_REG_t *) (addr_base + DPHY_TX_TIME3_REG_OFF);
75 dphy_tx_time4[sel] =
76 (DPHY_TX_TIME4_REG_t *) (addr_base + DPHY_TX_TIME4_REG_OFF);
77 dphy_rx_time0[sel] =
78 (DPHY_RX_TIME0_REG_t *) (addr_base + DPHY_RX_TIME0_REG_OFF);
79 dphy_rx_time1[sel] =
80 (DPHY_RX_TIME1_REG_t *) (addr_base + DPHY_RX_TIME1_REG_OFF);
81 dphy_rx_time2[sel] =
82 (DPHY_RX_TIME2_REG_t *) (addr_base + DPHY_RX_TIME2_REG_OFF);
83 dphy_rx_time3[sel] =
84 (DPHY_RX_TIME3_REG_t *) (addr_base + DPHY_RX_TIME3_REG_OFF);
85 dphy_ana0[sel] = (DPHY_ANA0_REG_t *) (addr_base + DPHY_ANA0_REG_OFF);
86 dphy_ana1[sel] = (DPHY_ANA1_REG_t *) (addr_base + DPHY_ANA1_REG_OFF);
87 dphy_ana2[sel] = (DPHY_ANA2_REG_t *) (addr_base + DPHY_ANA2_REG_OFF);
88 dphy_ana3[sel] = (DPHY_ANA3_REG_t *) (addr_base + DPHY_ANA3_REG_OFF);
89 dphy_ana4[sel] = (DPHY_ANA4_REG_t *) (addr_base + DPHY_ANA4_REG_OFF);
90 dphy_int_en0[sel] =
91 (DPHY_INT_EN0_REG_t *) (addr_base + DPHY_INT_EN0_REG_OFF);
92 dphy_int_en1[sel] =
93 (DPHY_INT_EN1_REG_t *) (addr_base + DPHY_INT_EN1_REG_OFF);
94 dphy_int_en2[sel] =
95 (DPHY_INT_EN2_REG_t *) (addr_base + DPHY_INT_EN2_REG_OFF);
96 dphy_int_pd0[sel] =
97 (DPHY_INT_PD0_REG_t *) (addr_base + DPHY_INT_PD0_REG_OFF);
98 dphy_int_pd1[sel] =
99 (DPHY_INT_PD1_REG_t *) (addr_base + DPHY_INT_PD1_REG_OFF);
100 dphy_int_pd2[sel] =
101 (DPHY_INT_PD2_REG_t *) (addr_base + DPHY_INT_PD2_REG_OFF);
102 dphy_dbg0[sel] = (DPHY_DBG0_REG_t *) (addr_base + DPHY_DBG0_REG_OFF);
103 dphy_dbg1[sel] = (DPHY_DBG1_REG_t *) (addr_base + DPHY_DBG1_REG_OFF);
104 dphy_dbg2[sel] = (DPHY_DBG2_REG_t *) (addr_base + DPHY_DBG2_REG_OFF);
105 dphy_dbg3[sel] = (DPHY_DBG3_REG_t *) (addr_base + DPHY_DBG3_REG_OFF);
106 dphy_dbg4[sel] = (DPHY_DBG4_REG_t *) (addr_base + DPHY_DBG4_REG_OFF);
107 dphy_dbg5[sel] = (DPHY_DBG5_REG_t *) (addr_base + DPHY_DBG5_REG_OFF);
108
109 return 0;
110 }
111
dphy_enable(unsigned int sel)112 void dphy_enable(unsigned int sel)
113 {
114 dphy_ctl[sel]->bits.module_en = 1;
115 }
116
dphy_disable(unsigned int sel)117 void dphy_disable(unsigned int sel)
118 {
119 dphy_ctl[sel]->bits.module_en = 0;
120 }
121
dphy_set_data_lane(unsigned int sel,unsigned char lane_num)122 void dphy_set_data_lane(unsigned int sel, unsigned char lane_num)
123 {
124 dphy_ctl[sel]->bits.lane_num = lane_num - 1;
125 }
126
dphy_get_data_lane(unsigned int sel)127 unsigned char dphy_get_data_lane(unsigned int sel)
128 {
129 return dphy_ctl[sel]->bits.lane_num + 1;
130 }
131
dphy_rx_enable(unsigned int sel,unsigned char lane_num)132 void dphy_rx_enable(unsigned int sel, unsigned char lane_num)
133 {
134 dphy_rx_ctl[sel]->bits.rx_clk_force = 1;
135 switch (lane_num - 1) {
136 case 3:
137 dphy_rx_ctl[sel]->bits.rx_d3_force = 1;
138 case 2:
139 dphy_rx_ctl[sel]->bits.rx_d2_force = 1;
140 case 1:
141 dphy_rx_ctl[sel]->bits.rx_d1_force = 1;
142 case 0:
143 dphy_rx_ctl[sel]->bits.rx_d0_force = 1;
144 break;
145 default:
146 dphy_rx_ctl[sel]->bits.rx_d3_force = 0;
147 dphy_rx_ctl[sel]->bits.rx_d2_force = 0;
148 dphy_rx_ctl[sel]->bits.rx_d1_force = 0;
149 dphy_rx_ctl[sel]->bits.rx_d0_force = 0;
150 break;
151 }
152 }
153
dphy_rx_disable(unsigned int sel,unsigned char lane_num)154 void dphy_rx_disable(unsigned int sel, unsigned char lane_num)
155 {
156 dphy_rx_ctl[sel]->bits.rx_clk_force = 0;
157 switch (lane_num - 1) {
158 case 3:
159 dphy_rx_ctl[sel]->bits.rx_d3_force = 0;
160 case 2:
161 dphy_rx_ctl[sel]->bits.rx_d2_force = 0;
162 case 1:
163 dphy_rx_ctl[sel]->bits.rx_d1_force = 0;
164 case 0:
165 dphy_rx_ctl[sel]->bits.rx_d0_force = 0;
166 break;
167 default:
168 dphy_rx_ctl[sel]->bits.rx_d3_force = 0;
169 dphy_rx_ctl[sel]->bits.rx_d2_force = 0;
170 dphy_rx_ctl[sel]->bits.rx_d1_force = 0;
171 dphy_rx_ctl[sel]->bits.rx_d0_force = 0;
172 break;
173 }
174 }
175
dphy_rx_dbc_enable(unsigned int sel)176 void dphy_rx_dbc_enable(unsigned int sel)
177 {
178 dphy_rx_ctl[sel]->bits.dbc_en = 1;
179 }
180
dphy_rx_dbc_disable(unsigned int sel)181 void dphy_rx_dbc_disable(unsigned int sel)
182 {
183 dphy_rx_ctl[sel]->bits.dbc_en = 0;
184 }
185
dphy_rx_hs_clk_miss_cnt_enable(unsigned int sel)186 void dphy_rx_hs_clk_miss_cnt_enable(unsigned int sel)
187 {
188 dphy_rx_time0[sel]->bits.hsrx_clk_miss_en = 1;
189 }
190
dphy_rx_hs_clk_miss_cnt_disable(unsigned int sel)191 void dphy_rx_hs_clk_miss_cnt_disable(unsigned int sel)
192 {
193 dphy_rx_time0[sel]->bits.hsrx_clk_miss_en = 0;
194 }
195
dphy_rx_hs_sync_cnt_enable(unsigned int sel)196 void dphy_rx_hs_sync_cnt_enable(unsigned int sel)
197 {
198 dphy_rx_time0[sel]->bits.hsrx_sync_err_to_en = 1;
199 }
200
dphy_rx_hs_sync_cnt_disable(unsigned int sel)201 void dphy_rx_hs_sync_cnt_disable(unsigned int sel)
202 {
203 dphy_rx_time0[sel]->bits.hsrx_sync_err_to_en = 0;
204 }
205
dphy_rx_lp_to_cnt_enable(unsigned int sel)206 void dphy_rx_lp_to_cnt_enable(unsigned int sel)
207 {
208 dphy_rx_time0[sel]->bits.lprx_to_en = 1;
209 }
210
dphy_rx_lp_to_cnt_disable(unsigned int sel)211 void dphy_rx_lp_to_cnt_disable(unsigned int sel)
212 {
213 dphy_rx_time0[sel]->bits.lprx_to_en = 0;
214 }
215
dphy_rx_freq_cnt_enable(unsigned int sel)216 void dphy_rx_freq_cnt_enable(unsigned int sel)
217 {
218 dphy_rx_time0[sel]->bits.freq_cnt_en = 1;
219 }
220
dphy_rx_freq_cnt_disable(unsigned int sel)221 void dphy_rx_freq_cnt_disable(unsigned int sel)
222 {
223 dphy_rx_time0[sel]->bits.freq_cnt_en = 0;
224 }
225
dphy_rx_set_hs_clk_miss(unsigned int sel,unsigned char cnt)226 void dphy_rx_set_hs_clk_miss(unsigned int sel, unsigned char cnt)
227 {
228 dphy_rx_time0[sel]->bits.hsrx_clk_miss = cnt;
229 }
230
dphy_rx_get_hs_clk_miss(unsigned int sel)231 unsigned char dphy_rx_get_hs_clk_miss(unsigned int sel)
232 {
233 return dphy_rx_time0[sel]->bits.hsrx_clk_miss;
234 }
235
dphy_rx_set_hs_sync_to(unsigned int sel,unsigned char cnt)236 void dphy_rx_set_hs_sync_to(unsigned int sel, unsigned char cnt)
237 {
238 dphy_rx_time0[sel]->bits.hsrx_sync_err_to = cnt;
239 }
240
dphy_rx_get_hs_sync_to(unsigned int sel)241 unsigned char dphy_rx_get_hs_sync_to(unsigned int sel)
242 {
243 return dphy_rx_time0[sel]->bits.hsrx_sync_err_to;
244 }
245
dphy_rx_set_lp_to(unsigned int sel,unsigned char cnt)246 void dphy_rx_set_lp_to(unsigned int sel, unsigned char cnt)
247 {
248 dphy_rx_time0[sel]->bits.lprx_to = cnt;
249 }
250
dphy_rx_get_lp_to(unsigned int sel)251 unsigned char dphy_rx_get_lp_to(unsigned int sel)
252 {
253 return dphy_rx_time0[sel]->bits.lprx_to;
254 }
255
dphy_rx_set_rx_dly(unsigned int sel,unsigned short cnt)256 void dphy_rx_set_rx_dly(unsigned int sel, unsigned short cnt)
257 {
258 dphy_rx_time1[sel]->bits.rx_dly = cnt;
259 }
260
dphy_rx_get_rx_dly(unsigned int sel)261 unsigned short dphy_rx_get_rx_dly(unsigned int sel)
262 {
263 return dphy_rx_time1[sel]->bits.rx_dly;
264 }
265
dphy_rx_set_lprst_dly(unsigned int sel,unsigned char cnt)266 void dphy_rx_set_lprst_dly(unsigned int sel, unsigned char cnt)
267 {
268 dphy_rx_time3[sel]->bits.lprst_dly = cnt;
269 }
270
dphy_rx_get_lprst_dly(unsigned int sel)271 unsigned char dphy_rx_get_lprst_dly(unsigned int sel)
272 {
273 return dphy_rx_time3[sel]->bits.lprst_dly;
274 }
275
dphy_rx_set_entm_to_enrx_dly(unsigned int sel,unsigned char cnt)276 void dphy_rx_set_entm_to_enrx_dly(unsigned int sel, unsigned char cnt)
277 {
278 dphy_rx_time2[sel]->bits.hsrx_ana0_set = cnt;
279 }
280
dphy_rx_get_entm_to_enrx_dly(unsigned int sel)281 unsigned char dphy_rx_get_entm_to_enrx_dly(unsigned int sel)
282 {
283 return dphy_rx_time2[sel]->bits.hsrx_ana0_set;
284 }
285
dphy_rx_set_lp_ulps_wp(unsigned int sel,unsigned int cnt)286 void dphy_rx_set_lp_ulps_wp(unsigned int sel, unsigned int cnt)
287 {
288 dphy_rx_time1[sel]->bits.lprx_ulps_wp = cnt;
289 }
290
dphy_rx_get_lp_ulps_wp(unsigned int sel)291 unsigned int dphy_rx_get_lp_ulps_wp(unsigned int sel)
292 {
293 return dphy_rx_time1[sel]->bits.lprx_ulps_wp;
294 }
295
dphy_rx_get_freq_cnt(unsigned int sel)296 unsigned short dphy_rx_get_freq_cnt(unsigned int sel)
297 {
298 return dphy_rx_time3[sel]->bits.freq_cnt;
299 }
300
dphy_int_enable(unsigned int sel,enum dphy_int dphy_int)301 void dphy_int_enable(unsigned int sel, enum dphy_int dphy_int)
302 {
303 switch (dphy_int) {
304 case SOT_D0:
305 dphy_int_en0[sel]->bits.sot_d0_int = 1;
306 break;
307 case SOT_D1:
308 dphy_int_en0[sel]->bits.sot_d1_int = 1;
309 break;
310 case SOT_D2:
311 dphy_int_en0[sel]->bits.sot_d2_int = 1;
312 break;
313 case SOT_D3:
314 dphy_int_en0[sel]->bits.sot_d3_int = 1;
315 break;
316 case SOT_ERR_D0:
317 dphy_int_en0[sel]->bits.sot_err_d0_int = 1;
318 break;
319 case SOT_ERR_D1:
320 dphy_int_en0[sel]->bits.sot_err_d1_int = 1;
321 break;
322 case SOT_ERR_D2:
323 dphy_int_en0[sel]->bits.sot_err_d2_int = 1;
324 break;
325 case SOT_ERR_D3:
326 dphy_int_en0[sel]->bits.sot_err_d3_int = 1;
327 break;
328 case SOT_SYNC_ERR_D0:
329 dphy_int_en0[sel]->bits.sot_sync_err_d0_int = 1;
330 break;
331 case SOT_SYNC_ERR_D1:
332 dphy_int_en0[sel]->bits.sot_sync_err_d1_int = 1;
333 break;
334 case SOT_SYNC_ERR_D2:
335 dphy_int_en0[sel]->bits.sot_sync_err_d2_int = 1;
336 break;
337 case SOT_SYNC_ERR_D3:
338 dphy_int_en0[sel]->bits.sot_sync_err_d3_int = 1;
339 break;
340 case RX_ALG_ERR_D0:
341 dphy_int_en0[sel]->bits.rx_alg_err_d0_int = 1;
342 break;
343 case RX_ALG_ERR_D1:
344 dphy_int_en0[sel]->bits.rx_alg_err_d1_int = 1;
345 break;
346 case RX_ALG_ERR_D2:
347 dphy_int_en0[sel]->bits.rx_alg_err_d2_int = 1;
348 break;
349 case RX_ALG_ERR_D3:
350 dphy_int_en0[sel]->bits.rx_alg_err_d3_int = 1;
351 break;
352 case CD_LP0_ERR_CLK:
353 dphy_int_en0[sel]->bits.cd_lp0_err_clk_int = 1;
354 break;
355 case CD_LP1_ERR_CLK:
356 dphy_int_en0[sel]->bits.cd_lp1_err_clk_int = 1;
357 break;
358 case CD_LP0_ERR_D0:
359 dphy_int_en0[sel]->bits.cd_lp0_err_d0_int = 1;
360 break;
361 case CD_LP1_ERR_D0:
362 dphy_int_en0[sel]->bits.cd_lp1_err_d0_int = 1;
363 break;
364 case CD_LP0_ERR_D1:
365 dphy_int_en0[sel]->bits.cd_lp0_err_d1_int = 1;
366 break;
367 case CD_LP1_ERR_D1:
368 dphy_int_en0[sel]->bits.cd_lp1_err_d1_int = 1;
369 break;
370 case CD_LP0_ERR_D2:
371 dphy_int_en0[sel]->bits.cd_lp0_err_d2_int = 1;
372 break;
373 case CD_LP1_ERR_D2:
374 dphy_int_en0[sel]->bits.cd_lp1_err_d2_int = 1;
375 break;
376 case CD_LP0_ERR_D3:
377 dphy_int_en0[sel]->bits.cd_lp0_err_d3_int = 1;
378 break;
379 case CD_LP1_ERR_D3:
380 dphy_int_en0[sel]->bits.cd_lp1_err_d3_int = 1;
381 break;
382 case ULPS_D0:
383 dphy_int_en1[sel]->bits.ulps_d0_int = 1;
384 break;
385 case ULPS_D1:
386 dphy_int_en1[sel]->bits.ulps_d1_int = 1;
387 break;
388 case ULPS_D2:
389 dphy_int_en1[sel]->bits.ulps_d2_int = 1;
390 break;
391 case ULPS_D3:
392 dphy_int_en1[sel]->bits.ulps_d3_int = 1;
393 break;
394 case ULPS_WP_D0:
395 dphy_int_en1[sel]->bits.ulps_wp_d0_int = 1;
396 break;
397 case ULPS_WP_D1:
398 dphy_int_en1[sel]->bits.ulps_wp_d1_int = 1;
399 break;
400 case ULPS_WP_D2:
401 dphy_int_en1[sel]->bits.ulps_wp_d2_int = 1;
402 break;
403 case ULPS_WP_D3:
404 dphy_int_en1[sel]->bits.ulps_wp_d3_int = 1;
405 break;
406 case ULPS_CLK:
407 dphy_int_en1[sel]->bits.ulps_clk_int = 1;
408 break;
409 case ULPS_WP_CLK:
410 dphy_int_en1[sel]->bits.ulps_wp_clk_int = 1;
411 break;
412 case LPDT_D0:
413 dphy_int_en1[sel]->bits.lpdt_d0_int = 1;
414 break;
415 case RX_TRND_D0:
416 dphy_int_en1[sel]->bits.rx_trnd_d0_int = 1;
417 break;
418 case TX_TRND_ERR_D0:
419 dphy_int_en1[sel]->bits.tx_trnd_err_d0_int = 1;
420 break;
421 case UNDEF1_D0:
422 dphy_int_en1[sel]->bits.undef1_d0_int = 1;
423 break;
424 case UNDEF2_D0:
425 dphy_int_en1[sel]->bits.undef2_d0_int = 1;
426 break;
427 case UNDEF3_D0:
428 dphy_int_en1[sel]->bits.undef3_d0_int = 1;
429 break;
430 case UNDEF4_D0:
431 dphy_int_en1[sel]->bits.undef4_d0_int = 1;
432 break;
433 case UNDEF5_D0:
434 dphy_int_en1[sel]->bits.undef5_d0_int = 1;
435 break;
436 case RST_D0:
437 dphy_int_en1[sel]->bits.rst_d0_int = 1;
438 break;
439 case RST_D1:
440 dphy_int_en1[sel]->bits.rst_d1_int = 1;
441 break;
442 case RST_D2:
443 dphy_int_en1[sel]->bits.rst_d2_int = 1;
444 break;
445 case RST_D3:
446 dphy_int_en1[sel]->bits.rst_d3_int = 1;
447 break;
448 case ESC_CMD_ERR_D0:
449 dphy_int_en1[sel]->bits.esc_cmd_err_d0_int = 1;
450 break;
451 case ESC_CMD_ERR_D1:
452 dphy_int_en1[sel]->bits.esc_cmd_err_d1_int = 1;
453 break;
454 case ESC_CMD_ERR_D2:
455 dphy_int_en1[sel]->bits.esc_cmd_err_d2_int = 1;
456 break;
457 case ESC_CMD_ERR_D3:
458 dphy_int_en1[sel]->bits.esc_cmd_err_d3_int = 1;
459 break;
460 case FALSE_CTL_D0:
461 dphy_int_en1[sel]->bits.false_ctl_d0_int = 1;
462 break;
463 case FALSE_CTL_D1:
464 dphy_int_en1[sel]->bits.false_ctl_d1_int = 1;
465 break;
466 case FALSE_CTL_D2:
467 dphy_int_en1[sel]->bits.false_ctl_d2_int = 1;
468 break;
469 case FALSE_CTL_D3:
470 dphy_int_en1[sel]->bits.false_ctl_d3_int = 1;
471 break;
472 default:
473 break;
474 }
475 }
476
dphy_int_disable(unsigned int sel,enum dphy_int dphy_int)477 void dphy_int_disable(unsigned int sel, enum dphy_int dphy_int)
478 {
479 switch (dphy_int) {
480 case SOT_D0:
481 dphy_int_en0[sel]->bits.sot_d0_int = 0;
482 break;
483 case SOT_D1:
484 dphy_int_en0[sel]->bits.sot_d1_int = 0;
485 break;
486 case SOT_D2:
487 dphy_int_en0[sel]->bits.sot_d2_int = 0;
488 break;
489 case SOT_D3:
490 dphy_int_en0[sel]->bits.sot_d3_int = 0;
491 break;
492 case SOT_ERR_D0:
493 dphy_int_en0[sel]->bits.sot_err_d0_int = 0;
494 break;
495 case SOT_ERR_D1:
496 dphy_int_en0[sel]->bits.sot_err_d1_int = 0;
497 break;
498 case SOT_ERR_D2:
499 dphy_int_en0[sel]->bits.sot_err_d2_int = 0;
500 break;
501 case SOT_ERR_D3:
502 dphy_int_en0[sel]->bits.sot_err_d3_int = 0;
503 break;
504 case SOT_SYNC_ERR_D0:
505 dphy_int_en0[sel]->bits.sot_sync_err_d0_int = 0;
506 break;
507 case SOT_SYNC_ERR_D1:
508 dphy_int_en0[sel]->bits.sot_sync_err_d1_int = 0;
509 break;
510 case SOT_SYNC_ERR_D2:
511 dphy_int_en0[sel]->bits.sot_sync_err_d2_int = 0;
512 break;
513 case SOT_SYNC_ERR_D3:
514 dphy_int_en0[sel]->bits.sot_sync_err_d3_int = 0;
515 break;
516 case RX_ALG_ERR_D0:
517 dphy_int_en0[sel]->bits.rx_alg_err_d0_int = 0;
518 break;
519 case RX_ALG_ERR_D1:
520 dphy_int_en0[sel]->bits.rx_alg_err_d1_int = 0;
521 break;
522 case RX_ALG_ERR_D2:
523 dphy_int_en0[sel]->bits.rx_alg_err_d2_int = 0;
524 break;
525 case RX_ALG_ERR_D3:
526 dphy_int_en0[sel]->bits.rx_alg_err_d3_int = 0;
527 break;
528 case CD_LP0_ERR_CLK:
529 dphy_int_en0[sel]->bits.cd_lp0_err_clk_int = 0;
530 break;
531 case CD_LP1_ERR_CLK:
532 dphy_int_en0[sel]->bits.cd_lp1_err_clk_int = 0;
533 break;
534 case CD_LP0_ERR_D0:
535 dphy_int_en0[sel]->bits.cd_lp0_err_d0_int = 0;
536 break;
537 case CD_LP1_ERR_D0:
538 dphy_int_en0[sel]->bits.cd_lp1_err_d0_int = 0;
539 break;
540 case CD_LP0_ERR_D1:
541 dphy_int_en0[sel]->bits.cd_lp0_err_d1_int = 0;
542 break;
543 case CD_LP1_ERR_D1:
544 dphy_int_en0[sel]->bits.cd_lp1_err_d1_int = 0;
545 break;
546 case CD_LP0_ERR_D2:
547 dphy_int_en0[sel]->bits.cd_lp0_err_d2_int = 0;
548 break;
549 case CD_LP1_ERR_D2:
550 dphy_int_en0[sel]->bits.cd_lp1_err_d2_int = 0;
551 break;
552 case CD_LP0_ERR_D3:
553 dphy_int_en0[sel]->bits.cd_lp0_err_d3_int = 0;
554 break;
555 case CD_LP1_ERR_D3:
556 dphy_int_en0[sel]->bits.cd_lp1_err_d3_int = 0;
557 break;
558 case ULPS_D0:
559 dphy_int_en1[sel]->bits.ulps_d0_int = 0;
560 break;
561 case ULPS_D1:
562 dphy_int_en1[sel]->bits.ulps_d1_int = 0;
563 break;
564 case ULPS_D2:
565 dphy_int_en1[sel]->bits.ulps_d2_int = 0;
566 break;
567 case ULPS_D3:
568 dphy_int_en1[sel]->bits.ulps_d3_int = 0;
569 break;
570 case ULPS_WP_D0:
571 dphy_int_en1[sel]->bits.ulps_wp_d0_int = 0;
572 break;
573 case ULPS_WP_D1:
574 dphy_int_en1[sel]->bits.ulps_wp_d1_int = 0;
575 break;
576 case ULPS_WP_D2:
577 dphy_int_en1[sel]->bits.ulps_wp_d2_int = 0;
578 break;
579 case ULPS_WP_D3:
580 dphy_int_en1[sel]->bits.ulps_wp_d3_int = 0;
581 break;
582 case ULPS_CLK:
583 dphy_int_en1[sel]->bits.ulps_clk_int = 0;
584 break;
585 case ULPS_WP_CLK:
586 dphy_int_en1[sel]->bits.ulps_wp_clk_int = 0;
587 break;
588 case LPDT_D0:
589 dphy_int_en1[sel]->bits.lpdt_d0_int = 0;
590 break;
591 case RX_TRND_D0:
592 dphy_int_en1[sel]->bits.rx_trnd_d0_int = 0;
593 break;
594 case TX_TRND_ERR_D0:
595 dphy_int_en1[sel]->bits.tx_trnd_err_d0_int = 0;
596 break;
597 case UNDEF1_D0:
598 dphy_int_en1[sel]->bits.undef1_d0_int = 0;
599 break;
600 case UNDEF2_D0:
601 dphy_int_en1[sel]->bits.undef2_d0_int = 0;
602 break;
603 case UNDEF3_D0:
604 dphy_int_en1[sel]->bits.undef3_d0_int = 0;
605 break;
606 case UNDEF4_D0:
607 dphy_int_en1[sel]->bits.undef4_d0_int = 0;
608 break;
609 case UNDEF5_D0:
610 dphy_int_en1[sel]->bits.undef5_d0_int = 0;
611 break;
612 case RST_D0:
613 dphy_int_en1[sel]->bits.rst_d0_int = 0;
614 break;
615 case RST_D1:
616 dphy_int_en1[sel]->bits.rst_d1_int = 0;
617 break;
618 case RST_D2:
619 dphy_int_en1[sel]->bits.rst_d2_int = 0;
620 break;
621 case RST_D3:
622 dphy_int_en1[sel]->bits.rst_d3_int = 0;
623 break;
624 case ESC_CMD_ERR_D0:
625 dphy_int_en1[sel]->bits.esc_cmd_err_d0_int = 0;
626 break;
627 case ESC_CMD_ERR_D1:
628 dphy_int_en1[sel]->bits.esc_cmd_err_d1_int = 0;
629 break;
630 case ESC_CMD_ERR_D2:
631 dphy_int_en1[sel]->bits.esc_cmd_err_d2_int = 0;
632 break;
633 case ESC_CMD_ERR_D3:
634 dphy_int_en1[sel]->bits.esc_cmd_err_d3_int = 0;
635 break;
636 case FALSE_CTL_D0:
637 dphy_int_en1[sel]->bits.false_ctl_d0_int = 0;
638 break;
639 case FALSE_CTL_D1:
640 dphy_int_en1[sel]->bits.false_ctl_d1_int = 0;
641 break;
642 case FALSE_CTL_D2:
643 dphy_int_en1[sel]->bits.false_ctl_d2_int = 0;
644 break;
645 case FALSE_CTL_D3:
646 dphy_int_en1[sel]->bits.false_ctl_d3_int = 0;
647 break;
648 default:
649 break;
650 }
651 }
652
dphy_get_int_status(unsigned int sel,enum dphy_int dphy_int)653 int dphy_get_int_status(unsigned int sel, enum dphy_int dphy_int)
654 {
655 switch (dphy_int) {
656 case SOT_D0:
657 return dphy_int_pd0[sel]->bits.sot_d0_pd;
658 case SOT_D1:
659 return dphy_int_pd0[sel]->bits.sot_d1_pd;
660 case SOT_D2:
661 return dphy_int_pd0[sel]->bits.sot_d2_pd;
662 case SOT_D3:
663 return dphy_int_pd0[sel]->bits.sot_d3_pd;
664 case SOT_ERR_D0:
665 return dphy_int_pd0[sel]->bits.sot_err_d0_pd;
666 case SOT_ERR_D1:
667 return dphy_int_pd0[sel]->bits.sot_err_d1_pd;
668 case SOT_ERR_D2:
669 return dphy_int_pd0[sel]->bits.sot_err_d2_pd;
670 case SOT_ERR_D3:
671 return dphy_int_pd0[sel]->bits.sot_err_d3_pd;
672 case SOT_SYNC_ERR_D0:
673 return dphy_int_pd0[sel]->bits.sot_sync_err_d0_pd;
674 case SOT_SYNC_ERR_D1:
675 return dphy_int_pd0[sel]->bits.sot_sync_err_d1_pd;
676 case SOT_SYNC_ERR_D2:
677 return dphy_int_pd0[sel]->bits.sot_sync_err_d2_pd;
678 case SOT_SYNC_ERR_D3:
679 return dphy_int_pd0[sel]->bits.sot_sync_err_d3_pd;
680 case RX_ALG_ERR_D0:
681 return dphy_int_pd0[sel]->bits.rx_alg_err_d0_pd;
682 case RX_ALG_ERR_D1:
683 return dphy_int_pd0[sel]->bits.rx_alg_err_d1_pd;
684 case RX_ALG_ERR_D2:
685 return dphy_int_pd0[sel]->bits.rx_alg_err_d2_pd;
686 case RX_ALG_ERR_D3:
687 return dphy_int_pd0[sel]->bits.rx_alg_err_d3_pd;
688 case CD_LP0_ERR_CLK:
689 return dphy_int_pd0[sel]->bits.cd_lp0_err_clk_pd;
690 case CD_LP1_ERR_CLK:
691 return dphy_int_pd0[sel]->bits.cd_lp1_err_clk_pd;
692 case CD_LP0_ERR_D0:
693 return dphy_int_pd0[sel]->bits.cd_lp0_err_d0_pd;
694 case CD_LP1_ERR_D0:
695 return dphy_int_pd0[sel]->bits.cd_lp1_err_d0_pd;
696 case CD_LP0_ERR_D1:
697 return dphy_int_pd0[sel]->bits.cd_lp0_err_d1_pd;
698 case CD_LP1_ERR_D1:
699 return dphy_int_pd0[sel]->bits.cd_lp1_err_d1_pd;
700 case CD_LP0_ERR_D2:
701 return dphy_int_pd0[sel]->bits.cd_lp0_err_d2_pd;
702 case CD_LP1_ERR_D2:
703 return dphy_int_pd0[sel]->bits.cd_lp1_err_d2_pd;
704 case CD_LP0_ERR_D3:
705 return dphy_int_pd0[sel]->bits.cd_lp0_err_d3_pd;
706 case CD_LP1_ERR_D3:
707 return dphy_int_pd0[sel]->bits.cd_lp1_err_d3_pd;
708 case ULPS_D0:
709 return dphy_int_pd1[sel]->bits.ulps_d0_pd;
710 case ULPS_D1:
711 return dphy_int_pd1[sel]->bits.ulps_d1_pd;
712 case ULPS_D2:
713 return dphy_int_pd1[sel]->bits.ulps_d2_pd;
714 case ULPS_D3:
715 return dphy_int_pd1[sel]->bits.ulps_d3_pd;
716 case ULPS_WP_D0:
717 return dphy_int_pd1[sel]->bits.ulps_wp_d0_pd;
718 case ULPS_WP_D1:
719 return dphy_int_pd1[sel]->bits.ulps_wp_d1_pd;
720 case ULPS_WP_D2:
721 return dphy_int_pd1[sel]->bits.ulps_wp_d2_pd;
722 case ULPS_WP_D3:
723 return dphy_int_pd1[sel]->bits.ulps_wp_d3_pd;
724 case ULPS_CLK:
725 return dphy_int_pd1[sel]->bits.ulps_clk_pd;
726 case ULPS_WP_CLK:
727 return dphy_int_pd1[sel]->bits.ulps_wp_clk_pd;
728 case LPDT_D0:
729 return dphy_int_pd1[sel]->bits.lpdt_d0_pd;
730 case RX_TRND_D0:
731 return dphy_int_pd1[sel]->bits.rx_trnd_d0_pd;
732 case TX_TRND_ERR_D0:
733 return dphy_int_pd1[sel]->bits.tx_trnd_err_d0_pd;
734 case UNDEF1_D0:
735 return dphy_int_pd1[sel]->bits.undef1_d0_pd;
736 case UNDEF2_D0:
737 return dphy_int_pd1[sel]->bits.undef2_d0_pd;
738 case UNDEF3_D0:
739 return dphy_int_pd1[sel]->bits.undef3_d0_pd;
740 case UNDEF4_D0:
741 return dphy_int_pd1[sel]->bits.undef4_d0_pd;
742 case UNDEF5_D0:
743 return dphy_int_pd1[sel]->bits.undef5_d0_pd;
744 case RST_D0:
745 return dphy_int_pd1[sel]->bits.rst_d0_pd;
746 case RST_D1:
747 return dphy_int_pd1[sel]->bits.rst_d1_pd;
748 case RST_D2:
749 return dphy_int_pd1[sel]->bits.rst_d2_pd;
750 case RST_D3:
751 return dphy_int_pd1[sel]->bits.rst_d3_pd;
752 case ESC_CMD_ERR_D0:
753 return dphy_int_pd1[sel]->bits.esc_cmd_err_d0_pd;
754 case ESC_CMD_ERR_D1:
755 return dphy_int_pd1[sel]->bits.esc_cmd_err_d1_pd;
756 case ESC_CMD_ERR_D2:
757 return dphy_int_pd1[sel]->bits.esc_cmd_err_d2_pd;
758 case ESC_CMD_ERR_D3:
759 return dphy_int_pd1[sel]->bits.esc_cmd_err_d3_pd;
760 case FALSE_CTL_D0:
761 return dphy_int_pd1[sel]->bits.false_ctl_d0_pd;
762 case FALSE_CTL_D1:
763 return dphy_int_pd1[sel]->bits.false_ctl_d1_pd;
764 case FALSE_CTL_D2:
765 return dphy_int_pd1[sel]->bits.false_ctl_d2_pd;
766 case FALSE_CTL_D3:
767 return dphy_int_pd1[sel]->bits.false_ctl_d3_pd;
768 default:
769 return -1;
770 }
771 }
772
dphy_clear_int_status(unsigned int sel,enum dphy_int dphy_int)773 void dphy_clear_int_status(unsigned int sel, enum dphy_int dphy_int)
774 {
775 switch (dphy_int) {
776 case SOT_D0:
777 dphy_int_pd0[sel]->bits.sot_d0_pd = 1;
778 break;
779 case SOT_D1:
780 dphy_int_pd0[sel]->bits.sot_d1_pd = 1;
781 break;
782 case SOT_D2:
783 dphy_int_pd0[sel]->bits.sot_d2_pd = 1;
784 break;
785 case SOT_D3:
786 dphy_int_pd0[sel]->bits.sot_d3_pd = 1;
787 break;
788 case SOT_ERR_D0:
789 dphy_int_pd0[sel]->bits.sot_err_d0_pd = 1;
790 break;
791 case SOT_ERR_D1:
792 dphy_int_pd0[sel]->bits.sot_err_d1_pd = 1;
793 break;
794 case SOT_ERR_D2:
795 dphy_int_pd0[sel]->bits.sot_err_d2_pd = 1;
796 break;
797 case SOT_ERR_D3:
798 dphy_int_pd0[sel]->bits.sot_err_d3_pd = 1;
799 break;
800 case SOT_SYNC_ERR_D0:
801 dphy_int_pd0[sel]->bits.sot_sync_err_d0_pd = 1;
802 break;
803 case SOT_SYNC_ERR_D1:
804 dphy_int_pd0[sel]->bits.sot_sync_err_d1_pd = 1;
805 break;
806 case SOT_SYNC_ERR_D2:
807 dphy_int_pd0[sel]->bits.sot_sync_err_d2_pd = 1;
808 break;
809 case SOT_SYNC_ERR_D3:
810 dphy_int_pd0[sel]->bits.sot_sync_err_d3_pd = 1;
811 break;
812 case RX_ALG_ERR_D0:
813 dphy_int_pd0[sel]->bits.rx_alg_err_d0_pd = 1;
814 break;
815 case RX_ALG_ERR_D1:
816 dphy_int_pd0[sel]->bits.rx_alg_err_d1_pd = 1;
817 break;
818 case RX_ALG_ERR_D2:
819 dphy_int_pd0[sel]->bits.rx_alg_err_d2_pd = 1;
820 break;
821 case RX_ALG_ERR_D3:
822 dphy_int_pd0[sel]->bits.rx_alg_err_d3_pd = 1;
823 break;
824 case CD_LP0_ERR_CLK:
825 dphy_int_pd0[sel]->bits.cd_lp0_err_clk_pd = 1;
826 break;
827 case CD_LP1_ERR_CLK:
828 dphy_int_pd0[sel]->bits.cd_lp1_err_clk_pd = 1;
829 break;
830 case CD_LP0_ERR_D0:
831 dphy_int_pd0[sel]->bits.cd_lp0_err_d0_pd = 1;
832 break;
833 case CD_LP1_ERR_D0:
834 dphy_int_pd0[sel]->bits.cd_lp1_err_d0_pd = 1;
835 break;
836 case CD_LP0_ERR_D1:
837 dphy_int_pd0[sel]->bits.cd_lp0_err_d1_pd = 1;
838 break;
839 case CD_LP1_ERR_D1:
840 dphy_int_pd0[sel]->bits.cd_lp1_err_d1_pd = 1;
841 break;
842 case CD_LP0_ERR_D2:
843 dphy_int_pd0[sel]->bits.cd_lp0_err_d2_pd = 1;
844 break;
845 case CD_LP1_ERR_D2:
846 dphy_int_pd0[sel]->bits.cd_lp1_err_d2_pd = 1;
847 break;
848 case CD_LP0_ERR_D3:
849 dphy_int_pd0[sel]->bits.cd_lp0_err_d3_pd = 1;
850 break;
851 case CD_LP1_ERR_D3:
852 dphy_int_pd0[sel]->bits.cd_lp1_err_d3_pd = 1;
853 break;
854 case ULPS_D0:
855 dphy_int_pd1[sel]->bits.ulps_d0_pd = 1;
856 break;
857 case ULPS_D1:
858 dphy_int_pd1[sel]->bits.ulps_d1_pd = 1;
859 break;
860 case ULPS_D2:
861 dphy_int_pd1[sel]->bits.ulps_d2_pd = 1;
862 break;
863 case ULPS_D3:
864 dphy_int_pd1[sel]->bits.ulps_d3_pd = 1;
865 break;
866 case ULPS_WP_D0:
867 dphy_int_pd1[sel]->bits.ulps_wp_d0_pd = 1;
868 break;
869 case ULPS_WP_D1:
870 dphy_int_pd1[sel]->bits.ulps_wp_d1_pd = 1;
871 break;
872 case ULPS_WP_D2:
873 dphy_int_pd1[sel]->bits.ulps_wp_d2_pd = 1;
874 break;
875 case ULPS_WP_D3:
876 dphy_int_pd1[sel]->bits.ulps_wp_d3_pd = 1;
877 break;
878 case ULPS_CLK:
879 dphy_int_pd1[sel]->bits.ulps_clk_pd = 1;
880 break;
881 case ULPS_WP_CLK:
882 dphy_int_pd1[sel]->bits.ulps_wp_clk_pd = 1;
883 break;
884 case LPDT_D0:
885 dphy_int_pd1[sel]->bits.lpdt_d0_pd = 1;
886 break;
887 case RX_TRND_D0:
888 dphy_int_pd1[sel]->bits.rx_trnd_d0_pd = 1;
889 break;
890 case TX_TRND_ERR_D0:
891 dphy_int_pd1[sel]->bits.tx_trnd_err_d0_pd = 1;
892 break;
893 case UNDEF1_D0:
894 dphy_int_pd1[sel]->bits.undef1_d0_pd = 1;
895 break;
896 case UNDEF2_D0:
897 dphy_int_pd1[sel]->bits.undef2_d0_pd = 1;
898 break;
899 case UNDEF3_D0:
900 dphy_int_pd1[sel]->bits.undef3_d0_pd = 1;
901 break;
902 case UNDEF4_D0:
903 dphy_int_pd1[sel]->bits.undef4_d0_pd = 1;
904 break;
905 case UNDEF5_D0:
906 dphy_int_pd1[sel]->bits.undef5_d0_pd = 1;
907 break;
908 case RST_D0:
909 dphy_int_pd1[sel]->bits.rst_d0_pd = 1;
910 break;
911 case RST_D1:
912 dphy_int_pd1[sel]->bits.rst_d1_pd = 1;
913 break;
914 case RST_D2:
915 dphy_int_pd1[sel]->bits.rst_d2_pd = 1;
916 break;
917 case RST_D3:
918 dphy_int_pd1[sel]->bits.rst_d3_pd = 1;
919 break;
920 case ESC_CMD_ERR_D0:
921 dphy_int_pd1[sel]->bits.esc_cmd_err_d0_pd = 1;
922 break;
923 case ESC_CMD_ERR_D1:
924 dphy_int_pd1[sel]->bits.esc_cmd_err_d1_pd = 1;
925 break;
926 case ESC_CMD_ERR_D2:
927 dphy_int_pd1[sel]->bits.esc_cmd_err_d2_pd = 1;
928 break;
929 case ESC_CMD_ERR_D3:
930 dphy_int_pd1[sel]->bits.esc_cmd_err_d3_pd = 1;
931 break;
932 case FALSE_CTL_D0:
933 dphy_int_pd1[sel]->bits.false_ctl_d0_pd = 1;
934 break;
935 case FALSE_CTL_D1:
936 dphy_int_pd1[sel]->bits.false_ctl_d1_pd = 1;
937 break;
938 case FALSE_CTL_D2:
939 dphy_int_pd1[sel]->bits.false_ctl_d2_pd = 1;
940 break;
941 case FALSE_CTL_D3:
942 dphy_int_pd1[sel]->bits.false_ctl_d3_pd = 1;
943 break;
944 default:
945 break;
946 }
947 }
948
dphy_get_lane_state(unsigned int sel,enum dphy_lane lane)949 enum dphy_lane_state dphy_get_lane_state(unsigned int sel, enum dphy_lane lane)
950 {
951 switch (lane) {
952 case LANE_D0:
953 return (enum dphy_lane_state)dphy_dbg3[sel]->bits.lprx_sta_d0;
954 case LANE_D1:
955 return (enum dphy_lane_state)dphy_dbg3[sel]->bits.lprx_sta_d1;
956 case LANE_D2:
957 return (enum dphy_lane_state)dphy_dbg3[sel]->bits.lprx_sta_d2;
958 case LANE_D3:
959 return (enum dphy_lane_state)dphy_dbg3[sel]->bits.lprx_sta_d3;
960 case LANE_CLK:
961 return (enum dphy_lane_state)dphy_dbg3[sel]->bits.lprx_sta_clk;
962 default:
963 return -1;
964 }
965 }
966
dphy_get_hs_data(unsigned int sel,enum dphy_lane lane)967 unsigned char dphy_get_hs_data(unsigned int sel, enum dphy_lane lane)
968 {
969 switch (lane) {
970 case LANE_D0:
971 return dphy_dbg5[sel]->bits.hsrx_data0;
972 case LANE_D1:
973 return dphy_dbg5[sel]->bits.hsrx_data1;
974 case LANE_D2:
975 return dphy_dbg5[sel]->bits.hsrx_data2;
976 case LANE_D3:
977 return dphy_dbg5[sel]->bits.hsrx_data3;
978 default:
979 return -1;
980 }
981 }
982
dphy_ana_init(unsigned int sel)983 void dphy_ana_init(unsigned int sel)
984 {
985 dphy_ana0[sel]->bits.reg_pws = 1;
986 dphy_ana0[sel]->bits.reg_sfb = 2;
987 dphy_ana0[sel]->bits.reg_slv = 7;
988 dphy_ana1[sel]->bits.reg_svtt = 4;
989 dphy_ana0[sel]->bits.reg_dmpc = 0;
990 dphy_ana0[sel]->bits.reg_dmp = 0;
991 dphy_ana4[sel]->bits.reg_dmplvc = 1;
992 dphy_ana4[sel]->bits.reg_dmplvd = 1;
993
994 dphy_ana2[sel]->bits.enib = 1;
995 dphy_ana3[sel]->bits.enldor = 1;
996 dphy_ana3[sel]->bits.enldod = 1;
997 dphy_ana3[sel]->bits.enldoc = 1;
998 udelay(3);
999 dphy_ana3[sel]->bits.envttc = 0;
1000
1001 }
1002
dphy_ana_exit(unsigned int sel)1003 void dphy_ana_exit(unsigned int sel)
1004 {
1005 dphy_ana3[sel]->bits.envttc = 1;
1006 udelay(3);
1007 dphy_ana3[sel]->bits.enldoc = 0;
1008 dphy_ana3[sel]->bits.enldod = 0;
1009 dphy_ana3[sel]->bits.enldor = 0;
1010 dphy_ana2[sel]->bits.enib = 0;
1011 }
1012