1 /* 2 * Copyright (c) 2022 ASR Microelectronics (Shanghai) Co., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef _DUET_ADC_H_ 17 #define _DUET_ADC_H_ 18 19 #include "core_cm4.h" 20 #define ADC_ENABLE 21 22 #if defined ADC_ENABLE 23 typedef enum { 24 ADC_SAMPLE_1M, 25 ADC_SAMPLE_500K, 26 ADC_SAMPLE_250K, 27 ADC_SAMPLE_125K 28 } AUX_ADC_SMP_RATE; 29 30 #define AUX_ADC_CLK (1<<12) 31 #define ADC_SAMPLE_SEL ADC_SAMPLE_125K 32 #define AUX_ADC_IRQ (1<<20) 33 34 #define SYS_REG_BASE 0x40000000 35 #define SYS_REG_BASE_CLKCTRL_ENABLE ((SYS_REG_BASE + 0x844)) 36 #define SYS_REG_BASE_CLKCTRL_DISABLE ((SYS_REG_BASE + 0x84C)) 37 #define SYS_REG_BASE_IRQ_ENABLE ((SYS_REG_BASE + 0x944)) 38 #define SYS_REG_BASE_IRQ_DISABLE ((SYS_REG_BASE + 0x948)) 39 40 #define SYS_REG_BASE_AUXADC ((SYS_REG_BASE + 0x89000)) 41 #define SYS_REG_BASE_XOCTRL2 ((SYS_REG_BASE + 0xA70)) 42 #define SYS_REG_BASE_REF_ROOT_CLK ((SYS_REG_BASE + 0x80C)) 43 #define SYS_REG_BASE_WIFI_CLK ((SYS_REG_BASE + 0x85C)) 44 #define SYS_REG_BASE_AUXADC ((SYS_REG_BASE + 0x89000)) 45 typedef void (*duet_adc_callback_func)(void *arg); 46 47 typedef struct { 48 union { 49 struct { 50 __IO uint32_t adc_resv : 24; 51 __IO uint32_t adc_int_mode : 1; 52 __IO uint32_t adc_int_en : 1; 53 __IO uint32_t adc_int_clr : 1; 54 __IO uint32_t adc_resv1 : 5; 55 } BITS_ADC_CTRL; 56 __IO uint32_t ADC_CTRL; /* adc control */ 57 }; 58 __IO uint32_t ADC_DATA; 59 } duet_ADC; 60 #define ADC ((duet_ADC *)(SYS_REG_BASE_AUXADC)) 61 #define BIT(pos) (1U<<(pos)) 62 /* Modem Config */ 63 #define MDM_CLKGATEFCTRL0_ADDR 0x60C00874 64 65 typedef enum { 66 ADC_CHANNEL_NUM0, 67 ADC_CHANNEL_NUM1, 68 ADC_CHANNEL_NUM2, 69 ADC_CHANNEL_NUM3, 70 ADC_CHANNEL_NUM4, 71 ADC_CHANNEL_NUM5, 72 ADC_CHANNEL_NUM6, 73 ADC_CHANNEL_NUM7, 74 ADC_CHANNEL_TEMN, 75 ADC_CHANNEL_TEMP 76 } duet_adc_channel_t; 77 78 typedef struct { 79 uint32_t sampling_cycle; /* sampling period in number of ADC clock cycles */ 80 } duet_adc_config_t; 81 typedef enum { 82 MOD_TRIG, 83 MOD_CNT10 84 } AUX_ADC_MOD; 85 86 typedef struct { 87 uint8_t port; /* adc port */ 88 duet_adc_config_t config; /* adc config */ 89 void *priv; /* priv data */ 90 } duet_adc_dev_t; 91 92 int32_t duet_adc_init(duet_adc_dev_t *adc_config); 93 94 int32_t duet_adc_get(duet_adc_dev_t *adc_config); 95 96 int32_t duet_adc_finalize(duet_adc_dev_t *adc_config); 97 98 int32_t duet_tempr_get(duet_adc_dev_t *adc_config); 99 #endif 100 #endif // _duet_ADC_H_ 101