1 /*
2 * Copyright (c) 2022 ASR Microelectronics (Shanghai) Co., Ltd. All rights reserved.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15
16 #include "duet.h"
17 #include "duet_ram_layout.h"
18
19 #define WIFI_ADC_SHARED (32 * 1024)
20
duet_ram_layout_init(Tcm_Config_Type tcm_config,Wifi_Ram_Config_Type wifi_config,Bt_Ram_Config_Type bt_config)21 uint32_t duet_ram_layout_init(Tcm_Config_Type tcm_config, Wifi_Ram_Config_Type wifi_config,
22 Bt_Ram_Config_Type bt_config)
23 {
24 uint32_t tmp_value, reg_tcm = 0, reg_wifi = 0, reg_ble = 0;
25
26 if (tcm_config < 0 || tcm_config >= ITCM_DTCM_NUM) {
27 return -1;
28 }
29 if (wifi_config < 0 || wifi_config >= WIFI_RAM_NUM) {
30 return -1;
31 }
32 if (bt_config < 0 || bt_config >= BT_RAM_NUM) {
33 return -1;
34 }
35
36 switch (tcm_config) {
37 case ITCM_DTCM_32_192:
38 reg_tcm = 0;
39 break;
40 case ITCM_DTCM_96_128:
41 reg_tcm = 1;
42 break;
43 default:
44 return -1;
45 }
46
47 switch (wifi_config) {
48 case WIFI_RAM_0:
49 reg_wifi = 0;
50 break;
51 case WIFI_RAM_32:
52 reg_wifi = 1;
53 break;
54 case WIFI_RAM_64:
55 reg_wifi = 2;
56 break;
57 case WIFI_RAM_96:
58 reg_wifi = 4;
59 break;
60 default:
61 return -1;
62 }
63
64 switch (bt_config) {
65 case BT_RAM_0:
66 reg_ble = 0;
67 break;
68 case BT_RAM_16:
69 reg_ble = 1;
70 break;
71 case BT_RAM_32:
72 reg_ble = 3;
73 break;
74 default:
75 return -1;
76 }
77
78 tmp_value = REG_RD(0X40000000);
79 REG_WR(0X40000000, (tmp_value & ~0x00000001) | reg_tcm);
80
81 tmp_value = REG_RD(0X4000002C) & (~0x0000001f);
82 tmp_value |= (reg_ble << 3);
83 tmp_value |= (reg_wifi);
84 REG_WR(0X4000002C, (tmp_value));
85
86 return 0;
87 }
88
duet_get_ram_layout(Ram_Layout_Type * ram_layout)89 uint32_t duet_get_ram_layout(Ram_Layout_Type *ram_layout)
90 {
91 uint32_t reg_tcm = 0, reg_wifi = 0, reg_bt = 0;
92
93 if (ram_layout == 0) {
94 return -1;
95 }
96
97 reg_tcm = REG_RD(0X40000000) & 0x00000001;
98 if (reg_tcm == 0) {
99 ram_layout->itcm_addr = 0x00080000;
100 ram_layout->itcm_size = (32 * 1024);
101 ram_layout->dtcm_addr = 0x20FD0000;
102 ram_layout->dtcm_size = (192 * 1024);
103 } else {
104 ram_layout->itcm_addr = 0x00080000;
105 ram_layout->itcm_size = (96 * 1024);
106 ram_layout->dtcm_addr = 0x20FE0000;
107 ram_layout->dtcm_size = (128 * 1024);
108 }
109
110 ram_layout->soc_addr = 0x21000000;
111 ram_layout->wifi_addr = 0x60000000;
112 ram_layout->bt_addr = 0x62008000;
113
114 reg_wifi = REG_RD(0X4000002C) & 0x0000007;
115 if (reg_wifi == 1) {
116 ram_layout->wifi_size = (32 * 1024);
117 } else if (reg_wifi == 2) {
118 ram_layout->wifi_size = (64 * 1024);
119 } else if (reg_wifi == 4) {
120 ram_layout->wifi_size = (96 * 1024);
121 } else {
122 ram_layout->wifi_size = (0 * 1024);
123 }
124
125 reg_bt = (REG_RD(0X4000002C) & 0x00000018) >> 3;
126 if (reg_bt == 1) {
127 ram_layout->bt_size = (16 * 1024);
128 } else if (reg_bt == 3) {
129 ram_layout->bt_size = (32 * 1024);
130 } else {
131 ram_layout->bt_size = (0 * 1024);
132 }
133
134 ram_layout->soc_size = (128 * 1024) - ram_layout->wifi_size - ram_layout->bt_size;
135 ram_layout->wifi_size += WIFI_ADC_SHARED;
136
137 return 0;
138 }