1 /* 2 * drivers/amlogic/amports/encoder.h 3 * 4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 */ 17 18 #ifndef __H264_H__ 19 #define __H264_H__ 20 21 #include <linux/mutex.h> 22 #include <linux/semaphore.h> 23 #include <linux/list.h> 24 #include <linux/interrupt.h> 25 #include <linux/sched.h> 26 #include <linux/spinlock.h> 27 #include <linux/wait.h> 28 #include <linux/slab.h> 29 30 #ifdef CONFIG_AMLOGIC_MEDIA_GE2D 31 #include <linux/amlogic/media/ge2d/ge2d.h> 32 #endif 33 34 #include <linux/dma-buf.h> 35 36 #define AMVENC_DEVINFO_M8 "AML-M8" 37 #define AMVENC_DEVINFO_G9 "AML-G9" 38 #define AMVENC_DEVINFO_GXBB "AML-GXBB" 39 #define AMVENC_DEVINFO_GXTVBB "AML-GXTVBB" 40 #define AMVENC_DEVINFO_GXL "AML-GXL" 41 42 #define HCODEC_IRQ_MBOX_CLR HCODEC_ASSIST_MBOX2_CLR_REG 43 #define HCODEC_IRQ_MBOX_MASK HCODEC_ASSIST_MBOX2_MASK 44 45 #define H264_ENC_SVC 46 47 /* M8: 2550/10 = 255M GX: 2000/10 = 200M */ 48 #define HDEC_L0() WRITE_HHI_REG(HHI_VDEC_CLK_CNTL, \ 49 (2 << 25) | (1 << 16) | (1 << 24) | \ 50 (0xffff & READ_HHI_REG(HHI_VDEC_CLK_CNTL))) 51 /* M8: 2550/8 = 319M GX: 2000/8 = 250M */ 52 #define HDEC_L1() WRITE_HHI_REG(HHI_VDEC_CLK_CNTL, \ 53 (0 << 25) | (1 << 16) | (1 << 24) | \ 54 (0xffff & READ_HHI_REG(HHI_VDEC_CLK_CNTL))) 55 /* M8: 2550/7 = 364M GX: 2000/7 = 285M */ 56 #define HDEC_L2() WRITE_HHI_REG(HHI_VDEC_CLK_CNTL, \ 57 (3 << 25) | (0 << 16) | (1 << 24) | \ 58 (0xffff & READ_HHI_REG(HHI_VDEC_CLK_CNTL))) 59 /* M8: 2550/6 = 425M GX: 2000/6 = 333M */ 60 #define HDEC_L3() WRITE_HHI_REG(HHI_VDEC_CLK_CNTL, \ 61 (1 << 25) | (1 << 16) | (1 << 24) | \ 62 (0xffff & READ_HHI_REG(HHI_VDEC_CLK_CNTL))) 63 /* M8: 2550/5 = 510M GX: 2000/5 = 400M */ 64 #define HDEC_L4() WRITE_HHI_REG(HHI_VDEC_CLK_CNTL, \ 65 (2 << 25) | (0 << 16) | (1 << 24) | \ 66 (0xffff & READ_HHI_REG(HHI_VDEC_CLK_CNTL))) 67 /* M8: 2550/4 = 638M GX: 2000/4 = 500M */ 68 #define HDEC_L5() WRITE_HHI_REG(HHI_VDEC_CLK_CNTL, \ 69 (0 << 25) | (0 << 16) | (1 << 24) | \ 70 (0xffff & READ_HHI_REG(HHI_VDEC_CLK_CNTL))) 71 /* M8: 2550/3 = 850M GX: 2000/3 = 667M */ 72 #define HDEC_L6() WRITE_HHI_REG(HHI_VDEC_CLK_CNTL, \ 73 (1 << 25) | (0 << 16) | (1 << 24) | \ 74 (0xffff & READ_HHI_REG(HHI_VDEC_CLK_CNTL))) 75 76 #define hvdec_clock_enable(level) \ 77 do { \ 78 if (level == 0) \ 79 HDEC_L0(); \ 80 else if (level == 1) \ 81 HDEC_L1(); \ 82 else if (level == 2) \ 83 HDEC_L2(); \ 84 else if (level == 3) \ 85 HDEC_L3(); \ 86 else if (level == 4) \ 87 HDEC_L4(); \ 88 else if (level == 5) \ 89 HDEC_L5(); \ 90 else if (level == 6) \ 91 HDEC_L6(); \ 92 WRITE_VREG_BITS(DOS_GCLK_EN0, 0x7fff, 12, 15); \ 93 } while (0) 94 95 #define hvdec_clock_disable() \ 96 do { \ 97 WRITE_VREG_BITS(DOS_GCLK_EN0, 0, 12, 15); \ 98 WRITE_HHI_REG_BITS(HHI_VDEC_CLK_CNTL, 0, 24, 1); \ 99 } while (0) 100 101 #define LOG_ALL 0 102 #define LOG_INFO 1 103 #define LOG_DEBUG 2 104 #define LOG_ERROR 3 105 106 #define enc_pr(level, x...) \ 107 do { \ 108 if (level >= encode_print_level) \ 109 printk(x); \ 110 } while (0) 111 112 #define AMVENC_AVC_IOC_MAGIC 'E' 113 114 #define AMVENC_AVC_IOC_GET_DEVINFO _IOW(AMVENC_AVC_IOC_MAGIC, 0xf0, u32) 115 #define AMVENC_AVC_IOC_MAX_INSTANCE _IOW(AMVENC_AVC_IOC_MAGIC, 0xf1, u32) 116 117 #define AMVENC_AVC_IOC_GET_ADDR _IOW(AMVENC_AVC_IOC_MAGIC, 0x00, u32) 118 #define AMVENC_AVC_IOC_INPUT_UPDATE _IOW(AMVENC_AVC_IOC_MAGIC, 0x01, u32) 119 #define AMVENC_AVC_IOC_NEW_CMD _IOW(AMVENC_AVC_IOC_MAGIC, 0x02, u32) 120 #define AMVENC_AVC_IOC_GET_STAGE _IOW(AMVENC_AVC_IOC_MAGIC, 0x03, u32) 121 #define AMVENC_AVC_IOC_GET_OUTPUT_SIZE _IOW(AMVENC_AVC_IOC_MAGIC, 0x04, u32) 122 #define AMVENC_AVC_IOC_CONFIG_INIT _IOW(AMVENC_AVC_IOC_MAGIC, 0x05, u32) 123 #define AMVENC_AVC_IOC_FLUSH_CACHE _IOW(AMVENC_AVC_IOC_MAGIC, 0x06, u32) 124 #define AMVENC_AVC_IOC_FLUSH_DMA _IOW(AMVENC_AVC_IOC_MAGIC, 0x07, u32) 125 #define AMVENC_AVC_IOC_GET_BUFFINFO _IOW(AMVENC_AVC_IOC_MAGIC, 0x08, u32) 126 #define AMVENC_AVC_IOC_SUBMIT _IOW(AMVENC_AVC_IOC_MAGIC, 0x09, u32) 127 #define AMVENC_AVC_IOC_READ_CANVAS _IOW(AMVENC_AVC_IOC_MAGIC, 0x0a, u32) 128 #define AMVENC_AVC_IOC_QP_MODE _IOW(AMVENC_AVC_IOC_MAGIC, 0x0b, u32) 129 130 131 132 #define IE_PIPPELINE_BLOCK_SHIFT 0 133 #define IE_PIPPELINE_BLOCK_MASK 0x1f 134 #define ME_PIXEL_MODE_SHIFT 5 135 #define ME_PIXEL_MODE_MASK 0x3 136 137 enum amvenc_mem_type_e { 138 LOCAL_BUFF = 0, 139 CANVAS_BUFF, 140 PHYSICAL_BUFF, 141 DMA_BUFF, 142 MAX_BUFF_TYPE 143 }; 144 145 enum amvenc_frame_fmt_e { 146 FMT_YUV422_SINGLE = 0, 147 FMT_YUV444_SINGLE, 148 FMT_NV21, 149 FMT_NV12, 150 FMT_YUV420, 151 FMT_YUV444_PLANE, 152 FMT_RGB888, 153 FMT_RGB888_PLANE, 154 FMT_RGB565, 155 FMT_RGBA8888, 156 FMT_YUV422_12BIT, 157 FMT_YUV444_10BIT, 158 FMT_YUV422_10BIT, 159 FMT_BGR888, 160 MAX_FRAME_FMT 161 }; 162 163 #define MAX_ENCODE_REQUEST 8 /* 64 */ 164 165 #define MAX_ENCODE_INSTANCE 8 /* 64 */ 166 167 #define ENCODE_PROCESS_QUEUE_START 0 168 #define ENCODE_PROCESS_QUEUE_STOP 1 169 170 #define AMVENC_FLUSH_FLAG_INPUT 0x1 171 #define AMVENC_FLUSH_FLAG_OUTPUT 0x2 172 #define AMVENC_FLUSH_FLAG_REFERENCE 0x4 173 #define AMVENC_FLUSH_FLAG_INTRA_INFO 0x8 174 #define AMVENC_FLUSH_FLAG_INTER_INFO 0x10 175 #define AMVENC_FLUSH_FLAG_QP 0x20 176 #define AMVENC_FLUSH_FLAG_DUMP 0x40 177 #define AMVENC_FLUSH_FLAG_CBR 0x80 178 179 #define ENCODER_BUFFER_INPUT 0 180 #define ENCODER_BUFFER_REF0 1 181 #define ENCODER_BUFFER_REF1 2 182 #define ENCODER_BUFFER_OUTPUT 3 183 #define ENCODER_BUFFER_INTER_INFO 4 184 #define ENCODER_BUFFER_INTRA_INFO 5 185 #define ENCODER_BUFFER_QP 6 186 #define ENCODER_BUFFER_DUMP 7 187 #define ENCODER_BUFFER_CBR 8 188 189 struct encode_wq_s; 190 191 struct enc_dma_cfg { 192 int fd; 193 void *dev; 194 void *vaddr; 195 void *paddr; 196 struct dma_buf *dbuf; 197 struct dma_buf_attachment *attach; 198 struct sg_table *sg; 199 enum dma_data_direction dir; 200 }; 201 202 struct encode_request_s { 203 u32 quant; 204 u32 cmd; 205 u32 ucode_mode; 206 u32 src; 207 u32 framesize; 208 209 u32 me_weight; 210 u32 i4_weight; 211 u32 i16_weight; 212 213 u32 crop_top; 214 u32 crop_bottom; 215 u32 crop_left; 216 u32 crop_right; 217 u32 src_w; 218 u32 src_h; 219 u32 scale_enable; 220 221 u32 nr_mode; 222 u32 flush_flag; 223 u32 timeout; 224 enum amvenc_mem_type_e type; 225 enum amvenc_frame_fmt_e fmt; 226 struct encode_wq_s *parent; 227 struct enc_dma_cfg dma_cfg[3]; 228 u32 plane_num; 229 }; 230 231 struct encode_queue_item_s { 232 struct list_head list; 233 struct encode_request_s request; 234 }; 235 236 struct Buff_s { 237 u32 buf_start; 238 u32 buf_size; 239 bool used; 240 }; 241 242 struct BuffInfo_s { 243 u32 lev_id; 244 u32 min_buffsize; 245 u32 max_width; 246 u32 max_height; 247 struct Buff_s dct; 248 struct Buff_s dec0_y; 249 struct Buff_s dec0_uv; 250 struct Buff_s dec1_y; 251 struct Buff_s dec1_uv; 252 struct Buff_s assit; 253 struct Buff_s bitstream; 254 struct Buff_s scale_buff; 255 struct Buff_s dump_info; 256 struct Buff_s cbr_info; 257 }; 258 259 struct encode_meminfo_s { 260 u32 buf_start; 261 u32 buf_size; 262 263 u32 BitstreamStart; 264 u32 BitstreamEnd; 265 266 /*input buffer define*/ 267 u32 dct_buff_start_addr; 268 u32 dct_buff_end_addr; 269 270 /*microcode assitant buffer*/ 271 u32 assit_buffer_offset; 272 273 u32 scaler_buff_start_addr; 274 275 u32 dump_info_ddr_start_addr; 276 u32 dump_info_ddr_size; 277 278 u32 cbr_info_ddr_start_addr; 279 u32 cbr_info_ddr_size; 280 281 u8 * cbr_info_ddr_virt_addr; 282 283 s32 dblk_buf_canvas; 284 s32 ref_buf_canvas; 285 struct BuffInfo_s bufspec; 286 #ifdef CONFIG_CMA 287 struct page *venc_pages; 288 #endif 289 }; 290 291 struct encode_picinfo_s { 292 u32 encoder_width; 293 u32 encoder_height; 294 295 u32 rows_per_slice; 296 297 u32 idr_pic_id; /* need reset as 0 for IDR */ 298 u32 frame_number; /* need plus each frame */ 299 /* need reset as 0 for IDR and plus 2 for NON-IDR */ 300 u32 pic_order_cnt_lsb; 301 302 u32 log2_max_pic_order_cnt_lsb; 303 u32 log2_max_frame_num; 304 u32 init_qppicture; 305 #ifdef H264_ENC_SVC 306 u32 enable_svc; 307 u32 non_ref_limit; 308 u32 non_ref_cnt; 309 #endif 310 u32 color_space; 311 }; 312 313 struct encode_cbr_s { 314 u16 block_w; 315 u16 block_h; 316 u16 long_th; 317 u8 start_tbl_id; 318 u8 short_shift; 319 u8 long_mb_num; 320 }; 321 322 struct encode_wq_s { 323 struct list_head list; 324 325 /* dev info */ 326 u32 ucode_index; 327 u32 hw_status; 328 u32 output_size; 329 330 u32 sps_size; 331 u32 pps_size; 332 333 u32 me_weight; 334 u32 i4_weight; 335 u32 i16_weight; 336 337 u32 quant_tbl_i4[8]; 338 u32 quant_tbl_i16[8]; 339 u32 quant_tbl_me[8]; 340 341 struct encode_meminfo_s mem; 342 struct encode_picinfo_s pic; 343 struct encode_request_s request; 344 struct encode_cbr_s cbr_info; 345 atomic_t request_ready; 346 wait_queue_head_t request_complete; 347 }; 348 349 struct encode_event_s { 350 wait_queue_head_t hw_complete; 351 struct completion process_complete; 352 spinlock_t sem_lock; /* for queue switch and create destroy queue. */ 353 struct completion request_in_com; 354 }; 355 356 struct encode_manager_s { 357 struct list_head wq; 358 struct list_head process_queue; 359 struct list_head free_queue; 360 361 u32 encode_hw_status; 362 u32 process_queue_state; 363 s32 irq_num; 364 u32 wq_count; 365 u32 ucode_index; 366 u32 max_instance; 367 #ifdef CONFIG_AMLOGIC_MEDIA_GE2D 368 struct ge2d_context_s *context; 369 #endif 370 bool irq_requested; 371 bool need_reset; 372 bool process_irq; 373 bool inited; /* power on encode */ 374 bool remove_flag; /* remove wq; */ 375 bool uninit_flag; /* power off encode */ 376 bool use_reserve; 377 378 #ifdef CONFIG_CMA 379 bool check_cma; 380 ulong cma_pool_size; 381 #endif 382 struct platform_device *this_pdev; 383 struct Buff_s *reserve_buff; 384 struct encode_wq_s *current_wq; 385 struct encode_wq_s *last_wq; 386 struct encode_queue_item_s *current_item; 387 struct task_struct *encode_thread; 388 struct Buff_s reserve_mem; 389 struct encode_event_s event; 390 struct tasklet_struct encode_tasklet; 391 }; 392 393 extern s32 encode_wq_add_request(struct encode_wq_s *wq); 394 extern struct encode_wq_s *create_encode_work_queue(void); 395 extern s32 destroy_encode_work_queue(struct encode_wq_s *encode_work_queue); 396 397 /******************************************** 398 * AV Scratch Register Re-Define 399 ****************************************** * 400 */ 401 #define ENCODER_STATUS HCODEC_HENC_SCRATCH_0 402 #define MEM_OFFSET_REG HCODEC_HENC_SCRATCH_1 403 #define DEBUG_REG HCODEC_HENC_SCRATCH_2 404 #define IDR_PIC_ID HCODEC_HENC_SCRATCH_5 405 #define FRAME_NUMBER HCODEC_HENC_SCRATCH_6 406 #define PIC_ORDER_CNT_LSB HCODEC_HENC_SCRATCH_7 407 #define LOG2_MAX_PIC_ORDER_CNT_LSB HCODEC_HENC_SCRATCH_8 408 #define LOG2_MAX_FRAME_NUM HCODEC_HENC_SCRATCH_9 409 #define ANC0_BUFFER_ID HCODEC_HENC_SCRATCH_A 410 #define QPPICTURE HCODEC_HENC_SCRATCH_B 411 412 #define IE_ME_MB_TYPE HCODEC_HENC_SCRATCH_D 413 414 /* bit 0-4, IE_PIPPELINE_BLOCK 415 * bit 5 me half pixel in m8 416 * disable i4x4 in gxbb 417 * bit 6 me step2 sub pixel in m8 418 * disable i16x16 in gxbb 419 */ 420 #define IE_ME_MODE HCODEC_HENC_SCRATCH_E 421 #define IE_REF_SEL HCODEC_HENC_SCRATCH_F 422 423 /* [31:0] NUM_ROWS_PER_SLICE_P */ 424 /* [15:0] NUM_ROWS_PER_SLICE_I */ 425 #define FIXED_SLICE_CFG HCODEC_HENC_SCRATCH_L 426 427 /* For GX */ 428 #define INFO_DUMP_START_ADDR HCODEC_HENC_SCRATCH_I 429 430 /* For CBR */ 431 #define H264_ENC_CBR_TABLE_ADDR HCODEC_HENC_SCRATCH_3 432 #define H264_ENC_CBR_MB_SIZE_ADDR HCODEC_HENC_SCRATCH_4 433 /* Bytes(Float) * 256 */ 434 #define H264_ENC_CBR_CTL HCODEC_HENC_SCRATCH_G 435 /* [31:28] : init qp table idx */ 436 /* [27:24] : short_term adjust shift */ 437 /* [23:16] : Long_term MB_Number between adjust, */ 438 /* [15:0] Long_term adjust threshold(Bytes) */ 439 #define H264_ENC_CBR_TARGET_SIZE HCODEC_HENC_SCRATCH_H 440 /* Bytes(Float) * 256 */ 441 #define H264_ENC_CBR_PREV_BYTES HCODEC_HENC_SCRATCH_J 442 #define H264_ENC_CBR_REGION_SIZE HCODEC_HENC_SCRATCH_J 443 444 /* for SVC */ 445 #define H264_ENC_SVC_PIC_TYPE HCODEC_HENC_SCRATCH_K 446 447 /* define for PIC header */ 448 #define ENC_SLC_REF 0x8410 449 #define ENC_SLC_NON_REF 0x8010 450 451 /* --------------------------------------------------- */ 452 /* ENCODER_STATUS define */ 453 /* --------------------------------------------------- */ 454 #define ENCODER_IDLE 0 455 #define ENCODER_SEQUENCE 1 456 #define ENCODER_PICTURE 2 457 #define ENCODER_IDR 3 458 #define ENCODER_NON_IDR 4 459 #define ENCODER_MB_HEADER 5 460 #define ENCODER_MB_DATA 6 461 462 #define ENCODER_SEQUENCE_DONE 7 463 #define ENCODER_PICTURE_DONE 8 464 #define ENCODER_IDR_DONE 9 465 #define ENCODER_NON_IDR_DONE 10 466 #define ENCODER_MB_HEADER_DONE 11 467 #define ENCODER_MB_DATA_DONE 12 468 469 #define ENCODER_NON_IDR_INTRA 13 470 #define ENCODER_NON_IDR_INTER 14 471 472 #define ENCODER_ERROR 0xff 473 474 /******************************************** 475 * defines for H.264 mb_type 476 ******************************************* 477 */ 478 #define HENC_MB_Type_PBSKIP 0x0 479 #define HENC_MB_Type_PSKIP 0x0 480 #define HENC_MB_Type_BSKIP_DIRECT 0x0 481 #define HENC_MB_Type_P16x16 0x1 482 #define HENC_MB_Type_P16x8 0x2 483 #define HENC_MB_Type_P8x16 0x3 484 #define HENC_MB_Type_SMB8x8 0x4 485 #define HENC_MB_Type_SMB8x4 0x5 486 #define HENC_MB_Type_SMB4x8 0x6 487 #define HENC_MB_Type_SMB4x4 0x7 488 #define HENC_MB_Type_P8x8 0x8 489 #define HENC_MB_Type_I4MB 0x9 490 #define HENC_MB_Type_I16MB 0xa 491 #define HENC_MB_Type_IBLOCK 0xb 492 #define HENC_MB_Type_SI4MB 0xc 493 #define HENC_MB_Type_I8MB 0xd 494 #define HENC_MB_Type_IPCM 0xe 495 #define HENC_MB_Type_AUTO 0xf 496 497 #define HENC_MB_CBP_AUTO 0xff 498 #define HENC_SKIP_RUN_AUTO 0xffff 499 500 501 extern bool amvenc_avc_on(void); 502 #endif 503