1 /* 2 * linux-5.4/drivers/media/platform/sunxi-vin/vin-mipi/protocol/protocol_reg_i.h 3 * 4 * Copyright (c) 2007-2017 Allwinnertech Co., Ltd. 5 * 6 * This software is licensed under the terms of the GNU General Public 7 * License version 2, as published by the Free Software Foundation, and 8 * may be copied, distributed, and modified under those terms. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 */ 16 17 18 #ifndef __PROTOCOL_REG_I__H__ 19 #define __PROTOCOL_REG_I__H__ 20 21 #ifdef __cplusplus 22 extern "C" { 23 #endif 24 25 #define MIPI_CSI2_CTL_OFF 0x0000 26 #define MIPI_CSI2_CFG_OFF 0x0004 27 #define MIPI_CSI2_VCDT_RX_OFF 0x0008 28 #define MIPI_CSI2_RX_PKT_NUM_OFF 0x000C 29 #define MIPI_CSI2_VER_OFF 0x003C 30 #define MIPI_CSI2_CH_CFG_OFF 0x0040 31 #define MIPI_CSI2_CH_INT_EN_OFF 0x0050 32 #define MIPI_CSI2_CH_INT_PD_OFF 0x0058 33 #define MIPI_CSI2_CH_DT_TRM_OFF 0x0060 34 #define MIPI_CSI2_CH_CUR_PH_OFF 0x0070 35 #define MIPI_CSI2_CH_ECC_OFF 0x0074 36 #define MIPI_CSI2_CH_CKS_OFF 0x0078 37 #define MIPI_CSI2_CH_FRAME_NUM_OFF 0x007C 38 #define MIPI_CSI2_CH_LINE_NUM_OFF 0x0080 39 40 #define MIPI_CSI2_CH_OFF 0x0100 41 42 #define MIPI_CSI2_CTL_ADDR (MIPI_CSI0_VBASE + MIPI_CSI2_CTL_OFF) 43 #define MIPI_CSI2_CFG_ADDR (MIPI_CSI0_VBASE + MIPI_CSI2_CFG_OFF) 44 #define MIPI_CSI2_VCDT_RX_ADDR (MIPI_CSI0_VBASE + MIPI_CSI2_VCDT_RX_OFF) 45 #define MIPI_CSI2_RX_PKT_NUM_ADDR (MIPI_CSI0_VBASE + MIPI_CSI2_RX_PKT_NUM_OFF) 46 #define MIPI_CSI2_VER_ADDR (MIPI_CSI0_VBASE + MIPI_CSI2_VER_OFF) 47 #define MIPI_CSI2_CH_CFG_ADDR (MIPI_CSI0_VBASE + MIPI_CSI2_CH_CFG_OFF) 48 #define MIPI_CSI2_CH_INT_EN_ADDR (MIPI_CSI0_VBASE + MIPI_CSI2_CH_INT_EN_OFF) 49 #define MIPI_CSI2_CH_INT_PD_ADDR (MIPI_CSI0_VBASE + MIPI_CSI2_CH_INT_PD_OFF) 50 #define MIPI_CSI2_CH_DT_TRM_ADDR (MIPI_CSI0_VBASE + MIPI_CSI2_CH_DT_TRM_OFF) 51 #define MIPI_CSI2_CH_CUR_PH_ADDR (MIPI_CSI0_VBASE + MIPI_CSI2_CH_CUR_PH_OFF) 52 #define MIPI_CSI2_CH_ECC_ADDR (MIPI_CSI0_VBASE + MIPI_CSI2_CH_ECC_OFF) 53 #define MIPI_CSI2_CH_CKS_ADDR (MIPI_CSI0_VBASE + MIPI_CSI2_CH_CKS_OFF) 54 #define MIPI_CSI2_CH_FRAME_NUM_ADDR (MIPI_CSI0_VBASE + MIPI_CSI2_CH_FRAME_NUM_OFF) 55 #define MIPI_CSI2_CH_LINE_NUM_ADDR (MIPI_CSI0_VBASE + MIPI_CSI2_CH_LINE_NUM_OFF) 56 57 typedef union { 58 unsigned int dwval; 59 struct { 60 unsigned int en:1; 61 unsigned int unpk_en:1; 62 unsigned int res0:28; 63 unsigned int ver_en:1; 64 unsigned int rst:1; 65 } bits; 66 } MIPI_CSI2_CTL_t; 67 68 typedef union { 69 unsigned int dwval; 70 struct { 71 unsigned int dl_cfg:2; 72 unsigned int res0:2; 73 unsigned int ph_byte_ord:2; 74 unsigned int ph_bit_ord:1; 75 unsigned int pl_bit_ord:1; 76 unsigned int ch_mode:2; 77 unsigned int res1:22; 78 } bits; 79 } MIPI_CSI2_CFG_t; 80 81 typedef union { 82 unsigned int dwval; 83 struct { 84 unsigned int ch0_dt:6; 85 unsigned int ch0_vc:2; 86 unsigned int ch1_dt:6; 87 unsigned int ch1_vc:2; 88 unsigned int ch2_dt:6; 89 unsigned int ch2_vc:2; 90 unsigned int ch3_dt:6; 91 unsigned int ch3_vc:2; 92 } bits; 93 } MIPI_CSI2_VCDT_RX_t; 94 95 typedef union { 96 unsigned int dwval; 97 struct { 98 unsigned int pkt_num; 99 } bits; 100 } MIPI_CSI2_RX_PKT_NUM_t; 101 102 typedef union { 103 unsigned int dwval; 104 struct { 105 unsigned int ver; 106 } bits; 107 } MIPI_CSI2_VER_t; 108 109 typedef union { 110 unsigned int dwval; 111 struct { 112 unsigned int line_sync:1; 113 unsigned int embd_dat_en:1; 114 unsigned int itl_sync:1; 115 unsigned int src_sel:1; 116 unsigned int res0:28; 117 } bits; 118 } MIPI_CSI2_CH_CFG_t; 119 120 typedef union { 121 unsigned int dwval; 122 struct { 123 unsigned int fifo_over_int:1; 124 unsigned int res0:7; 125 unsigned int frame_end_sync_int:1; 126 unsigned int frame_start_sync_int:1; 127 unsigned int line_end_sync_int:1; 128 unsigned int line_start_sync_int:1; 129 unsigned int res1:4; 130 unsigned int ph_update_int:1; 131 unsigned int pf_int:1; 132 unsigned int emb_data_int:1; 133 unsigned int res2:5; 134 unsigned int frame_sync_err_int:1; 135 unsigned int line_sync_err_int:1; 136 unsigned int ecc_err_int:1; 137 unsigned int ecc_wrn_int:1; 138 unsigned int chksum_err_int:1; 139 unsigned int eot_err_int:1; 140 unsigned int res3:2; 141 } bits; 142 } MIPI_CSI2_CH_INT_EN_t; 143 144 typedef union { 145 unsigned int dwval; 146 struct { 147 unsigned int fifo_over_pd:1; 148 unsigned int res0:7; 149 unsigned int frame_end_sync_pd:1; 150 unsigned int frame_start_sync_pd:1; 151 unsigned int line_end_sync_pd:1; 152 unsigned int line_start_sync_pd:1; 153 unsigned int res1:4; 154 unsigned int ph_update_pd:1; 155 unsigned int pf_pd:1; 156 unsigned int emb_data_pd:1; 157 unsigned int res2:5; 158 unsigned int frame_sync_err_pd:1; 159 unsigned int line_sync_err_pd:1; 160 unsigned int ecc_err_pd:1; 161 unsigned int ecc_wrn_pd:1; 162 unsigned int chksum_err_pd:1; 163 unsigned int eot_err_pd:1; 164 unsigned int res3:2; 165 } bits; 166 } MIPI_CSI2_CH_INT_PD_t; 167 168 typedef union { 169 unsigned int dwval; 170 struct { 171 unsigned int fs:1; 172 unsigned int fe:1; 173 unsigned int ls:1; 174 unsigned int le:1; 175 unsigned int res0:4; 176 unsigned int gs0:1; 177 unsigned int gs1:1; 178 unsigned int gs2:1; 179 unsigned int gs3:1; 180 unsigned int gs4:1; 181 unsigned int gs5:1; 182 unsigned int gs6:1; 183 unsigned int gs7:1; 184 unsigned int gl:1; 185 unsigned int yuv:1; 186 unsigned int rgb:1; 187 unsigned int raw:1; 188 unsigned int res1:12; 189 } bits; 190 } MIPI_CSI2_CH_DT_TRM_t; 191 192 typedef union { 193 unsigned int dwval; 194 struct { 195 unsigned int cur_dt:6; 196 unsigned int cur_vc:2; 197 unsigned int res0:8; 198 unsigned int cur_wc:16; 199 } bits; 200 } MIPI_CSI2_CH_CUR_PH_t; 201 202 typedef union { 203 unsigned int dwval; 204 struct { 205 unsigned int rxd_ecc:8; 206 unsigned int res0:8; 207 unsigned int cal_ecc:8; 208 unsigned int res1:8; 209 } bits; 210 } MIPI_CSI2_CH_ECC_t; 211 212 typedef union { 213 unsigned int dwval; 214 struct { 215 unsigned int rxd_cks:16; 216 unsigned int cal_cks:16; 217 } bits; 218 } MIPI_CSI2_CH_CKS_t; 219 220 typedef union { 221 unsigned int dwval; 222 struct { 223 unsigned int frame_num:16; 224 unsigned int res0:16; 225 } bits; 226 } MIPI_CSI2_CH_FRAME_NUM_t; 227 228 typedef union { 229 unsigned int dwval; 230 struct { 231 unsigned int line_num:16; 232 unsigned int res0:16; 233 } bits; 234 } MIPI_CSI2_CH_LINE_NUM_t; 235 236 #ifdef __cplusplus 237 } 238 #endif 239 240 #endif 241