1 /*
2 * drivers/usb/sunxi_usb/udc/sunxi_udc.c
3 * (C) Copyright 2010-2015
4 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
5 * javen, 2010-3-3, create this file
6 *
7 * usb device contoller driver
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 */
15
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/delay.h>
19 #include <linux/ioport.h>
20 #include <linux/sched.h>
21 #include <linux/slab.h>
22 #include <linux/errno.h>
23 #include <linux/init.h>
24 #include <linux/timer.h>
25 #include <linux/list.h>
26 #include <linux/interrupt.h>
27 #include <linux/platform_device.h>
28 #include <linux/clk.h>
29 #include <linux/reset.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/prefetch.h>
32
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35
36 #include <asm/byteorder.h>
37 #include <asm/io.h>
38 #include <asm/irq.h>
39 #include <asm/unaligned.h>
40
41 #include <linux/regulator/consumer.h>
42
43 #include "sunxi_udc_config.h"
44 #include "sunxi_udc_board.h"
45
46 #include "sunxi_udc_debug.h"
47 #include "sunxi_udc_dma.h"
48 #include <linux/of.h>
49 #include <linux/of_address.h>
50 #include <linux/of_device.h>
51 #include <linux/dma-mapping.h>
52
53 #if defined(CONFIG_POWER_SUPPLY)
54 #include <linux/power_supply.h>
55 #endif
56
57 #define DRIVER_DESC "SoftWinner USB Device Controller"
58 #define DRIVER_AUTHOR "SoftWinner USB Developer"
59
60 static const char gadget_name[] = "sunxi_usb_udc";
61 static const char driver_desc[] = DRIVER_DESC;
62
63 static u64 sunxi_udc_mask = ~0ULL; // DMA_BIT_MASK(64); /* Avoid Clang waring: shift count >= width of type */
64
65 static struct sunxi_udc *the_controller;
66 static u32 usbd_port_no;
67 static sunxi_udc_io_t g_sunxi_udc_io;
68 static u32 usb_connect;
69 static u32 is_controller_alive;
70 static u8 is_udc_enable; /* is udc enable by gadget? */
71
72 static bool charger_mode;
73
74 static struct platform_device *g_udc_pdev;
75
76 static __u32 dma_working;
77
78 static __u8 first_enable = 1;
79
80 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
81
82 static u8 crq_bRequest;
83 static u8 crq_wIndex;
84 static const unsigned char TestPkt[54] = {
85 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xAA,
86 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xEE, 0xEE, 0xEE,
87 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF,
88 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x7F, 0xBF, 0xDF,
89 0xEF, 0xF7, 0xFB, 0xFD, 0xFC, 0x7E, 0xBF, 0xDF, 0xEF, 0xF7,
90 0xFB, 0xFD, 0x7E, 0x00
91 };
92
93 /* debug */
94 unsigned static int g_queue_debug;
95 int g_dma_debug;
96 unsigned static int g_write_debug;
97 unsigned static int g_read_debug;
98 unsigned static int g_irq_debug;
99 unsigned static int g_msc_write_debug;
100 unsigned static int g_msc_read_debug;
101
102
103
show_ed_test(struct device * dev,struct device_attribute * attr,char * buf)104 static ssize_t show_ed_test(struct device *dev,
105 struct device_attribute *attr, char *buf)
106 {
107
108 return sprintf(buf, "%d\n", g_queue_debug);
109 }
110
ed_test(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)111 static ssize_t ed_test(struct device *dev,
112 struct device_attribute *attr,
113 const char *buf, size_t count)
114 {
115 void __iomem *fifo = NULL;
116 int reg_val;
117
118 if (!strncmp(buf, "test_j_state", 12)) {
119 USBC_EnterMode_Test_J(g_sunxi_udc_io.usb_bsp_hdle);
120 DMSG_INFO("test_mode:%s\n", "test_j_state");
121 } else if (!strncmp(buf, "test_k_state", 12)) {
122 USBC_EnterMode_Test_K(g_sunxi_udc_io.usb_bsp_hdle);
123 DMSG_INFO("test_mode:%s\n", "test_k_state");
124 } else if (!strncmp(buf, "test_se0_nak", 12)) {
125 USBC_EnterMode_Test_SE0_NAK(g_sunxi_udc_io.usb_bsp_hdle);
126 DMSG_INFO("test_mode:%s\n", "test_se0_nak");
127 } else if (!strncmp(buf, "test_pack", 9)) {
128 DMSG_INFO("test_mode___:%s\n", "test_pack");
129 reg_val = USBC_Readl(USBC_REG_PCTL(g_sunxi_udc_io.usb_vbase));
130 reg_val |= (0x1 << 0);
131 USBC_Writel(reg_val, USBC_REG_PCTL(g_sunxi_udc_io.usb_vbase));
132 msleep(1000);
133 fifo = USBC_SelectFIFO(g_sunxi_udc_io.usb_bsp_hdle, 0);
134 USBC_WritePacket(g_sunxi_udc_io.usb_bsp_hdle,
135 fifo, 54, (u32 *)TestPkt);
136 USBC_Dev_WriteDataStatus(g_sunxi_udc_io.usb_bsp_hdle,
137 USBC_EP_TYPE_EP0, 0);
138 USBC_EnterMode_TestPacket(g_sunxi_udc_io.usb_bsp_hdle);
139 } else if (!strncmp(buf, "disable_test_mode", 17)) {
140 DMSG_INFO("start disable_test_mode\n");
141 USBC_EnterMode_Idle(g_sunxi_udc_io.usb_bsp_hdle);
142 } else {
143 DMSG_PANIC("ERR: test_mode Argment is invalid\n");
144 }
145
146 return count;
147 }
148
149 static DEVICE_ATTR(otg_ed_test, 0644, show_ed_test, ed_test);
150
show_phy_range(struct device * dev,struct device_attribute * attr,char * buf)151 static ssize_t show_phy_range(struct device *dev,
152 struct device_attribute *attr, char *buf)
153 {
154 return sprintf(buf, "rate:0x%x\n",
155 USBC_Phyx_Read(g_sunxi_udc_io.usb_bsp_hdle));
156 }
157
udc_phy_range(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)158 static ssize_t udc_phy_range(struct device *dev, struct device_attribute *attr,
159 const char *buf, size_t count)
160 {
161 int val = 0;
162 int err;
163
164 if (dev == NULL) {
165 DMSG_PANIC("ERR: Argment is invalid\n");
166 return 0;
167 }
168
169 err = kstrtoint(buf, 16, &val);
170 if (err != 0)
171 return -EINVAL;
172
173 if ((val >= 0x0) && (val <= 0x3ff)) {
174 USBC_Phyx_Write(g_sunxi_udc_io.usb_bsp_hdle, val);
175 } else {
176 DMSG_PANIC("adjust PHY's paraments 0x%x is fail! value:0x0~0x3ff\n", val);
177 return count;
178 }
179
180 DMSG_INFO("adjust succeed, PHY's paraments:0x%x.\n",
181 USBC_Phyx_Read(g_sunxi_udc_io.usb_bsp_hdle));
182
183 return count;
184 }
185
186 static DEVICE_ATTR(otg_phy_range, 0644, show_phy_range, udc_phy_range);
187
188
show_udc_debug(struct device * dev,struct device_attribute * attr,char * buf)189 static ssize_t show_udc_debug(struct device *dev,
190 struct device_attribute *attr, char *buf)
191 {
192 return sprintf(buf, "%d\n", g_queue_debug);
193 }
194
udc_queue_debug(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)195 static ssize_t udc_queue_debug(struct device *dev,
196 struct device_attribute *attr,
197 const char *buf, size_t count)
198 {
199 int debug = 0;
200 int ret = 0;
201
202 ret = kstrtoint(buf, 0, &debug);
203 if (ret != 0)
204 return ret;
205
206 g_queue_debug = debug;
207
208 return count;
209 }
210
211 static DEVICE_ATTR(queue_debug, 0644, show_udc_debug, udc_queue_debug);
212
show_dma_debug(struct device * dev,struct device_attribute * attr,char * buf)213 static ssize_t show_dma_debug(struct device *dev,
214 struct device_attribute *attr, char *buf)
215 {
216 return sprintf(buf, "%d\n", g_dma_debug);
217 }
218
udc_dma_debug(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)219 static ssize_t udc_dma_debug(struct device *dev,
220 struct device_attribute *attr,
221 const char *buf, size_t count)
222 {
223 int debug = 0;
224 int ret = 0;
225
226 ret = kstrtoint(buf, 0, &debug);
227 if (ret != 0)
228 return ret;
229
230 g_dma_debug = debug;
231
232 return count;
233 }
234
235 static DEVICE_ATTR(dma_debug, 0644, show_dma_debug, udc_dma_debug);
236
show_write_debug(struct device * dev,struct device_attribute * attr,char * buf)237 static ssize_t show_write_debug(struct device *dev,
238 struct device_attribute *attr, char *buf)
239 {
240 return sprintf(buf, "%d\n", g_write_debug);
241 }
242
udc_write_debug(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)243 static ssize_t udc_write_debug(struct device *dev,
244 struct device_attribute *attr,
245 const char *buf, size_t count)
246 {
247 int debug = 0;
248 int ret = 0;
249
250 ret = kstrtoint(buf, 0, &debug);
251 if (ret != 0)
252 return ret;
253
254 g_write_debug = debug;
255
256 return count;
257 }
258
259 static DEVICE_ATTR(write_debug, 0644, show_write_debug, udc_write_debug);
260
show_read_debug(struct device * dev,struct device_attribute * attr,char * buf)261 static ssize_t show_read_debug(struct device *dev,
262 struct device_attribute *attr, char *buf)
263 {
264 return sprintf(buf, "%d\n", g_read_debug);
265 }
266
udc_read_debug(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)267 static ssize_t udc_read_debug(struct device *dev,
268 struct device_attribute *attr,
269 const char *buf, size_t count)
270 {
271 int debug = 0;
272 int ret = 0;
273
274 ret = kstrtoint(buf, 0, &debug);
275 if (ret != 0)
276 return ret;
277
278 g_read_debug = debug;
279
280 return count;
281 }
282
283 static DEVICE_ATTR(read_debug, 0644, show_read_debug, udc_read_debug);
284
show_irq_debug(struct device * dev,struct device_attribute * attr,char * buf)285 static ssize_t show_irq_debug(struct device *dev,
286 struct device_attribute *attr, char *buf)
287 {
288 return sprintf(buf, "%d\n", g_irq_debug);
289 }
290
udc_irq_debug(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)291 static ssize_t udc_irq_debug(struct device *dev,
292 struct device_attribute *attr,
293 const char *buf, size_t count)
294 {
295 int debug = 0;
296 int ret = 0;
297
298 ret = kstrtoint(buf, 0, &debug);
299 if (ret != 0)
300 return ret;
301
302 g_irq_debug = debug;
303
304 return count;
305 }
306
307 static DEVICE_ATTR(irq_debug, 0644, show_irq_debug, udc_irq_debug);
308
show_msc_write_debug(struct device * dev,struct device_attribute * attr,char * buf)309 static ssize_t show_msc_write_debug(struct device *dev,
310 struct device_attribute *attr, char *buf)
311 {
312 return sprintf(buf, "%d\n", g_msc_write_debug);
313 }
314
udc_msc_write_debug(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)315 static ssize_t udc_msc_write_debug(struct device *dev,
316 struct device_attribute *attr,
317 const char *buf, size_t count)
318 {
319 int debug = 0;
320 int ret = 0;
321
322 ret = kstrtoint(buf, 0, &debug);
323 if (ret != 0)
324 return ret;
325
326 g_msc_write_debug = debug;
327
328 return count;
329 }
330
331 static DEVICE_ATTR(msc_write_debug, 0644,
332 show_msc_write_debug, udc_msc_write_debug);
333
show_msc_read_debug(struct device * dev,struct device_attribute * attr,char * buf)334 static ssize_t show_msc_read_debug(struct device *dev,
335 struct device_attribute *attr, char *buf)
336 {
337 return sprintf(buf, "%d\n", g_msc_read_debug);
338 }
339
udc_msc_read_debug(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)340 static ssize_t udc_msc_read_debug(struct device *dev,
341 struct device_attribute *attr,
342 const char *buf, size_t count)
343 {
344 int debug = 0;
345 int ret = 0;
346
347 ret = kstrtoint(buf, 0, &debug);
348 if (ret != 0)
349 return ret;
350
351 g_msc_read_debug = debug;
352
353 return count;
354 }
355
356 static DEVICE_ATTR(msc_read_debug, 0644,
357 show_msc_read_debug, udc_msc_read_debug);
358
359 /* function defination */
360 static void cfg_udc_command(enum sunxi_udc_cmd_e cmd);
361 static void cfg_vbus_draw(unsigned int ma);
362
is_peripheral_active(void)363 static __u32 is_peripheral_active(void)
364 {
365 return is_controller_alive;
366 }
367
368 /**
369 * DMA transfer conditions:
370 * 1. the driver support dma transfer
371 * 2. not EP0
372 * 3. more than one packet
373 */
374 #define big_req(req, ep) ((req->req.length != req->req.actual) \
375 ? ((req->req.length >= 512) \
376 && ((req->req.length - req->req.actual) \
377 > ep->ep.maxpacket)) \
378 : (req->req.length > ep->ep.maxpacket))
379 #define is_sunxi_udc_dma_capable(req, ep) (is_udc_support_dma() \
380 && big_req(req, ep) \
381 && ep->num)
382
383 #define is_buffer_mapped(req, ep) (is_sunxi_udc_dma_capable(req, ep) \
384 && (req->map_state != UN_MAPPED))
385
sunxi_set_cur_vol_work(struct work_struct * work)386 void sunxi_set_cur_vol_work(struct work_struct *work)
387 {
388 #if !defined(SUNXI_USB_FPGA) && defined(CONFIG_POWER_SUPPLY)
389 struct power_supply *psy = NULL;
390 union power_supply_propval temp;
391 struct device_node *np = NULL;
392
393 if (of_find_property(g_udc_pdev->dev.of_node, "det_vbus_supply", NULL))
394 psy = devm_power_supply_get_by_phandle(&g_udc_pdev->dev,
395 "det_vbus_supply");
396
397 if (!psy || IS_ERR(psy)) {
398 DMSG_PANIC("%s()%d WARN: get power supply failed\n",
399 __func__, __LINE__);
400 } else {
401 temp.intval = 500;
402 /*
403 * When connect to PC, we will parse dts to get current limit value.
404 * If get failed, we will set default value 500.
405 */
406 np = of_parse_phandle(g_udc_pdev->dev.of_node, "det_vbus_supply", 0);
407 if (np)
408 of_property_read_u32(np, "pmu_usbpc_cur", &temp.intval);
409
410 power_supply_set_property(psy,
411 POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT, &temp);
412 }
413 #endif
414 }
415
416 /* Maps the buffer to dma */
sunxi_udc_map_dma_buffer(struct sunxi_udc_request * req,struct sunxi_udc * udc,struct sunxi_udc_ep * ep)417 static inline void sunxi_udc_map_dma_buffer(
418 struct sunxi_udc_request *req,
419 struct sunxi_udc *udc,
420 struct sunxi_udc_ep *ep)
421 {
422 if (!is_sunxi_udc_dma_capable(req, ep)) {
423 DMSG_PANIC("err: need not to dma map\n");
424 return;
425 }
426
427 req->map_state = UN_MAPPED;
428
429 if (req->req.dma == DMA_ADDR_INVALID) {
430 req->req.dma = dma_map_single(
431 udc->controller,
432 req->req.buf,
433 req->req.length,
434 (is_tx_ep(ep) ? DMA_TO_DEVICE
435 : DMA_FROM_DEVICE));
436 if (dma_mapping_error(udc->controller,
437 req->req.dma)){
438 DMSG_PANIC("dma_mapping_error, %p, %x\n",
439 req->req.buf, req->req.length);
440 return;
441 }
442 req->map_state = SW_UDC_USB_MAPPED;
443 } else {
444 dma_sync_single_for_device(udc->controller,
445 req->req.dma,
446 req->req.length,
447 (is_tx_ep(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
448 req->map_state = PRE_MAPPED;
449 }
450 }
451
452 /* Unmap the buffer from dma and maps it back to cpu */
sunxi_udc_unmap_dma_buffer(struct sunxi_udc_request * req,struct sunxi_udc * udc,struct sunxi_udc_ep * ep)453 static inline void sunxi_udc_unmap_dma_buffer(
454 struct sunxi_udc_request *req,
455 struct sunxi_udc *udc,
456 struct sunxi_udc_ep *ep)
457 {
458 if (!is_buffer_mapped(req, ep))
459 return;
460
461 if (req->req.dma == DMA_ADDR_INVALID) {
462 DMSG_PANIC("not unmapping a never mapped buffer\n");
463 return;
464 }
465
466 if (req->map_state == SW_UDC_USB_MAPPED) {
467 dma_unmap_single(udc->controller,
468 req->req.dma,
469 req->req.length,
470 (is_tx_ep(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
471
472 req->req.dma = DMA_ADDR_INVALID;
473 } else { /* PRE_MAPPED */
474 dma_sync_single_for_cpu(udc->controller,
475 req->req.dma,
476 req->req.length,
477 (is_tx_ep(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
478 }
479
480 req->map_state = UN_MAPPED;
481 }
482
sunxi_udc_handle_unaligned_buf_start(struct sunxi_udc_ep * ep,struct sunxi_udc_request * req)483 static int sunxi_udc_handle_unaligned_buf_start(struct sunxi_udc_ep *ep, struct sunxi_udc_request *req)
484 {
485 void *req_buf = req->req.buf;
486
487 /* if dma is not being used and buffer is aligned */
488 if (!is_sunxi_udc_dma_capable(req, ep))
489 return 0;
490
491 if (!((long)req_buf & 0x3))
492 return 0;
493
494 req->req.buf = kmalloc(req->req.length, GFP_ATOMIC);
495 if (!req->req.buf) {
496 req->req.buf = req_buf;
497 DMSG_PANIC("%s: unable to allocate memory for bounce buffer\n", __func__);
498 return -ENOMEM;
499 }
500
501 req->saved_req_buf = req_buf;
502
503 if (ep->bEndpointAddress & USB_DIR_IN)
504 memcpy(req->req.buf, req_buf, req->req.length);
505
506 return 0;
507 }
508
sunxi_udc_handle_unaligned_buf_complete(struct sunxi_udc_ep * ep,struct sunxi_udc_request * req)509 static void sunxi_udc_handle_unaligned_buf_complete(struct sunxi_udc_ep *ep, struct sunxi_udc_request *req)
510 {
511
512 /* if dma is not being used and buffer is aligned */
513 if (!req->saved_req_buf)
514 return;
515
516 if (!is_sunxi_udc_dma_capable(req, ep))
517 return;
518
519 /* Copy data from bounce buffer on successful out transfer */
520 if (!(ep->bEndpointAddress & USB_DIR_IN) && !req->req.status)
521 memcpy(req->saved_req_buf, req->req.buf,
522 req->req.actual);
523
524 /* Free bounce buffer */
525 kfree(req->req.buf);
526
527 req->req.buf = req->saved_req_buf;
528 req->saved_req_buf = NULL;
529 }
530
sunxi_udc_done(struct sunxi_udc_ep * ep,struct sunxi_udc_request * req,int status)531 static void sunxi_udc_done(struct sunxi_udc_ep *ep,
532 struct sunxi_udc_request *req, int status)
533 __releases(ep->dev->lock)
534 __acquires(ep->dev->lock)
535 {
536 unsigned halted = ep->halted;
537
538 if (g_queue_debug) {
539 DMSG_INFO("d: (%s, %p, %d, %d)\n\n\n", ep->ep.name,
540 &(req->req), req->req.length, req->req.actual);
541 }
542
543 list_del_init(&req->queue);
544
545 if (likely(req->req.status == -EINPROGRESS))
546 req->req.status = status;
547 else
548 status = req->req.status;
549
550 ep->halted = 1;
551 if (is_sunxi_udc_dma_capable(req, ep)) {
552 spin_unlock(&ep->dev->lock);
553 sunxi_udc_unmap_dma_buffer(req, ep->dev, ep);
554 sunxi_udc_handle_unaligned_buf_complete(ep, req);
555 req->req.complete(&ep->ep, &req->req);
556 spin_lock(&ep->dev->lock);
557 } else {
558 spin_unlock(&ep->dev->lock);
559 req->req.complete(&ep->ep, &req->req);
560 spin_lock(&ep->dev->lock);
561 }
562
563 ep->halted = halted;
564 }
565
sunxi_udc_nuke(struct sunxi_udc * udc,struct sunxi_udc_ep * ep,int status)566 static void sunxi_udc_nuke(struct sunxi_udc *udc,
567 struct sunxi_udc_ep *ep, int status)
568 {
569 /* Sanity check */
570 if (IS_ERR_OR_NULL(&ep->queue)) {
571 DMSG_PANIC("ERR: %s,ep->queue is NULL \n", __func__);
572 return;
573 }
574
575 while (!list_empty(&ep->queue)) {
576 struct sunxi_udc_request *req;
577
578 req = list_entry(ep->queue.next,
579 struct sunxi_udc_request, queue);
580 DMSG_INFO_UDC("nuke: ep num is %d\n", ep->num);
581 sunxi_udc_done(ep, req, status);
582 }
583 }
584
sunxi_udc_clear_ep_state(struct sunxi_udc * dev)585 static inline void sunxi_udc_clear_ep_state(struct sunxi_udc *dev)
586 {
587 unsigned i = 0;
588
589 /**
590 * hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint
591 * fifos, and pending transactions mustn't be continued in any case.
592 */
593 for (i = 1; i < SW_UDC_ENDPOINTS; i++)
594 sunxi_udc_nuke(dev, &dev->ep[i], -ECONNABORTED);
595 }
596
sunxi_udc_fifo_count_out(__hdle usb_bsp_hdle,__u8 ep_index)597 static inline int sunxi_udc_fifo_count_out(__hdle usb_bsp_hdle, __u8 ep_index)
598 {
599 if (ep_index) {
600 return USBC_ReadLenFromFifo(
601 g_sunxi_udc_io.usb_bsp_hdle,
602 USBC_EP_TYPE_RX);
603 } else {
604 return USBC_ReadLenFromFifo(
605 g_sunxi_udc_io.usb_bsp_hdle,
606 USBC_EP_TYPE_EP0);
607 }
608 }
609
sunxi_udc_write_packet(void __iomem * fifo,struct sunxi_udc_request * req,unsigned max)610 static inline int sunxi_udc_write_packet(void __iomem *fifo,
611 struct sunxi_udc_request *req,
612 unsigned max)
613 {
614 unsigned len = min(req->req.length - req->req.actual, max);
615 void *buf = req->req.buf + req->req.actual;
616
617 prefetch(buf);
618
619 DMSG_DBG_UDC("W: req.actual(%d), req.length(%d), len(%d), total(%d)\n",
620 req->req.actual, req->req.length, len, req->req.actual + len);
621
622 req->req.actual += len;
623
624 udelay(5);
625 USBC_WritePacket(g_sunxi_udc_io.usb_bsp_hdle, fifo, len, buf);
626
627 return len;
628 }
629
pio_write_fifo(struct sunxi_udc_ep * ep,struct sunxi_udc_request * req)630 static int pio_write_fifo(struct sunxi_udc_ep *ep,
631 struct sunxi_udc_request *req)
632 {
633 unsigned count = 0;
634 int is_last = 0;
635 u32 idx = 0;
636 void __iomem *fifo_reg = 0;
637 __s32 ret = 0;
638 u8 old_ep_index = 0;
639
640 idx = ep->bEndpointAddress & 0x7F;
641
642 /* write data */
643
644 /* select ep */
645 old_ep_index = USBC_GetActiveEp(g_sunxi_udc_io.usb_bsp_hdle);
646 USBC_SelectActiveEp(g_sunxi_udc_io.usb_bsp_hdle, idx);
647
648 /* select fifo */
649 fifo_reg = USBC_SelectFIFO(g_sunxi_udc_io.usb_bsp_hdle, idx);
650
651 count = sunxi_udc_write_packet(fifo_reg, req, ep->ep.maxpacket);
652
653 /* check if the last packet */
654
655 /* last packet is often short (sometimes a zlp) */
656 if (count != ep->ep.maxpacket)
657 is_last = 1;
658 else if (req->req.length != req->req.actual || req->req.zero)
659 is_last = 0;
660 else
661 is_last = 2;
662
663 if (g_write_debug) {
664 DMSG_INFO("pw: (0x%p, %d, %d)\n",
665 &(req->req), req->req.length, req->req.actual);
666 }
667
668 if (idx) { /* ep1~4 */
669 ret = USBC_Dev_WriteDataStatus(
670 g_sunxi_udc_io.usb_bsp_hdle,
671 USBC_EP_TYPE_TX, is_last);
672 if (ret != 0) {
673 DMSG_PANIC("ERR: USBC_Dev_WriteDataStatus, failed\n");
674 req->req.status = -EOVERFLOW;
675 }
676 } else { /* ep0 */
677 ret = USBC_Dev_WriteDataStatus(
678 g_sunxi_udc_io.usb_bsp_hdle,
679 USBC_EP_TYPE_EP0, is_last);
680 if (ret != 0) {
681 DMSG_PANIC("ERR: USBC_Dev_WriteDataStatus, failed\n");
682 req->req.status = -EOVERFLOW;
683 }
684 }
685
686 USBC_SelectActiveEp(g_sunxi_udc_io.usb_bsp_hdle, old_ep_index);
687
688 if (is_last) {
689 if (!idx) { /* ep0 */
690 ep->dev->ep0state = EP0_IDLE;
691 }
692
693 sunxi_udc_done(ep, req, 0);
694 is_last = 1;
695 }
696
697 return is_last;
698 }
699
dma_write_fifo(struct sunxi_udc_ep * ep,struct sunxi_udc_request * req)700 static int dma_write_fifo(struct sunxi_udc_ep *ep,
701 struct sunxi_udc_request *req)
702 {
703 u32 left_len = 0;
704 u32 idx = 0;
705 void __iomem *fifo_reg = 0;
706 u8 old_ep_index = 0;
707
708 idx = ep->bEndpointAddress & 0x7F;
709
710 /* select ep */
711 old_ep_index = USBC_GetActiveEp(g_sunxi_udc_io.usb_bsp_hdle);
712 USBC_SelectActiveEp(g_sunxi_udc_io.usb_bsp_hdle, idx);
713
714 /* select fifo */
715 fifo_reg = USBC_SelectFIFO(g_sunxi_udc_io.usb_bsp_hdle, idx);
716
717 /* auto_set, tx_mode, dma_tx_en, mode1 */
718 USBC_Dev_ConfigEpDma(
719 ep->dev->sunxi_udc_io->usb_bsp_hdle,
720 USBC_EP_TYPE_TX);
721
722 USBC_SelectActiveEp(g_sunxi_udc_io.usb_bsp_hdle, old_ep_index);
723
724 /* cut fragment part(??) */
725 left_len = req->req.length - req->req.actual;
726 left_len = left_len - (left_len % ep->ep.maxpacket);
727
728 ep->dma_working = 1;
729 dma_working = 1;
730 ep->dma_transfer_len = left_len;
731
732 spin_unlock(&ep->dev->lock);
733
734 sunxi_udc_dma_set_config(ep, req, (__u32)req->req.dma, left_len);
735 sunxi_udc_dma_start(ep, fifo_reg, (__u32)req->req.dma, left_len);
736 spin_lock(&ep->dev->lock);
737
738 return 0;
739 }
740
741 /* return: 0 = still running, 1 = completed, negative = errno */
sunxi_udc_write_fifo(struct sunxi_udc_ep * ep,struct sunxi_udc_request * req)742 static int sunxi_udc_write_fifo(struct sunxi_udc_ep *ep,
743 struct sunxi_udc_request *req)
744 {
745 if (ep->dma_working) {
746 if (g_dma_debug) {
747 struct sunxi_udc_request *req_next = NULL;
748
749 DMSG_PANIC("ERR: dma is busy, write fifo. ep(0x%p, %d), req(0x%p, 0x%p, 0x%p, %d, %d)\n\n",
750 ep, ep->num,
751 req, &(req->req),
752 req->req.buf,
753 req->req.length,
754 req->req.actual);
755
756 if (likely(!list_empty(&ep->queue)))
757 req_next = list_entry(ep->queue.next,
758 struct sunxi_udc_request,
759 queue);
760 else
761 req_next = NULL;
762
763 if (req_next) {
764 DMSG_PANIC("ERR: dma is busy, write fifo. req(0x%p, 0x%p, 0x%p, %d, %d)\n\n",
765 req_next,
766 &(req_next->req),
767 req_next->req.buf,
768 req_next->req.length,
769 req_next->req.actual);
770 }
771 }
772 return 0;
773 }
774
775 if (is_sunxi_udc_dma_capable(req, ep))
776 return dma_write_fifo(ep, req);
777 else
778 return pio_write_fifo(ep, req);
779 }
780
sunxi_udc_read_packet(void __iomem * fifo,void * buf,struct sunxi_udc_request * req,unsigned avail)781 static inline int sunxi_udc_read_packet(void __iomem *fifo,
782 void *buf, struct sunxi_udc_request *req, unsigned avail)
783 {
784 unsigned len = 0;
785
786 len = min(req->req.length - req->req.actual, avail);
787 req->req.actual += len;
788
789 DMSG_DBG_UDC("R: req.actual(%d), req.length(%d), len(%d), total(%d)\n",
790 req->req.actual, req->req.length, len, req->req.actual + len);
791
792 USBC_ReadPacket(g_sunxi_udc_io.usb_bsp_hdle, fifo, len, buf);
793
794 return len;
795 }
796
797 /* return: 0 = still running, 1 = completed, negative = errno */
pio_read_fifo(struct sunxi_udc_ep * ep,struct sunxi_udc_request * req)798 static int pio_read_fifo(struct sunxi_udc_ep *ep, struct sunxi_udc_request *req)
799 {
800 void *buf = NULL;
801 unsigned bufferspace = 0;
802 int is_last = 1;
803 unsigned avail = 0;
804 int fifo_count = 0;
805 u32 idx = 0;
806 void __iomem *fifo_reg = 0;
807 __s32 ret = 0;
808 u8 old_ep_index = 0;
809
810 idx = ep->bEndpointAddress & 0x7F;
811
812 /* select fifo */
813 fifo_reg = USBC_SelectFIFO(g_sunxi_udc_io.usb_bsp_hdle, idx);
814
815 if (!req->req.length) {
816 DMSG_PANIC("ERR: req->req.length == 0\n");
817 return 1;
818 }
819
820 buf = req->req.buf + req->req.actual;
821 bufferspace = req->req.length - req->req.actual;
822 if (!bufferspace) {
823 DMSG_PANIC("ERR: buffer full!\n");
824 return -1;
825 }
826
827 /* select ep */
828 old_ep_index = USBC_GetActiveEp(g_sunxi_udc_io.usb_bsp_hdle);
829 USBC_SelectActiveEp(g_sunxi_udc_io.usb_bsp_hdle, idx);
830
831 fifo_count = sunxi_udc_fifo_count_out(g_sunxi_udc_io.usb_bsp_hdle, idx);
832 if (fifo_count > ep->ep.maxpacket)
833 avail = ep->ep.maxpacket;
834 else
835 avail = fifo_count;
836
837 fifo_count = sunxi_udc_read_packet(fifo_reg, buf, req, avail);
838
839 /**
840 * checking this with ep0 is not accurate as we already
841 * read a control request
842 */
843 if (idx != 0 && fifo_count < ep->ep.maxpacket) {
844 is_last = 1;
845 /* overflowed this request? flush extra data */
846 if (fifo_count != avail)
847 req->req.status = -EOVERFLOW;
848 } else {
849 is_last = (req->req.length <= req->req.actual) ? 1 : 0;
850 }
851
852 if (g_read_debug) {
853 DMSG_INFO("pr: (0x%p, %d, %d)\n",
854 &(req->req), req->req.length, req->req.actual);
855 }
856
857 if (idx) {
858 ret = USBC_Dev_ReadDataStatus(
859 g_sunxi_udc_io.usb_bsp_hdle,
860 USBC_EP_TYPE_RX, is_last);
861 if (ret != 0) {
862 DMSG_PANIC("ERR: pio_read_fifo: ");
863 DMSG_PANIC("USBC_Dev_WriteDataStatus, failed\n");
864 req->req.status = -EOVERFLOW;
865 }
866 } else {
867 ret = USBC_Dev_ReadDataStatus(
868 g_sunxi_udc_io.usb_bsp_hdle,
869 USBC_EP_TYPE_EP0, is_last);
870 if (ret != 0) {
871 DMSG_PANIC("ERR: pio_read_fifo: ");
872 DMSG_PANIC("USBC_Dev_WriteDataStatus, failed\n");
873 req->req.status = -EOVERFLOW;
874 }
875 }
876
877 USBC_SelectActiveEp(g_sunxi_udc_io.usb_bsp_hdle, old_ep_index);
878
879 if (is_last) {
880 if (!idx)
881 ep->dev->ep0state = EP0_IDLE;
882
883 sunxi_udc_done(ep, req, 0);
884 is_last = 1;
885 }
886
887 return is_last;
888 }
889
dma_read_fifo(struct sunxi_udc_ep * ep,struct sunxi_udc_request * req)890 static int dma_read_fifo(struct sunxi_udc_ep *ep, struct sunxi_udc_request *req)
891 {
892 u32 left_len = 0;
893 u32 idx = 0;
894 void __iomem *fifo_reg = 0;
895 u8 old_ep_index = 0;
896
897 idx = ep->bEndpointAddress & 0x7F;
898
899 /* select ep */
900 old_ep_index = USBC_GetActiveEp(g_sunxi_udc_io.usb_bsp_hdle);
901 USBC_SelectActiveEp(g_sunxi_udc_io.usb_bsp_hdle, idx);
902
903 /* select fifo */
904 fifo_reg = USBC_SelectFIFO(g_sunxi_udc_io.usb_bsp_hdle, idx);
905
906 /* auto_set, tx_mode, dma_tx_en, mode1 */
907 USBC_Dev_ConfigEpDma(
908 ep->dev->sunxi_udc_io->usb_bsp_hdle, USBC_EP_TYPE_RX);
909
910 USBC_SelectActiveEp(g_sunxi_udc_io.usb_bsp_hdle, old_ep_index);
911
912 /* cut fragment packet part */
913 left_len = req->req.length - req->req.actual;
914 left_len = left_len - (left_len % ep->ep.maxpacket);
915
916 if (g_dma_debug) {
917 DMSG_INFO("dr: (0x%p, %d, %d)\n", &(req->req),
918 req->req.length, req->req.actual);
919 }
920
921 ep->dma_working = 1;
922 dma_working = 1;
923 ep->dma_transfer_len = left_len;
924
925 spin_unlock(&ep->dev->lock);
926
927 sunxi_udc_dma_set_config(ep, req, (__u32)req->req.dma, left_len);
928 sunxi_udc_dma_start(ep, fifo_reg, (__u32)req->req.dma, left_len);
929 spin_lock(&ep->dev->lock);
930
931 return 0;
932 }
933
934 /*
935 * If dma is working, RxPktRdy should be clear automatically.
936 * If not, we consider a short packet comes in and we will
937 * deal with it then.
938 *
939 * FIXME: The longest time to confirm is up to (5us * 1000).
940 */
941 #ifdef SW_UDC_DMA_INNER
sunxi_udc_confirm_rx_ready(void)942 static int sunxi_udc_confirm_rx_ready(void)
943 {
944 int i = 0;
945 int rx_ready_flag = 1;
946
947 for (i = 0; i < 1000; i++) {
948 if (!USBC_Dev_IsReadDataReady(g_sunxi_udc_io.usb_bsp_hdle, USBC_EP_TYPE_RX)) {
949 rx_ready_flag = 0;
950 break;
951 }
952 udelay(5);
953 }
954 DMSG_DBG_UDC("[confirm rx ready] rx_ready_flag = %d, i = %d\n",
955 rx_ready_flag, i);
956
957 return rx_ready_flag;
958 }
959
dma_got_short_pkt(struct sunxi_udc_ep * ep,struct sunxi_udc_request * req)960 static int dma_got_short_pkt(struct sunxi_udc_ep *ep, struct sunxi_udc_request *req)
961 {
962 dma_channel_t *pchan = NULL;
963 int dma_bc = 0;
964 int dma_r_bc = 0;
965 int fifo_count = 0;
966 // unsigned long flags = 0;
967 __s32 ret = 0;
968
969 pchan = (dma_channel_t *)ep->dma_hdle;
970 if (pchan == NULL) {
971 DMSG_DBG_UDC("[dma_got_short_pkt] dma_hdle is NULL!\n");
972 return 0;
973 }
974
975 if (!sunxi_udc_confirm_rx_ready())
976 return 0;
977
978 dma_bc = USBC_Readw(USBC_REG_DMA_BC(pchan->reg_base, pchan->channel_num));
979 dma_r_bc = USBC_Readw(USBC_REG_DMA_RESIDUAL_BC(pchan->reg_base, pchan->channel_num));
980 fifo_count = USBC_ReadLenFromFifo(g_sunxi_udc_io.usb_bsp_hdle, USBC_EP_TYPE_RX);
981
982 if (g_dma_debug) {
983 DMSG_INFO("read_fifo: dma_working... rx_cnt = %d, dma_channel = %d, dma_bc = %d, dma_r_bc = %d\n",
984 fifo_count, pchan->channel_num, dma_bc, dma_r_bc);
985 }
986
987 if (!fifo_count) {
988 ret = USBC_Dev_ReadDataStatus(
989 g_sunxi_udc_io.usb_bsp_hdle,
990 USBC_EP_TYPE_RX, 1);
991 if (ret != 0) {
992 DMSG_PANIC("USBC_Dev_WriteDataStatus, failed\n");
993 req->req.status = -EOVERFLOW;
994 return 0;
995 }
996
997 goto reassign;
998 }
999 /*
1000 * rx fifo got a short packet, reassign the transfer len
1001 */
1002 if (fifo_count > 0 && fifo_count < ep->ep.maxpacket) {
1003 reassign:
1004 req->req.length = dma_bc - dma_r_bc + fifo_count;
1005 ep->dma_transfer_len = dma_bc - dma_r_bc;
1006
1007 if (g_dma_debug) {
1008 DMSG_INFO("reassign: req.length = %d, req.actual = %d, ep->dma_transfer_len = %d\n",
1009 req->req.length, req->req.actual, ep->dma_transfer_len);
1010 }
1011 /*
1012 * we need to stop dma manually
1013 */
1014 sunxi_udc_dma_chan_disable((dm_hdl_t)ep->dma_hdle);
1015 sunxi_udc_dma_release((dm_hdl_t)ep->dma_hdle);
1016 ep->dma_hdle = NULL;
1017
1018 // spin_unlock_irqrestore(&ep->dev->lock, flags);
1019 spin_unlock_irq(&ep->dev->lock);
1020 sunxi_udc_dma_completion(ep->dev, ep, req);
1021 spin_lock_irq(&ep->dev->lock);
1022 // spin_lock_irqsave(&ep->dev->lock, flags);
1023
1024 return 1;
1025 }
1026
1027 return 0;
1028 }
1029 #endif
1030
1031 /* return: 0 = still running, 1 = completed, negative = errno */
sunxi_udc_read_fifo(struct sunxi_udc_ep * ep,struct sunxi_udc_request * req)1032 static int sunxi_udc_read_fifo(struct sunxi_udc_ep *ep,
1033 struct sunxi_udc_request *req)
1034 {
1035 int fifo_count = 0;
1036
1037 if (ep->dma_working) {
1038 #ifdef SW_UDC_DMA_INNER
1039 if (dma_got_short_pkt(ep, req))
1040 return 1;
1041 #endif
1042
1043 if (g_dma_debug) {
1044 struct sunxi_udc_request *req_next = NULL;
1045
1046 DMSG_PANIC("ERR: dma is busy, read fifo. ep(0x%p, %d), req(0x%p, 0x%p, 0x%p, %d, %d)\n\n",
1047 ep,
1048 ep->num,
1049 req,
1050 &(req->req),
1051 req->req.buf,
1052 req->req.length,
1053 req->req.actual);
1054
1055 if (likely(!list_empty(&ep->queue)))
1056 req_next = list_entry(ep->queue.next,
1057 struct sunxi_udc_request,
1058 queue);
1059 else
1060 req_next = NULL;
1061
1062 if (req_next) {
1063 DMSG_PANIC("ERR: dma is busy, read fifo. req(0x%p, 0x%p, 0x%p, %d, %d)\n\n",
1064 req_next,
1065 &(req_next->req),
1066 req_next->req.buf,
1067 req_next->req.length,
1068 req_next->req.actual);
1069 }
1070 }
1071 return 0;
1072 }
1073
1074 fifo_count = USBC_ReadLenFromFifo(g_sunxi_udc_io.usb_bsp_hdle, USBC_EP_TYPE_RX);
1075
1076 if ((is_sunxi_udc_dma_capable(req, ep)) && (fifo_count == ep->ep.maxpacket))
1077 return dma_read_fifo(ep, req);
1078 else
1079 return pio_read_fifo(ep, req);
1080 }
1081
sunxi_udc_read_fifo_crq(struct usb_ctrlrequest * crq)1082 static int sunxi_udc_read_fifo_crq(struct usb_ctrlrequest *crq)
1083 {
1084 u32 fifo_count = 0;
1085 u32 i = 0;
1086 void *pOut = crq;
1087 void __iomem *fifo = 0;
1088
1089 fifo = USBC_SelectFIFO(g_sunxi_udc_io.usb_bsp_hdle, 0);
1090 fifo_count = USBC_ReadLenFromFifo(
1091 g_sunxi_udc_io.usb_bsp_hdle,
1092 USBC_EP_TYPE_EP0);
1093
1094 if (fifo_count != 8) {
1095 i = 0;
1096
1097 while (i < 16 && (fifo_count != 8)) {
1098 fifo_count = USBC_ReadLenFromFifo(
1099 g_sunxi_udc_io.usb_bsp_hdle,
1100 USBC_EP_TYPE_EP0);
1101 i++;
1102 }
1103
1104 if (i >= 16)
1105 DMSG_PANIC("ERR: get ep0 fifo len failed\n");
1106 }
1107
1108 return USBC_ReadPacket(g_sunxi_udc_io.usb_bsp_hdle,
1109 fifo, fifo_count, pOut);
1110 }
1111
sunxi_udc_get_status(struct sunxi_udc * dev,struct usb_ctrlrequest * crq)1112 static int sunxi_udc_get_status(struct sunxi_udc *dev,
1113 struct usb_ctrlrequest *crq)
1114 {
1115 u16 status = 0;
1116 u8 buf[8];
1117 u8 ep_num = crq->wIndex & 0x7F;
1118 u8 is_in = crq->wIndex & USB_DIR_IN;
1119 void __iomem *fifo = 0;
1120 u8 old_ep_index = 0;
1121 int ret = 0;
1122
1123 switch (crq->bRequestType & USB_RECIP_MASK) {
1124 case USB_RECIP_INTERFACE:
1125 buf[0] = 0x00;
1126 buf[1] = 0x00;
1127 break;
1128
1129 case USB_RECIP_DEVICE:
1130 status = dev->devstatus;
1131 buf[0] = 0x01;
1132 buf[1] = 0x00;
1133 break;
1134
1135 case USB_RECIP_ENDPOINT:
1136 if (ep_num > 4 || crq->wLength > 2)
1137 return 1;
1138
1139 old_ep_index = USBC_GetActiveEp(g_sunxi_udc_io.usb_bsp_hdle);
1140 USBC_SelectActiveEp(g_sunxi_udc_io.usb_bsp_hdle, ep_num);
1141 if (ep_num == 0) {
1142 status = USBC_Dev_IsEpStall(
1143 g_sunxi_udc_io.usb_bsp_hdle,
1144 USBC_EP_TYPE_EP0);
1145 } else {
1146 if (is_in) {
1147 ret = readw(g_sunxi_udc_io.usb_vbase
1148 + USBC_REG_o_TXCSR);
1149 status = ret & (0x1 << USBC_BP_TXCSR_D_SEND_STALL);
1150 } else {
1151 ret = readw(g_sunxi_udc_io.usb_vbase
1152 + USBC_REG_o_RXCSR);
1153 status = ret & (0x1 << USBC_BP_RXCSR_D_SEND_STALL);
1154 }
1155 }
1156 status = status ? 1 : 0;
1157 if (status) {
1158 buf[0] = 0x01;
1159 buf[1] = 0x00;
1160 } else {
1161 buf[0] = 0x00;
1162 buf[1] = 0x00;
1163 }
1164 USBC_SelectActiveEp(g_sunxi_udc_io.usb_bsp_hdle, old_ep_index);
1165 break;
1166
1167 default:
1168 return 1;
1169 }
1170
1171 /* Seems to be needed to get it working. ouch :( */
1172 udelay(5);
1173 USBC_Dev_ReadDataStatus(
1174 g_sunxi_udc_io.usb_bsp_hdle,
1175 USBC_EP_TYPE_EP0, 0);
1176
1177 fifo = USBC_SelectFIFO(g_sunxi_udc_io.usb_bsp_hdle, 0);
1178 USBC_WritePacket(g_sunxi_udc_io.usb_bsp_hdle, fifo, crq->wLength, buf);
1179 USBC_Dev_WriteDataStatus(g_sunxi_udc_io.usb_bsp_hdle,
1180 USBC_EP_TYPE_EP0, 1);
1181
1182 return 0;
1183 }
1184
1185 static int sunxi_udc_set_halt(struct usb_ep *_ep, int value);
1186 static int sunxi_udc_set_halt_ex(struct usb_ep *_ep, int value, int is_in);
1187
sunxi_udc_handle_ep0_idle(struct sunxi_udc * dev,struct sunxi_udc_ep * ep,struct usb_ctrlrequest * crq,u32 ep0csr)1188 static void sunxi_udc_handle_ep0_idle(struct sunxi_udc *dev,
1189 struct sunxi_udc_ep *ep,
1190 struct usb_ctrlrequest *crq,
1191 u32 ep0csr)
1192 {
1193 int len = 0, ret = 0, tmp = 0;
1194 int is_in = 0;
1195
1196 /* start control request? */
1197 if (!USBC_Dev_IsReadDataReady(
1198 g_sunxi_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0)) {
1199 DMSG_WRN("ERR: data is ready, can not read data.\n");
1200 return;
1201 }
1202
1203 sunxi_udc_nuke(dev, ep, -EPROTO);
1204
1205 len = sunxi_udc_read_fifo_crq(crq);
1206 if (len != sizeof(*crq)) {
1207 USBC_Dev_ReadDataStatus(g_sunxi_udc_io.usb_bsp_hdle,
1208 USBC_EP_TYPE_EP0, 0);
1209 USBC_Dev_EpSendStall(g_sunxi_udc_io.usb_bsp_hdle,
1210 USBC_EP_TYPE_EP0);
1211
1212 return;
1213 }
1214
1215 DMSG_DBG_UDC("ep0: bRequest = %d bRequestType %d wLength = %d\n",
1216 crq->bRequest, crq->bRequestType, crq->wLength);
1217
1218 /* cope with automagic for some standard requests. */
1219 dev->req_std = ((crq->bRequestType & USB_TYPE_MASK)
1220 == USB_TYPE_STANDARD);
1221 dev->req_config = 0;
1222 dev->req_pending = 1;
1223
1224 if (dev->req_std) { /* standard request */
1225 switch (crq->bRequest) {
1226 case USB_REQ_SET_CONFIGURATION:
1227 DMSG_DBG_UDC("USB_REQ_SET_CONFIGURATION ...\n");
1228
1229 if (crq->bRequestType == USB_RECIP_DEVICE)
1230 dev->req_config = 1;
1231 break;
1232 case USB_REQ_SET_INTERFACE:
1233 DMSG_DBG_UDC("USB_REQ_SET_INTERFACE ...\n");
1234
1235 if (crq->bRequestType == USB_RECIP_INTERFACE)
1236 dev->req_config = 1;
1237 break;
1238 case USB_REQ_SET_ADDRESS:
1239 DMSG_DBG_UDC("USB_REQ_SET_ADDRESS ...\n");
1240
1241 if (crq->bRequestType == USB_RECIP_DEVICE) {
1242 tmp = crq->wValue & 0x7F;
1243 dev->address = tmp;
1244
1245 /* rx receive over, dataend, tx_pakect ready */
1246 USBC_Dev_ReadDataStatus(
1247 g_sunxi_udc_io.usb_bsp_hdle,
1248 USBC_EP_TYPE_EP0, 1);
1249
1250 dev->ep0state = EP0_END_XFER;
1251
1252 crq_bRequest = USB_REQ_SET_ADDRESS;
1253
1254 return;
1255 }
1256 break;
1257 case USB_REQ_GET_STATUS:
1258 DMSG_DBG_UDC("USB_REQ_GET_STATUS ...\n");
1259
1260 if (!sunxi_udc_get_status(dev, crq))
1261 return;
1262 break;
1263 case USB_REQ_CLEAR_FEATURE:
1264 /* --<1>--data direction must be host to device */
1265 if (x_test_bit(crq->bRequestType, 7)) {
1266 DMSG_PANIC("USB_REQ_CLEAR_FEATURE: ");
1267 DMSG_PANIC("data is not host to device\n");
1268 break;
1269 }
1270
1271 USBC_Dev_ReadDataStatus(
1272 g_sunxi_udc_io.usb_bsp_hdle,
1273 USBC_EP_TYPE_EP0, 1);
1274
1275 /* --<3>--data stage */
1276 if (crq->bRequestType == USB_RECIP_DEVICE) {
1277 /* wValue 0-1 */
1278 if (crq->wValue) {
1279 dev->devstatus &= ~(1 << USB_DEVICE_REMOTE_WAKEUP);
1280 } else {
1281 int k = 0;
1282
1283 for (k = 0; k < SW_UDC_ENDPOINTS; k++) {
1284 is_in = crq->wIndex & USB_DIR_IN;
1285 sunxi_udc_set_halt_ex(&dev->ep[k].ep, 0, is_in);
1286 }
1287 }
1288
1289 } else if (crq->bRequestType == USB_RECIP_INTERFACE) {
1290 /**
1291 * --<2>--token stage over
1292 * do nothing
1293 */
1294 } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
1295 /* --<3>--release the forbidden of ep */
1296 /* wValue 0-1 */
1297 if (crq->wValue) {
1298 dev->devstatus &= ~(1 << USB_DEVICE_REMOTE_WAKEUP);
1299 } else {
1300 int k = 0;
1301
1302 is_in = crq->wIndex & USB_DIR_IN;
1303 for (k = 0; k < SW_UDC_ENDPOINTS; k++) {
1304 if (dev->ep[k].bEndpointAddress == (crq->wIndex & 0xff))
1305 sunxi_udc_set_halt_ex(&dev->ep[k].ep, 0, is_in);
1306 }
1307 }
1308
1309 } else {
1310 DMSG_PANIC("PANIC : nonsupport set feature request. (%d)\n", crq->bRequestType);
1311 USBC_Dev_EpSendStall(
1312 g_sunxi_udc_io.usb_bsp_hdle,
1313 USBC_EP_TYPE_EP0);
1314 }
1315
1316 dev->ep0state = EP0_IDLE;
1317
1318 return;
1319
1320 case USB_REQ_SET_FEATURE:
1321 /* --<1>--data direction must be host to device */
1322 if (x_test_bit(crq->bRequestType, 7)) {
1323 DMSG_PANIC("USB_REQ_SET_FEATURE: data is not host to device\n");
1324 break;
1325 }
1326
1327 /* --<3>--data stage */
1328 if (crq->bRequestType == USB_RECIP_DEVICE) {
1329 if (crq->wValue == USB_DEVICE_TEST_MODE) {
1330 /* setup packet receive over */
1331 switch (crq->wIndex) {
1332 case SUNXI_UDC_TEST_J:
1333 USBC_Dev_ReadDataStatus(g_sunxi_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0, 1);
1334 dev->ep0state = EP0_END_XFER;
1335 crq_wIndex = TEST_J;
1336 crq_bRequest = USB_REQ_SET_FEATURE;
1337 return;
1338 case SUNXI_UDC_TEST_K:
1339 USBC_Dev_ReadDataStatus(g_sunxi_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0, 1);
1340 dev->ep0state = EP0_END_XFER;
1341 crq_wIndex = TEST_K;
1342 crq_bRequest = USB_REQ_SET_FEATURE;
1343 return;
1344 case SUNXI_UDC_TEST_SE0_NAK:
1345 USBC_Dev_ReadDataStatus(g_sunxi_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0, 1);
1346 dev->ep0state = EP0_END_XFER;
1347 crq_wIndex = TEST_SE0_NAK;
1348 crq_bRequest = USB_REQ_SET_FEATURE;
1349 return;
1350 case SUNXI_UDC_TEST_PACKET:
1351 USBC_Dev_ReadDataStatus(g_sunxi_udc_io.usb_bsp_hdle, USBC_EP_TYPE_EP0, 1);
1352 dev->ep0state = EP0_END_XFER;
1353 crq_wIndex = TEST_PACKET;
1354 crq_bRequest = USB_REQ_SET_FEATURE;
1355 return;
1356 default:
1357 break;
1358 }
1359 }
1360
1361 USBC_Dev_ReadDataStatus(
1362 g_sunxi_udc_io.usb_bsp_hdle,
1363 USBC_EP_TYPE_EP0, 1);
1364 dev->devstatus |= (1 << USB_DEVICE_REMOTE_WAKEUP);
1365 } else if (crq->bRequestType == USB_RECIP_INTERFACE) {
1366 /* --<2>--token stage over */
1367 USBC_Dev_ReadDataStatus(
1368 g_sunxi_udc_io.usb_bsp_hdle,
1369 USBC_EP_TYPE_EP0, 1);
1370 /* do nothing */
1371 } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
1372 /* --<3>--forbidden ep */
1373 int k = 0;
1374
1375 is_in = crq->wIndex & USB_DIR_IN;
1376 USBC_Dev_ReadDataStatus(
1377 g_sunxi_udc_io.usb_bsp_hdle,
1378 USBC_EP_TYPE_EP0, 1);
1379 for (k = 0; k < SW_UDC_ENDPOINTS; k++) {
1380 if (dev->ep[k].bEndpointAddress == (crq->wIndex & 0xff))
1381 sunxi_udc_set_halt_ex(&dev->ep[k].ep, 1, is_in);
1382 }
1383
1384 } else {
1385 DMSG_PANIC("PANIC : nonsupport set feature request. (%d)\n", crq->bRequestType);
1386
1387 USBC_Dev_ReadDataStatus(
1388 g_sunxi_udc_io.usb_bsp_hdle,
1389 USBC_EP_TYPE_EP0, 1);
1390 USBC_Dev_EpSendStall(
1391 g_sunxi_udc_io.usb_bsp_hdle,
1392 USBC_EP_TYPE_EP0);
1393 }
1394
1395 dev->ep0state = EP0_IDLE;
1396
1397 return;
1398
1399 default:
1400 /* only receive setup_data packet, cannot set DataEnd */
1401 USBC_Dev_ReadDataStatus(
1402 g_sunxi_udc_io.usb_bsp_hdle,
1403 USBC_EP_TYPE_EP0, 0);
1404 break;
1405 }
1406 } else {
1407 USBC_Dev_ReadDataStatus(
1408 g_sunxi_udc_io.usb_bsp_hdle,
1409 USBC_EP_TYPE_EP0, 0);
1410 #if IS_ENABLED(CONFIG_USB_G_WEBCAM) || IS_ENABLED(CONFIG_USB_CONFIGFS_F_UVC)
1411 /**
1412 * getinfo request about exposure time asolute,
1413 * iris absolute, brightness of webcam.
1414 */
1415 if (crq->bRequest == 0x86
1416 && crq->bRequestType == 0xa1
1417 && crq->wLength == 0x1
1418 && ((crq->wValue == 0x400 && crq->wIndex == 0x100)
1419 || (crq->wValue == 0x900 && crq->wIndex == 0x100)
1420 || (crq->wValue == 0x200 && crq->wIndex == 0x200))) {
1421 USBC_Dev_EpSendStall(g_sunxi_udc_io.usb_bsp_hdle,
1422 USBC_EP_TYPE_EP0);
1423 return;
1424 }
1425 #endif
1426 }
1427
1428 if (crq->bRequestType & USB_DIR_IN)
1429 dev->ep0state = EP0_IN_DATA_PHASE;
1430 else
1431 dev->ep0state = EP0_OUT_DATA_PHASE;
1432
1433 if (!dev->driver)
1434 return;
1435
1436 spin_unlock(&dev->lock);
1437 ret = dev->driver->setup(&dev->gadget, crq);
1438 spin_lock(&dev->lock);
1439 if (ret < 0) {
1440 if (dev->req_config) {
1441 DMSG_PANIC("ERR: config change %02x fail %d?\n",
1442 crq->bRequest, ret);
1443 return;
1444 }
1445
1446 if (ret == -EOPNOTSUPP)
1447 DMSG_PANIC("ERR: Operation not supported\n");
1448 else
1449 DMSG_PANIC("ERR: dev->driver->setup failed. (%d)\n",
1450 ret);
1451
1452 udelay(5);
1453
1454 USBC_Dev_ReadDataStatus(
1455 g_sunxi_udc_io.usb_bsp_hdle,
1456 USBC_EP_TYPE_EP0, 1);
1457 USBC_Dev_EpSendStall(
1458 g_sunxi_udc_io.usb_bsp_hdle,
1459 USBC_EP_TYPE_EP0);
1460
1461 dev->ep0state = EP0_IDLE;
1462 /* deferred i/o == no response yet */
1463 } else if (dev->req_pending) {
1464 dev->req_pending = 0;
1465 }
1466
1467 if (dev->req_std) {
1468 if (crq->bRequest == USB_REQ_SET_CONFIGURATION
1469 || crq->bRequest == USB_REQ_SET_INTERFACE) {
1470 /* rx_packet receive over */
1471 USBC_Dev_ReadDataStatus(
1472 g_sunxi_udc_io.usb_bsp_hdle,
1473 USBC_EP_TYPE_EP0, 1);
1474 }
1475 }
1476 }
1477
sunxi_udc_handle_ep0(struct sunxi_udc * dev)1478 static void sunxi_udc_handle_ep0(struct sunxi_udc *dev)
1479 {
1480 u32 ep0csr = 0;
1481 struct sunxi_udc_ep *ep = &dev->ep[0];
1482 struct sunxi_udc_request *req = NULL;
1483 struct usb_ctrlrequest crq;
1484
1485 DMSG_DBG_UDC("sunxi_udc_handle_ep0--1--\n");
1486
1487 if (list_empty(&ep->queue))
1488 req = NULL;
1489 else
1490 req = list_entry(ep->queue.next,
1491 struct sunxi_udc_request, queue);
1492
1493 DMSG_DBG_UDC("sunxi_udc_handle_ep0--2--\n");
1494
1495 /**
1496 * We make the assumption that sunxi_udc_UDC_IN_CSR1_REG equal to
1497 * sunxi_udc_UDC_EP0_CSR_REG when index is zero.
1498 */
1499 USBC_SelectActiveEp(g_sunxi_udc_io.usb_bsp_hdle, 0);
1500
1501 /* clear stall status */
1502 if (USBC_Dev_IsEpStall(g_sunxi_udc_io.usb_bsp_hdle,
1503 USBC_EP_TYPE_EP0)) {
1504 DMSG_PANIC("ERR: ep0 stall\n");
1505
1506 sunxi_udc_nuke(dev, ep, -EPIPE);
1507 USBC_Dev_EpClearStall(g_sunxi_udc_io.usb_bsp_hdle,
1508 USBC_EP_TYPE_EP0);
1509 dev->ep0state = EP0_IDLE;
1510 return;
1511 }
1512
1513 /* clear setup end */
1514 if (USBC_Dev_Ctrl_IsSetupEnd(g_sunxi_udc_io.usb_bsp_hdle)) {
1515 DMSG_PANIC("handle_ep0: ep0 setup end\n");
1516
1517 sunxi_udc_nuke(dev, ep, 0);
1518 USBC_Dev_Ctrl_ClearSetupEnd(g_sunxi_udc_io.usb_bsp_hdle);
1519 dev->ep0state = EP0_IDLE;
1520 }
1521
1522 DMSG_DBG_UDC("sunxi_udc_handle_ep0--3--%d\n", dev->ep0state);
1523
1524 ep0csr = USBC_Readw(USBC_REG_CSR0(g_sunxi_udc_io.usb_vbase));
1525
1526 switch (dev->ep0state) {
1527 case EP0_IDLE:
1528 sunxi_udc_handle_ep0_idle(dev, ep, &crq, ep0csr);
1529 break;
1530 case EP0_IN_DATA_PHASE: /* GET_DESCRIPTOR etc */
1531 DMSG_DBG_UDC("EP0_IN_DATA_PHASE ... what now?\n");
1532
1533 if (!USBC_Dev_IsWriteDataReady(
1534 g_sunxi_udc_io.usb_bsp_hdle,
1535 USBC_EP_TYPE_EP0)
1536 && req) {
1537 sunxi_udc_write_fifo(ep, req);
1538 }
1539 break;
1540 case EP0_OUT_DATA_PHASE: /* SET_DESCRIPTOR etc */
1541 DMSG_DBG_UDC("EP0_OUT_DATA_PHASE ... what now?\n");
1542
1543 if (USBC_Dev_IsReadDataReady(
1544 g_sunxi_udc_io.usb_bsp_hdle,
1545 USBC_EP_TYPE_EP0)
1546 && req) {
1547 sunxi_udc_read_fifo(ep, req);
1548 }
1549 break;
1550 case EP0_END_XFER:
1551 DMSG_DBG_UDC("EP0_END_XFER ... what now?\n");
1552 DMSG_DBG_UDC("crq_bRequest = 0x%x\n", crq_bRequest);
1553
1554 switch (crq_bRequest) {
1555 case USB_REQ_SET_ADDRESS:
1556 USBC_SelectActiveEp(g_sunxi_udc_io.usb_bsp_hdle, 0);
1557
1558 USBC_Dev_Ctrl_ClearSetupEnd(
1559 g_sunxi_udc_io.usb_bsp_hdle);
1560 USBC_Dev_SetAddress(
1561 g_sunxi_udc_io.usb_bsp_hdle,
1562 dev->address);
1563
1564 DMSG_INFO_UDC("Set address %d\n", dev->address);
1565 break;
1566 case USB_REQ_SET_FEATURE:
1567 switch (crq_wIndex) {
1568 case TEST_J:
1569 USBC_EnterMode_Test_J(
1570 g_sunxi_udc_io.usb_bsp_hdle);
1571 break;
1572
1573 case TEST_K:
1574 USBC_EnterMode_Test_K(
1575 g_sunxi_udc_io.usb_bsp_hdle);
1576 break;
1577
1578 case TEST_SE0_NAK:
1579 USBC_EnterMode_Test_SE0_NAK(
1580 g_sunxi_udc_io.usb_bsp_hdle);
1581 break;
1582
1583 case TEST_PACKET:
1584 {
1585 void __iomem *fifo = 0;
1586
1587 fifo = USBC_SelectFIFO(
1588 g_sunxi_udc_io.usb_bsp_hdle, 0);
1589 USBC_WritePacket(
1590 g_sunxi_udc_io.usb_bsp_hdle,
1591 fifo, 54, (u32 *)TestPkt);
1592 USBC_EnterMode_TestPacket(
1593 g_sunxi_udc_io.usb_bsp_hdle);
1594 USBC_Dev_WriteDataStatus(
1595 g_sunxi_udc_io.usb_bsp_hdle,
1596 USBC_EP_TYPE_EP0, 0);
1597 }
1598 break;
1599 default:
1600 break;
1601 }
1602
1603 crq_wIndex = 0;
1604 break;
1605 default:
1606 break;
1607 }
1608
1609 crq_bRequest = 0;
1610
1611 dev->ep0state = EP0_IDLE;
1612 break;
1613
1614 case EP0_STALL:
1615 DMSG_DBG_UDC("EP0_STALL ... what now?\n");
1616 dev->ep0state = EP0_IDLE;
1617 break;
1618 }
1619
1620 DMSG_DBG_UDC("sunxi_udc_handle_ep0--4--%d\n", dev->ep0state);
1621 }
1622
sunxi_udc_handle_ep(struct sunxi_udc_ep * ep)1623 static void sunxi_udc_handle_ep(struct sunxi_udc_ep *ep)
1624 {
1625 struct sunxi_udc_request *req = NULL;
1626 int is_in = ep->bEndpointAddress & USB_DIR_IN;
1627 u32 idx = 0;
1628 u8 old_ep_index = 0;
1629
1630 /* see sunxi_udc_queue. */
1631 if (likely(!list_empty(&ep->queue)))
1632 req = list_entry(ep->queue.next,
1633 struct sunxi_udc_request, queue);
1634 else
1635 req = NULL;
1636
1637 if (g_irq_debug) {
1638 DMSG_INFO("e: (%s), tx_csr=0x%x\n", ep->ep.name,
1639 USBC_Readw(USBC_REG_TXCSR(g_sunxi_udc_io.usb_vbase)));
1640 if (req) {
1641 DMSG_INFO("req: (0x%p, %d, %d)\n", &(req->req),
1642 req->req.length, req->req.actual);
1643 }
1644 }
1645
1646 idx = ep->bEndpointAddress & 0x7F;
1647
1648 old_ep_index = USBC_GetActiveEp(g_sunxi_udc_io.usb_bsp_hdle);
1649 USBC_SelectActiveEp(g_sunxi_udc_io.usb_bsp_hdle, idx);
1650
1651 if (is_in) {
1652 if (USBC_Dev_IsEpStall(g_sunxi_udc_io.usb_bsp_hdle,
1653 USBC_EP_TYPE_TX)) {
1654 DMSG_PANIC("ERR: tx ep(%d) is stall\n", idx);
1655 USBC_Dev_EpClearStall(
1656 g_sunxi_udc_io.usb_bsp_hdle,
1657 USBC_EP_TYPE_TX);
1658 goto end;
1659 }
1660 } else {
1661 if (USBC_Dev_IsEpStall(g_sunxi_udc_io.usb_bsp_hdle,
1662 USBC_EP_TYPE_RX)) {
1663 DMSG_PANIC("ERR: rx ep(%d) is stall\n", idx);
1664 USBC_Dev_EpClearStall(
1665 g_sunxi_udc_io.usb_bsp_hdle,
1666 USBC_EP_TYPE_RX);
1667 goto end;
1668 }
1669 }
1670
1671 if (req) {
1672 if (is_in) {
1673 if (!USBC_Dev_IsWriteDataReady(
1674 g_sunxi_udc_io.usb_bsp_hdle,
1675 USBC_EP_TYPE_TX)) {
1676 sunxi_udc_write_fifo(ep, req);
1677 }
1678 } else {
1679 if (USBC_Dev_IsReadDataReady(
1680 g_sunxi_udc_io.usb_bsp_hdle,
1681 USBC_EP_TYPE_RX)) {
1682 sunxi_udc_read_fifo(ep, req);
1683 }
1684 }
1685 }
1686
1687 end:
1688 USBC_SelectActiveEp(g_sunxi_udc_io.usb_bsp_hdle, old_ep_index);
1689 }
1690
1691 /* mask the useless irq, save disconect, reset, resume, suspend */
filtrate_irq_misc(u32 irq_misc)1692 static u32 filtrate_irq_misc(u32 irq_misc)
1693 {
1694 u32 irq = irq_misc;
1695
1696 irq &= ~(USBC_INTUSB_VBUS_ERROR
1697 | USBC_INTUSB_SESSION_REQ
1698 | USBC_INTUSB_CONNECT
1699 | USBC_INTUSB_SOF);
1700 USBC_INT_ClearMiscPending(g_sunxi_udc_io.usb_bsp_hdle,
1701 USBC_INTUSB_VBUS_ERROR);
1702 USBC_INT_ClearMiscPending(g_sunxi_udc_io.usb_bsp_hdle,
1703 USBC_INTUSB_SESSION_REQ);
1704 USBC_INT_ClearMiscPending(g_sunxi_udc_io.usb_bsp_hdle,
1705 USBC_INTUSB_CONNECT);
1706 USBC_INT_ClearMiscPending(g_sunxi_udc_io.usb_bsp_hdle,
1707 USBC_INTUSB_SOF);
1708
1709 return irq;
1710 }
1711
clear_all_irq(void)1712 static void clear_all_irq(void)
1713 {
1714 USBC_INT_ClearEpPendingAll(g_sunxi_udc_io.usb_bsp_hdle,
1715 USBC_EP_TYPE_TX);
1716 USBC_INT_ClearEpPendingAll(g_sunxi_udc_io.usb_bsp_hdle,
1717 USBC_EP_TYPE_RX);
1718 USBC_INT_ClearMiscPendingAll(g_sunxi_udc_io.usb_bsp_hdle);
1719 }
1720
throw_away_all_urb(struct sunxi_udc * dev)1721 static void throw_away_all_urb(struct sunxi_udc *dev)
1722 {
1723 int k = 0;
1724
1725 DMSG_INFO_UDC("irq: reset happen, throw away all urb\n");
1726 for (k = 0; k < SW_UDC_ENDPOINTS; k++)
1727 sunxi_udc_nuke(dev,
1728 (struct sunxi_udc_ep *)&(dev->ep[k]),
1729 -ECONNRESET);
1730 }
1731
1732 /* clear all dma status of the EP, called when dma exception */
sunxi_udc_clean_dma_status(struct sunxi_udc_ep * ep)1733 static void sunxi_udc_clean_dma_status(struct sunxi_udc_ep *ep)
1734 {
1735 u8 ep_index = 0;
1736 u8 old_ep_index = 0;
1737 //struct sunxi_udc_request *req = NULL;
1738
1739 ep_index = ep->bEndpointAddress & 0x7F;
1740
1741 old_ep_index = USBC_GetActiveEp(g_sunxi_udc_io.usb_bsp_hdle);
1742 USBC_SelectActiveEp(g_sunxi_udc_io.usb_bsp_hdle, ep_index);
1743
1744 if ((ep->bEndpointAddress) & USB_DIR_IN) { /* dma_mode1 */
1745 /* clear ep dma status */
1746 USBC_Dev_ClearEpDma(g_sunxi_udc_io.usb_bsp_hdle,
1747 USBC_EP_TYPE_TX);
1748
1749 /* select bus to pio */
1750 sunxi_udc_switch_bus_to_pio(ep, 1);
1751 } else { /* dma_mode0 */
1752 /* clear ep dma status */
1753 USBC_Dev_ClearEpDma(g_sunxi_udc_io.usb_bsp_hdle,
1754 USBC_EP_TYPE_RX);
1755
1756 /* select bus to pio */
1757 sunxi_udc_switch_bus_to_pio(ep, 0);
1758 }
1759
1760 USBC_SelectActiveEp(g_sunxi_udc_io.usb_bsp_hdle, old_ep_index);
1761
1762 ep->dma_working = 0;
1763 dma_working = 0;
1764 }
1765
sunxi_udc_stop_dma_work(struct sunxi_udc * dev,u32 unlock)1766 static void sunxi_udc_stop_dma_work(struct sunxi_udc *dev, u32 unlock)
1767 {
1768 __u32 i = 0;
1769 struct sunxi_udc_ep *ep = NULL;
1770
1771 for (i = 0; i < SW_UDC_ENDPOINTS; i++) {
1772 ep = &dev->ep[i];
1773
1774 if (sunxi_udc_dma_is_busy(ep)) {
1775 DMSG_PANIC("wrn: ep(%d) must stop working\n", i);
1776
1777 if (unlock) {
1778 spin_unlock(&ep->dev->lock);
1779 sunxi_udc_dma_stop(ep);
1780 spin_lock(&ep->dev->lock);
1781 } else {
1782 sunxi_udc_dma_stop(ep);
1783 }
1784
1785 #ifdef SW_UDC_DMA_INNER
1786 ep->dma_hdle = NULL;
1787 #else
1788 ep->sunxi_udc_dma[ep->num].is_start = 0;
1789 #endif
1790 ep->dma_transfer_len = 0;
1791
1792 sunxi_udc_clean_dma_status(ep);
1793 }
1794 }
1795 }
1796
sunxi_udc_dma_completion(struct sunxi_udc * dev,struct sunxi_udc_ep * ep,struct sunxi_udc_request * req)1797 void sunxi_udc_dma_completion(struct sunxi_udc *dev,
1798 struct sunxi_udc_ep *ep,
1799 struct sunxi_udc_request *req)
1800 {
1801 unsigned long flags = 0;
1802 __u8 old_ep_index = 0;
1803 __u32 dma_transmit_len = 0;
1804 int is_complete = 0;
1805 struct sunxi_udc_request *req_next = NULL;
1806
1807 if (dev == NULL || ep == NULL || req == NULL) {
1808 DMSG_PANIC("ERR: argment invaild. (0x%p, 0x%p, 0x%p)\n",
1809 dev, ep, req);
1810 return;
1811 }
1812
1813 if (!ep->dma_working) {
1814 DMSG_PANIC("ERR: dma is not work, can not callback\n");
1815 return;
1816 }
1817
1818 sunxi_udc_unmap_dma_buffer(req, dev, ep);
1819
1820 spin_lock_irqsave(&dev->lock, flags);
1821
1822 old_ep_index = USBC_GetActiveEp(dev->sunxi_udc_io->usb_bsp_hdle);
1823 USBC_SelectActiveEp(dev->sunxi_udc_io->usb_bsp_hdle, ep->num);
1824
1825 if ((ep->bEndpointAddress) & USB_DIR_IN) { /* tx, dma_mode1 */
1826 while (USBC_Dev_IsWriteDataReady_FifoEmpty(
1827 dev->sunxi_udc_io->usb_bsp_hdle,
1828 USBC_EP_TYPE_TX))
1829 ;
1830 USBC_Dev_ClearEpDma(dev->sunxi_udc_io->usb_bsp_hdle,
1831 USBC_EP_TYPE_TX);
1832 } else { /* rx, dma_mode0 */
1833 USBC_Dev_ClearEpDma(dev->sunxi_udc_io->usb_bsp_hdle,
1834 USBC_EP_TYPE_RX);
1835 }
1836
1837 dma_transmit_len = sunxi_udc_dma_transmit_length(ep);
1838 if (dma_transmit_len < req->req.length) {
1839 if ((ep->bEndpointAddress) & USB_DIR_IN)
1840 USBC_Dev_ClearEpDma(dev->sunxi_udc_io->usb_bsp_hdle,
1841 USBC_EP_TYPE_TX);
1842 else
1843 USBC_Dev_ClearEpDma(dev->sunxi_udc_io->usb_bsp_hdle,
1844 USBC_EP_TYPE_RX);
1845 }
1846
1847 ep->dma_working = 0;
1848 dma_working = 0;
1849 ep->dma_transfer_len = 0;
1850
1851 /* if current data transfer not complete, then go on */
1852 req->req.actual += dma_transmit_len;
1853
1854 if (g_dma_debug) {
1855 DMSG_INFO("di: (0x%p, %d, %d),(%d,%d)\n",
1856 &(req->req), req->req.length, req->req.actual,
1857 ep->bEndpointAddress, USB_DIR_IN);
1858 }
1859
1860 if (req->req.length > req->req.actual) {
1861 if (((ep->bEndpointAddress & USB_DIR_IN) != 0)
1862 && !USBC_Dev_IsWriteDataReady_FifoEmpty(
1863 dev->sunxi_udc_io->usb_bsp_hdle,
1864 USBC_EP_TYPE_TX)) {
1865 if (pio_write_fifo(ep, req)) {
1866 req = NULL;
1867 is_complete = 1;
1868 }
1869 } else if (((ep->bEndpointAddress & USB_DIR_IN) == 0)
1870 && USBC_Dev_IsReadDataReady(
1871 dev->sunxi_udc_io->usb_bsp_hdle,
1872 USBC_EP_TYPE_RX)) {
1873 if (pio_read_fifo(ep, req)) {
1874 req = NULL;
1875 is_complete = 1;
1876 }
1877 }
1878 } else { /* if DMA transfer data over, then done */
1879 /*tx need zero packet in sometime*/
1880 if ((ep->bEndpointAddress & USB_DIR_IN) != 0 && req->req.zero)
1881 pio_write_fifo(ep, req);
1882 else
1883 sunxi_udc_done(ep, req, 0);
1884 is_complete = 1;
1885 }
1886
1887 /* start next transfer */
1888 if (is_complete) {
1889 if (likely(!list_empty(&ep->queue)))
1890 req_next = list_entry(ep->queue.next,
1891 struct sunxi_udc_request, queue);
1892 else
1893 req_next = NULL;
1894
1895 if (req_next) {
1896 if ((ep->bEndpointAddress & USB_DIR_IN) != 0) {
1897 while (USBC_Dev_IsWriteDataReady_FifoEmpty(
1898 dev->sunxi_udc_io->usb_bsp_hdle,
1899 USBC_EP_TYPE_TX))
1900 ;
1901 sunxi_udc_write_fifo(ep, req_next);
1902 } else if (((ep->bEndpointAddress & USB_DIR_IN) == 0)
1903 && USBC_Dev_IsReadDataReady(
1904 dev->sunxi_udc_io->usb_bsp_hdle,
1905 USBC_EP_TYPE_RX)) {
1906
1907 sunxi_udc_read_fifo(ep, req_next);
1908 }
1909 }
1910 }
1911
1912 USBC_SelectActiveEp(dev->sunxi_udc_io->usb_bsp_hdle, old_ep_index);
1913
1914 spin_unlock_irqrestore(&dev->lock, flags);
1915 }
1916
sunxi_udc_irq(int dummy,void * _dev)1917 static irqreturn_t sunxi_udc_irq(int dummy, void *_dev)
1918 {
1919 struct sunxi_udc *dev = _dev;
1920 int usb_irq = 0;
1921 int tx_irq = 0;
1922 int rx_irq = 0;
1923 int i = 0;
1924 int dma_irq = 0;
1925 u32 old_ep_idx = 0;
1926 unsigned long flags = 0;
1927
1928 spin_lock_irqsave(&dev->lock, flags);
1929
1930 /* Driver connected ? */
1931 if (!dev->driver || !is_peripheral_active()) {
1932 DMSG_PANIC("ERR: functoin driver is not exist, ");
1933 DMSG_PANIC("or udc is not active.\n");
1934
1935 /* Clear interrupts */
1936 clear_all_irq();
1937
1938 spin_unlock_irqrestore(&dev->lock, flags);
1939
1940 return IRQ_NONE;
1941 }
1942
1943 /* Save index */
1944 old_ep_idx = USBC_GetActiveEp(g_sunxi_udc_io.usb_bsp_hdle);
1945
1946 /* Read status registers */
1947 usb_irq = USBC_INT_MiscPending(g_sunxi_udc_io.usb_bsp_hdle);
1948 tx_irq = USBC_INT_EpPending(g_sunxi_udc_io.usb_bsp_hdle,
1949 USBC_EP_TYPE_TX);
1950 rx_irq = USBC_INT_EpPending(g_sunxi_udc_io.usb_bsp_hdle,
1951 USBC_EP_TYPE_RX);
1952 dma_irq = USBC_Readw(USBC_REG_DMA_INTS(dev->sunxi_udc_io->usb_vbase));
1953
1954 usb_irq = filtrate_irq_misc(usb_irq);
1955
1956 if (g_irq_debug) {
1957 DMSG_INFO("\nirq: %02x,tx_irq=%02x,rx_irq=%02x, dma_irq:%x\n",
1958 usb_irq, tx_irq, rx_irq, dma_irq);
1959 }
1960
1961 /**
1962 * Now, handle interrupts. There's two types :
1963 * - Reset, Resume, Suspend coming -> usb_int_reg
1964 * - EP -> ep_int_reg
1965 */
1966
1967 /* RESET */
1968 if (usb_irq & USBC_INTUSB_RESET) {
1969 DMSG_INFO_UDC("IRQ: reset\n");
1970
1971 USBC_INT_ClearMiscPending(g_sunxi_udc_io.usb_bsp_hdle,
1972 USBC_INTUSB_RESET);
1973
1974 clear_all_irq();
1975
1976 usb_connect = 1;
1977
1978 if (!charger_mode) {
1979 pr_debug("usb_connecting: hold wake lock.\n");
1980 __pm_stay_awake(dev->ws);
1981 }
1982
1983 USBC_SelectActiveEp(g_sunxi_udc_io.usb_bsp_hdle, 0);
1984 USBC_Dev_SetAddress_default(g_sunxi_udc_io.usb_bsp_hdle);
1985
1986 if (is_udc_support_dma())
1987 sunxi_udc_stop_dma_work(dev, 1);
1988
1989 throw_away_all_urb(dev);
1990
1991 dev->address = 0;
1992 dev->ep0state = EP0_IDLE;
1993 dev->gadget.speed = USB_SPEED_UNKNOWN;
1994 g_irq_debug = 0;
1995 g_queue_debug = 0;
1996 g_dma_debug = 0;
1997
1998 spin_unlock_irqrestore(&dev->lock, flags);
1999
2000 #if !defined(SUNXI_USB_FPGA) && defined(CONFIG_POWER_SUPPLY)
2001 schedule_work(&dev->set_cur_vol_work);
2002 #endif
2003
2004 return IRQ_HANDLED;
2005 }
2006
2007 /* RESUME */
2008 if (usb_irq & USBC_INTUSB_RESUME) {
2009 DMSG_INFO_UDC("IRQ: resume\n");
2010
2011 /* clear interrupt */
2012 USBC_INT_ClearMiscPending(g_sunxi_udc_io.usb_bsp_hdle,
2013 USBC_INTUSB_RESUME);
2014
2015 if (dev->gadget.speed != USB_SPEED_UNKNOWN
2016 && dev->driver
2017 && dev->driver->resume) {
2018 spin_unlock(&dev->lock);
2019 dev->driver->resume(&dev->gadget);
2020 spin_lock(&dev->lock);
2021 usb_connect = 1;
2022 }
2023 }
2024
2025 /* SUSPEND */
2026 if (usb_irq & USBC_INTUSB_SUSPEND) {
2027 DMSG_INFO_UDC("IRQ: suspend\n");
2028
2029 /* clear interrupt */
2030 USBC_INT_ClearMiscPending(g_sunxi_udc_io.usb_bsp_hdle,
2031 USBC_INTUSB_SUSPEND);
2032
2033 if (dev->gadget.speed != USB_SPEED_UNKNOWN) {
2034 spin_unlock_irqrestore(&dev->lock, flags);
2035 schedule_work(&dev->vbus_det_work);
2036 spin_lock_irqsave(&dev->lock, flags);
2037 usb_connect = 0;
2038 if (!charger_mode) {
2039 __pm_relax(dev->ws);
2040 pr_debug("usb_connecting: release wake lock\n");
2041 }
2042
2043 } else {
2044 DMSG_INFO_UDC("ERR: usb speed is unknown\n");
2045 }
2046
2047 if (dev->gadget.speed != USB_SPEED_UNKNOWN
2048 && dev->driver
2049 && dev->driver->suspend) {
2050 spin_unlock(&dev->lock);
2051 dev->driver->suspend(&dev->gadget);
2052 spin_lock(&dev->lock);
2053 }
2054
2055 dev->ep0state = EP0_IDLE;
2056 }
2057
2058 /* DISCONNECT */
2059 if (usb_irq & USBC_INTUSB_DISCONNECT) {
2060 DMSG_INFO_UDC("IRQ: disconnect\n");
2061
2062 USBC_INT_ClearMiscPending(g_sunxi_udc_io.usb_bsp_hdle,
2063 USBC_INTUSB_DISCONNECT);
2064
2065 dev->ep0state = EP0_IDLE;
2066
2067 usb_connect = 0;
2068 }
2069
2070 /**
2071 * EP
2072 * control traffic
2073 * check on ep0csr != 0 is not a good idea as clearing in_pkt_ready
2074 * generate an interrupt
2075 */
2076 if (tx_irq & USBC_INTTx_FLAG_EP0) {
2077 DMSG_DBG_UDC("USB ep0 irq\n");
2078
2079 /* Clear the interrupt bit by setting it to 1 */
2080 USBC_INT_ClearEpPending(g_sunxi_udc_io.usb_bsp_hdle,
2081 USBC_EP_TYPE_TX, 0);
2082
2083 if (dev->gadget.speed == USB_SPEED_UNKNOWN) {
2084 if (USBC_Dev_QueryTransferMode(g_sunxi_udc_io.usb_bsp_hdle)
2085 == USBC_TS_MODE_HS) {
2086 dev->gadget.speed = USB_SPEED_HIGH;
2087
2088 DMSG_INFO_UDC("\n++++++++++++++++++++\n");
2089 DMSG_INFO_UDC(" usb enter high speed.\n");
2090 DMSG_INFO_UDC("\n++++++++++++++++++++\n");
2091 } else {
2092 dev->gadget.speed = USB_SPEED_FULL;
2093
2094 DMSG_INFO_UDC("\n++++++++++++++++++++\n");
2095 DMSG_INFO_UDC(" usb enter full speed.\n");
2096 DMSG_INFO_UDC("\n++++++++++++++++++++\n");
2097 }
2098 }
2099
2100 sunxi_udc_handle_ep0(dev);
2101 }
2102
2103 #ifdef SW_UDC_DMA_INNER
2104 if (is_udc_support_dma()) {
2105 struct sunxi_udc_request *req = NULL;
2106 struct sunxi_udc_ep *ep = NULL;
2107 int i = 0;
2108
2109 /* tx endpoint data transfers */
2110 for (i = 0; i < DMA_CHAN_TOTAL; i++) {
2111 u32 tmp = 1 << i;
2112
2113 if (dma_irq & tmp) {
2114 DMSG_DBG_UDC("USB dma chanle%d irq\n", i);
2115
2116 /* set 1 to clear pending */
2117 writel(BIT(i),
2118 USBC_REG_DMA_INTS(dev->sunxi_udc_io->usb_vbase));
2119
2120 ep = &dev->ep[dma_chnl[i].ep_num];
2121
2122 if (ep) {
2123 /* find req */
2124 sunxi_udc_dma_release((dm_hdl_t)ep->dma_hdle);
2125 ep->dma_hdle = NULL;
2126 if (likely(!list_empty(&ep->queue)))
2127 req = list_entry(ep->queue.next, struct sunxi_udc_request, queue);
2128 else
2129 req = NULL;
2130
2131 /* call back */
2132 if (req) {
2133 spin_unlock_irqrestore(&dev->lock, flags);
2134 sunxi_udc_dma_completion(dev, ep, req);
2135 spin_lock_irqsave(&dev->lock, flags);
2136 }
2137 } else {
2138 DMSG_PANIC("ERR: sunxi_udc_dma_callback: dma is remove, but dma irq is happened\n");
2139 }
2140 }
2141 }
2142 }
2143 #endif
2144
2145 /* rx endpoint data transfers */
2146 for (i = 1; i <= SW_UDC_EPNUMS; i++) {
2147 u32 tmp = 1 << i;
2148
2149 if (rx_irq & tmp) {
2150 DMSG_DBG_UDC("USB rx ep%d irq\n", i);
2151
2152 /* Clear the interrupt bit by setting it to 1 */
2153 USBC_INT_ClearEpPending(g_sunxi_udc_io.usb_bsp_hdle,
2154 USBC_EP_TYPE_RX, i);
2155
2156 sunxi_udc_handle_ep(&dev->ep[ep_fifo_out[i]]);
2157 }
2158 }
2159
2160 /* tx endpoint data transfers */
2161 for (i = 1; i <= SW_UDC_EPNUMS; i++) {
2162 u32 tmp = 1 << i;
2163
2164 if (tx_irq & tmp) {
2165 DMSG_DBG_UDC("USB tx ep%d irq\n", i);
2166
2167 /* Clear the interrupt bit by setting it to 1 */
2168 USBC_INT_ClearEpPending(g_sunxi_udc_io.usb_bsp_hdle,
2169 USBC_EP_TYPE_TX, i);
2170
2171 sunxi_udc_handle_ep(&dev->ep[ep_fifo_in[i]]);
2172 }
2173 }
2174
2175 /* Restore old index */
2176 USBC_SelectActiveEp(g_sunxi_udc_io.usb_bsp_hdle, old_ep_idx);
2177
2178 spin_unlock_irqrestore(&dev->lock, flags);
2179 return IRQ_HANDLED;
2180 }
2181
2182 /* sunxi_udc_ep_ops */
to_sunxi_udc_ep(struct usb_ep * ep)2183 static inline struct sunxi_udc_ep *to_sunxi_udc_ep(struct usb_ep *ep)
2184 {
2185 return container_of(ep, struct sunxi_udc_ep, ep);
2186 }
2187
to_sunxi_udc(struct usb_gadget * gadget)2188 static inline struct sunxi_udc *to_sunxi_udc(struct usb_gadget *gadget)
2189 {
2190 return container_of(gadget, struct sunxi_udc, gadget);
2191 }
2192
to_sunxi_udc_req(struct usb_request * req)2193 static inline struct sunxi_udc_request *to_sunxi_udc_req(struct usb_request *req)
2194 {
2195 return container_of(req, struct sunxi_udc_request, req);
2196 }
2197
sunxi_udc_ep_config_reset(struct sunxi_udc_ep * ep)2198 static void sunxi_udc_ep_config_reset(struct sunxi_udc_ep *ep)
2199 {
2200 if (ep->bmAttributes == USB_ENDPOINT_XFER_CONTROL)
2201 ep->ep.maxpacket = EP0_FIFO_SIZE;
2202 else if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2203 ep->ep.maxpacket = SW_UDC_EP_ISO_FIFO_SIZE;
2204 else if (ep->bmAttributes == USB_ENDPOINT_XFER_BULK)
2205 ep->ep.maxpacket = SW_UDC_EP_FIFO_SIZE;
2206 else if (ep->bmAttributes == USB_ENDPOINT_XFER_INT)
2207 ep->ep.maxpacket = SW_UDC_EP_FIFO_SIZE;
2208 else
2209 DMSG_PANIC("[ep_disable] ep type is invalid!\n");
2210 }
2211
sunxi_udc_ep_enable(struct usb_ep * _ep,const struct usb_endpoint_descriptor * desc)2212 static int sunxi_udc_ep_enable(struct usb_ep *_ep,
2213 const struct usb_endpoint_descriptor *desc)
2214 {
2215 struct sunxi_udc *dev = NULL;
2216 struct sunxi_udc_ep *ep = NULL;
2217 u32 max = 0;
2218 u32 old_ep_index = 0;
2219 __u32 fifo_addr = 0;
2220 unsigned long flags = 0;
2221 u32 ep_type = 0;
2222 u32 ts_type = 0;
2223 u32 fifo_size = 0;
2224 u8 double_fifo = 0;
2225 int i = 0;
2226
2227 if (_ep == NULL || desc == NULL) {
2228 DMSG_PANIC("ERR: invalid argment\n");
2229 return -EINVAL;
2230 }
2231
2232 if (_ep->name == ep0name || desc->bDescriptorType != USB_DT_ENDPOINT) {
2233 DMSG_PANIC("PANIC : _ep->name(%s) == ep0name || desc->bDescriptorType(%d) != USB_DT_ENDPOINT\n",
2234 _ep->name, desc->bDescriptorType);
2235 return -EINVAL;
2236 }
2237
2238 ep = to_sunxi_udc_ep(_ep);
2239 if (ep == NULL) {
2240 DMSG_PANIC("ERR: usbd_ep_enable, ep = NULL\n");
2241 return -EINVAL;
2242 }
2243
2244 if (ep->desc) {
2245 DMSG_PANIC("ERR: usbd_ep_enable, ep->desc is not NULL, ep%d(%s)\n",
2246 ep->num, _ep->name);
2247 return -EINVAL;
2248 }
2249
2250 DMSG_INFO_UDC("ep enable: ep%d(0x%p, %s, %d, %d)\n",
2251 ep->num, _ep, _ep->name,
2252 (desc->bEndpointAddress & USB_DIR_IN), _ep->maxpacket);
2253
2254 dev = ep->dev;
2255 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
2256 DMSG_PANIC("PANIC : dev->driver = 0x%p ?= NULL dev->gadget->speed =%d ?= USB_SPEED_UNKNOWN\n",
2257 dev->driver, dev->gadget.speed);
2258 return -ESHUTDOWN;
2259 }
2260
2261 max = le16_to_cpu(desc->wMaxPacketSize) & 0x1fff;
2262
2263 spin_lock_irqsave(&ep->dev->lock, flags);
2264
2265 _ep->maxpacket = max & 0x7ff;
2266 ep->desc = desc;
2267 ep->halted = 0;
2268 ep->bEndpointAddress = desc->bEndpointAddress;
2269
2270 /* ep_type */
2271 if ((ep->bEndpointAddress) & USB_DIR_IN) { /* tx */
2272 ep_type = USBC_EP_TYPE_TX;
2273 } else { /* rx */
2274 ep_type = USBC_EP_TYPE_RX;
2275 }
2276
2277 /* ts_type */
2278 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
2279 case USB_ENDPOINT_XFER_CONTROL:
2280 ts_type = USBC_TS_TYPE_CTRL;
2281 break;
2282 case USB_ENDPOINT_XFER_BULK:
2283 ts_type = USBC_TS_TYPE_BULK;
2284 break;
2285 case USB_ENDPOINT_XFER_ISOC:
2286 ts_type = USBC_TS_TYPE_ISO;
2287 break;
2288 case USB_ENDPOINT_XFER_INT:
2289 ts_type = USBC_TS_TYPE_INT;
2290 break;
2291 default:
2292 DMSG_PANIC("err: usbd_ep_enable, unknown ep type(%d)\n",
2293 (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK));
2294 goto end;
2295 }
2296
2297 /* fifo_addr && fifo_size && double fifo */
2298 for (i = 0; i < SW_UDC_ENDPOINTS; i++) {
2299 if (!strcmp(_ep->name, ep_fifo[i].name)) {
2300 fifo_addr = ep_fifo[i].fifo_addr;
2301 fifo_size = ep_fifo[i].fifo_size;
2302 double_fifo = ep_fifo[i].double_fifo;
2303 break;
2304 }
2305 }
2306
2307 DMSG_INFO_UDC("ep enable: ep%d(0x%p, %s, %d, %d), fifo(%d, %d, %d)\n",
2308 ep->num,
2309 _ep,
2310 _ep->name,
2311 (desc->bEndpointAddress & USB_DIR_IN),
2312 _ep->maxpacket,
2313 fifo_addr,
2314 fifo_size,
2315 double_fifo);
2316
2317 if (i >= SW_UDC_ENDPOINTS) {
2318 DMSG_PANIC("err: usbd_ep_enable, config fifo failed\n");
2319 goto end;
2320 }
2321
2322 /* check fifo size */
2323 if ((_ep->maxpacket & 0x7ff) > fifo_size) {
2324 DMSG_PANIC("err: usbd_ep_enable, fifo size is too small\n");
2325 goto end;
2326 }
2327
2328 /* check double fifo */
2329 if (double_fifo) {
2330 if (((_ep->maxpacket & 0x7ff) * 2) > fifo_size) {
2331 DMSG_PANIC("err: usbd_ep_enable, it is double fifo, ");
2332 DMSG_PANIC("but fifo size is too small\n");
2333 goto end;
2334 }
2335
2336 /* ????FIFO, ????????????? */
2337 fifo_size = _ep->maxpacket & 0x7ff;
2338 }
2339
2340 if (!is_peripheral_active()) {
2341 DMSG_INFO_UDC("usbd_ep_enable, usb device is not active\n");
2342 goto end;
2343 }
2344
2345 old_ep_index = USBC_GetActiveEp(g_sunxi_udc_io.usb_bsp_hdle);
2346 USBC_SelectActiveEp(g_sunxi_udc_io.usb_bsp_hdle, ep->num);
2347
2348 USBC_Dev_ConfigEp_Default(g_sunxi_udc_io.usb_bsp_hdle, ep_type);
2349 USBC_Dev_FlushFifo(g_sunxi_udc_io.usb_bsp_hdle, ep_type);
2350
2351 /**
2352 * set max packet ,type, direction, address;
2353 * reset fifo counters, enable irq
2354 */
2355 USBC_Dev_ConfigEp(g_sunxi_udc_io.usb_bsp_hdle,
2356 ts_type, ep_type, double_fifo,
2357 (_ep->maxpacket & 0x7ff));
2358 USBC_ConfigFifo(g_sunxi_udc_io.usb_bsp_hdle,
2359 ep_type, double_fifo, fifo_size,
2360 fifo_addr);
2361 if (ts_type == USBC_TS_TYPE_ISO)
2362 USBC_Dev_IsoUpdateEnable(g_sunxi_udc_io.usb_bsp_hdle);
2363
2364 USBC_INT_EnableEp(g_sunxi_udc_io.usb_bsp_hdle, ep_type, ep->num);
2365
2366 USBC_SelectActiveEp(g_sunxi_udc_io.usb_bsp_hdle, old_ep_index);
2367
2368 end:
2369 spin_unlock_irqrestore(&ep->dev->lock, flags);
2370
2371 sunxi_udc_set_halt(_ep, 0);
2372 return 0;
2373 }
2374
sunxi_udc_ep_disable(struct usb_ep * _ep)2375 static int sunxi_udc_ep_disable(struct usb_ep *_ep)
2376 {
2377 struct sunxi_udc_ep *ep = NULL;
2378 u32 old_ep_index = 0;
2379 unsigned long flags = 0;
2380
2381 if (!_ep) {
2382 DMSG_PANIC("ERR: invalid argment\n");
2383 return -EINVAL;
2384 }
2385
2386 ep = to_sunxi_udc_ep(_ep);
2387 if (ep == NULL) {
2388 DMSG_PANIC("ERR: usbd_ep_disable: ep = NULL\n");
2389 return -EINVAL;
2390 }
2391
2392 if (!ep->desc) {
2393 DMSG_PANIC("ERR: %s not enabled\n", _ep ? ep->ep.name : NULL);
2394 return -EINVAL;
2395 }
2396
2397 DMSG_INFO_UDC("ep disable: ep%d(0x%p, %s, %d, %x)\n",
2398 ep->num, _ep, _ep->name,
2399 (ep->bEndpointAddress & USB_DIR_IN), _ep->maxpacket);
2400
2401 spin_lock_irqsave(&ep->dev->lock, flags);
2402
2403 DMSG_DBG_UDC("ep_disable: %s\n", _ep->name);
2404
2405 ep->desc = NULL;
2406 ep->halted = 1;
2407 sunxi_udc_ep_config_reset(ep);
2408
2409 sunxi_udc_nuke(ep->dev, ep, -ESHUTDOWN);
2410
2411 if (!is_peripheral_active()) {
2412 DMSG_INFO_UDC("%s_%d: usb device is not active\n",
2413 __func__, __LINE__);
2414 goto end;
2415 }
2416
2417 old_ep_index = USBC_GetActiveEp(g_sunxi_udc_io.usb_bsp_hdle);
2418 USBC_SelectActiveEp(g_sunxi_udc_io.usb_bsp_hdle, ep->num);
2419
2420 if ((ep->bEndpointAddress) & USB_DIR_IN) { /* tx */
2421 USBC_Dev_ConfigEp_Default(g_sunxi_udc_io.usb_bsp_hdle,
2422 USBC_EP_TYPE_TX);
2423 USBC_INT_DisableEp(g_sunxi_udc_io.usb_bsp_hdle,
2424 USBC_EP_TYPE_TX, ep->num);
2425 } else { /* rx */
2426 USBC_Dev_ConfigEp_Default(g_sunxi_udc_io.usb_bsp_hdle,
2427 USBC_EP_TYPE_RX);
2428 USBC_INT_DisableEp(g_sunxi_udc_io.usb_bsp_hdle,
2429 USBC_EP_TYPE_RX, ep->num);
2430 }
2431
2432 USBC_SelectActiveEp(g_sunxi_udc_io.usb_bsp_hdle, old_ep_index);
2433
2434 end:
2435 spin_unlock_irqrestore(&ep->dev->lock, flags);
2436
2437 DMSG_DBG_UDC("%s disabled\n", _ep->name);
2438 return 0;
2439 }
2440
sunxi_udc_alloc_request(struct usb_ep * _ep,gfp_t mem_flags)2441 static struct usb_request *sunxi_udc_alloc_request(
2442 struct usb_ep *_ep,
2443 gfp_t mem_flags)
2444 {
2445 struct sunxi_udc_request *req = NULL;
2446
2447 if (!_ep) {
2448 DMSG_PANIC("ERR: invalid argment\n");
2449 return NULL;
2450 }
2451
2452 req = kzalloc(sizeof(struct sunxi_udc_request), mem_flags | GFP_ATOMIC);
2453 if (!req) {
2454 DMSG_PANIC("ERR: kzalloc failed\n");
2455 return NULL;
2456 }
2457
2458 memset(req, 0, sizeof(struct sunxi_udc_request));
2459
2460 req->req.dma = DMA_ADDR_INVALID;
2461
2462 INIT_LIST_HEAD(&req->queue);
2463
2464 DMSG_INFO_UDC("alloc request: ep(0x%p, %s, %d), req(0x%p)\n",
2465 _ep, _ep->name, _ep->maxpacket, req);
2466
2467 return &req->req;
2468 }
2469
sunxi_udc_free_request(struct usb_ep * _ep,struct usb_request * _req)2470 static void sunxi_udc_free_request(struct usb_ep *_ep, struct usb_request *_req)
2471 {
2472 struct sunxi_udc_request *req = NULL;
2473
2474 if (_ep == NULL || _req == NULL) {
2475 DMSG_PANIC("ERR: invalid argment\n");
2476 return;
2477 }
2478
2479 req = to_sunxi_udc_req(_req);
2480 if (req == NULL) {
2481 DMSG_PANIC("ERR: invalid argment\n");
2482 return;
2483 }
2484
2485 DMSG_INFO_UDC("free request: ep(0x%p, %s, %d), req(0x%p)\n",
2486 _ep, _ep->name, _ep->maxpacket, req);
2487
2488 kfree(req);
2489 }
2490
sunxi_udc_queue(struct usb_ep * _ep,struct usb_request * _req,gfp_t gfp_flags)2491 static int sunxi_udc_queue(struct usb_ep *_ep,
2492 struct usb_request *_req, gfp_t gfp_flags)
2493 {
2494 struct sunxi_udc_request *req = NULL;
2495 struct sunxi_udc_ep *ep = NULL;
2496 struct sunxi_udc *dev = NULL;
2497 unsigned long flags = 0;
2498 u8 old_ep_index = 0;
2499
2500 if (_ep == NULL || _req == NULL) {
2501 DMSG_PANIC("ERR: invalid argment\n");
2502 return -EINVAL;
2503 }
2504
2505 ep = to_sunxi_udc_ep(_ep);
2506 if ((ep == NULL || (!ep->desc && _ep->name != ep0name))) {
2507 DMSG_PANIC("ERR: sunxi_udc_queue: inval 2\n");
2508 return -EINVAL;
2509 }
2510
2511 dev = ep->dev;
2512 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
2513 DMSG_PANIC("ERR : dev->driver=0x%p, dev->gadget.speed=%x\n",
2514 dev->driver, dev->gadget.speed);
2515 return -ESHUTDOWN;
2516 }
2517
2518 if (!_req->complete || !_req->buf) {
2519 DMSG_PANIC("ERR: usbd_queue: _req is invalid\n");
2520 return -EINVAL;
2521 }
2522
2523 req = to_sunxi_udc_req(_req);
2524 if (!req) {
2525 DMSG_PANIC("ERR: req is NULL\n");
2526 return -EINVAL;
2527 }
2528
2529 sunxi_udc_handle_unaligned_buf_start(ep, req);
2530 spin_lock_irqsave(&ep->dev->lock, flags);
2531 _req->status = -EINPROGRESS;
2532 _req->actual = 0;
2533
2534 if (is_sunxi_udc_dma_capable(req, ep)) {
2535 spin_unlock_irqrestore(&ep->dev->lock, flags);
2536 sunxi_udc_map_dma_buffer(req, dev, ep);
2537 spin_lock_irqsave(&ep->dev->lock, flags);
2538 }
2539
2540 list_add_tail(&req->queue, &ep->queue);
2541
2542 if (!is_peripheral_active()) {
2543 DMSG_PANIC("warn: peripheral is active\n");
2544 goto end;
2545 }
2546
2547 if (g_queue_debug)
2548 DMSG_INFO("q:(0x%p,%d,%d)\n", _req, _req->length, _req->actual);
2549
2550 old_ep_index = USBC_GetActiveEp(g_sunxi_udc_io.usb_bsp_hdle);
2551 if (ep->bEndpointAddress)
2552 USBC_SelectActiveEp(g_sunxi_udc_io.usb_bsp_hdle,
2553 ep->bEndpointAddress & 0x7F);
2554 else
2555 USBC_SelectActiveEp(g_sunxi_udc_io.usb_bsp_hdle, 0);
2556
2557 /* if there is only one in the queue, then execute it */
2558 if (!ep->halted && (&req->queue == ep->queue.next)) {
2559 if (ep->bEndpointAddress == 0 /* ep0 */) {
2560 switch (dev->ep0state) {
2561 case EP0_IN_DATA_PHASE:
2562 if (!USBC_Dev_IsWriteDataReady(
2563 g_sunxi_udc_io.usb_bsp_hdle,
2564 USBC_EP_TYPE_EP0)
2565 && sunxi_udc_write_fifo(ep, req)) {
2566 dev->ep0state = EP0_IDLE;
2567 req = NULL;
2568 }
2569 break;
2570 case EP0_OUT_DATA_PHASE:
2571 if ((!_req->length)
2572 || (USBC_Dev_IsReadDataReady(
2573 g_sunxi_udc_io.usb_bsp_hdle,
2574 USBC_EP_TYPE_EP0)
2575 && sunxi_udc_read_fifo(ep, req))) {
2576 dev->ep0state = EP0_IDLE;
2577 req = NULL;
2578 }
2579 break;
2580 default:
2581 spin_unlock_irqrestore(&ep->dev->lock, flags);
2582 return -EL2HLT;
2583 }
2584 } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0
2585 && !USBC_Dev_IsWriteDataReady(
2586 g_sunxi_udc_io.usb_bsp_hdle,
2587 USBC_EP_TYPE_TX)) {
2588 #if (IS_ENABLED(CONFIG_USB_G_WEBCAM) || IS_ENABLED(CONFIG_USB_CONFIGFS_F_UVC)) \
2589 && IS_ENABLED(CONFIG_SMP)
2590 /**
2591 * not execute req when only one in the queue, otherwise
2592 * it will be deadlocked for webcam on SMP.
2593 */
2594 if ((ep->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
2595 == USB_ENDPOINT_XFER_ISOC) {
2596 int ret = 0;
2597
2598 ret = USBC_Dev_WriteDataStatus(
2599 g_sunxi_udc_io.usb_bsp_hdle,
2600 USBC_EP_TYPE_TX, 1);
2601 if (ret != 0) {
2602 DMSG_PANIC("ERR: USBC_Dev_WriteDataStatus, failed\n");
2603 req->req.status = -EOVERFLOW;
2604 USBC_SelectActiveEp(
2605 g_sunxi_udc_io.usb_bsp_hdle,
2606 old_ep_index);
2607 spin_unlock_irqrestore(&ep->dev->lock,
2608 flags);
2609 return req->req.status;
2610 }
2611 } else if (sunxi_udc_write_fifo(ep, req)) {
2612 req = NULL;
2613 }
2614 #else
2615 if (sunxi_udc_write_fifo(ep, req))
2616 req = NULL;
2617 #endif
2618 } else if ((ep->bEndpointAddress & USB_DIR_IN) == 0
2619 && USBC_Dev_IsReadDataReady(
2620 g_sunxi_udc_io.usb_bsp_hdle,
2621 USBC_EP_TYPE_RX)) {
2622 if (sunxi_udc_read_fifo(ep, req))
2623 req = NULL;
2624 }
2625 }
2626
2627 USBC_SelectActiveEp(g_sunxi_udc_io.usb_bsp_hdle, old_ep_index);
2628
2629 end:
2630 spin_unlock_irqrestore(&ep->dev->lock, flags);
2631 return 0;
2632 }
2633
sunxi_udc_dequeue(struct usb_ep * _ep,struct usb_request * _req)2634 static int sunxi_udc_dequeue(struct usb_ep *_ep, struct usb_request *_req)
2635 {
2636 struct sunxi_udc_ep *ep = NULL;
2637 struct sunxi_udc *udc = NULL;
2638 int retval = -EINVAL;
2639 struct sunxi_udc_request *req = NULL;
2640 unsigned long flags = 0;
2641
2642 DMSG_DBG_UDC("(%p,%p)\n", _ep, _req);
2643
2644 if (!the_controller->driver) {
2645 DMSG_PANIC("ERR: sunxi_udc_dequeue: driver is null\n");
2646 return -ESHUTDOWN;
2647 }
2648
2649 if (!_ep || !_req) {
2650 DMSG_PANIC("ERR: sunxi_udc_dequeue: invalid argment\n");
2651 return retval;
2652 }
2653
2654 ep = to_sunxi_udc_ep(_ep);
2655 if (ep == NULL) {
2656 DMSG_PANIC("ERR: ep == NULL\n");
2657 return -EINVAL;
2658 }
2659
2660 udc = to_sunxi_udc(ep->gadget);
2661 if (udc == NULL) {
2662 DMSG_PANIC("ERR: ep == NULL\n");
2663 return -EINVAL;
2664 }
2665
2666 DMSG_INFO_UDC("dequeue: ep(0x%p, %d), _req(0x%p, %d, %d)\n",
2667 ep, ep->num,
2668 _req, _req->length, _req->actual);
2669
2670 spin_lock_irqsave(&ep->dev->lock, flags);
2671
2672 list_for_each_entry(req, &ep->queue, queue) {
2673 if (&req->req == _req) {
2674 list_del_init(&req->queue);
2675 _req->status = -ECONNRESET;
2676 retval = 0;
2677 break;
2678 }
2679 }
2680
2681 if (retval == 0) {
2682 DMSG_DBG_UDC("dequeued req %p from %s, len %d buf %p\n",
2683 req, _ep->name, _req->length, _req->buf);
2684
2685 sunxi_udc_done(ep, req, -ECONNRESET);
2686 /*
2687 * If dma is capable, we should disable the dma channel and
2688 * clean dma status, or it would cause dma hang when unexpected
2689 * abort occurs.
2690 */
2691 #ifdef SW_UDC_DMA_INNER
2692 if (is_sunxi_udc_dma_capable(req, ep)) {
2693 sunxi_udc_dma_chan_disable((dm_hdl_t)ep->dma_hdle);
2694 sunxi_udc_clean_dma_status(ep);
2695 }
2696 #endif
2697 }
2698
2699 spin_unlock_irqrestore(&ep->dev->lock, flags);
2700 return retval;
2701 }
2702
sunxi_udc_set_halt_ex(struct usb_ep * _ep,int value,int is_in)2703 static int sunxi_udc_set_halt_ex(struct usb_ep *_ep, int value, int is_in)
2704 {
2705 struct sunxi_udc_ep *ep = NULL;
2706 u32 idx = 0;
2707 __u8 old_ep_index = 0;
2708
2709 if (_ep == NULL) {
2710 DMSG_PANIC("ERR: invalid argment\n");
2711 return -EINVAL;
2712 }
2713
2714 ep = to_sunxi_udc_ep(_ep);
2715 if (ep == NULL) {
2716 DMSG_PANIC("ERR: invalid argment\n");
2717 return -EINVAL;
2718 }
2719
2720 if (!ep->desc && ep->ep.name != ep0name) {
2721 DMSG_PANIC("ERR: !ep->desc && ep->ep.name != ep0name\n");
2722 return -EINVAL;
2723 }
2724
2725 if (!is_peripheral_active()) {
2726 DMSG_INFO_UDC("%s_%d: usb device is not active\n",
2727 __func__, __LINE__);
2728 return 0;
2729 }
2730
2731 idx = ep->bEndpointAddress & 0x7F;
2732
2733 old_ep_index = USBC_GetActiveEp(g_sunxi_udc_io.usb_bsp_hdle);
2734 USBC_SelectActiveEp(g_sunxi_udc_io.usb_bsp_hdle, idx);
2735
2736 if (idx == 0) {
2737 USBC_Dev_EpClearStall(
2738 g_sunxi_udc_io.usb_bsp_hdle,
2739 USBC_EP_TYPE_EP0);
2740 } else {
2741 if (is_in) {
2742 if (value) {
2743 USBC_Dev_EpSendStall(
2744 g_sunxi_udc_io.usb_bsp_hdle,
2745 USBC_EP_TYPE_TX);
2746 } else {
2747 USBC_Dev_EpClearStall(
2748 g_sunxi_udc_io.usb_bsp_hdle,
2749 USBC_EP_TYPE_TX);
2750 }
2751 } else {
2752 if (value)
2753 USBC_Dev_EpSendStall(
2754 g_sunxi_udc_io.usb_bsp_hdle,
2755 USBC_EP_TYPE_RX);
2756 else
2757 USBC_Dev_EpClearStall(
2758 g_sunxi_udc_io.usb_bsp_hdle,
2759 USBC_EP_TYPE_RX);
2760 }
2761 }
2762
2763 ep->halted = value ? 1 : 0;
2764
2765 USBC_SelectActiveEp(g_sunxi_udc_io.usb_bsp_hdle, old_ep_index);
2766 return 0;
2767 }
2768
sunxi_udc_set_halt(struct usb_ep * _ep,int value)2769 static int sunxi_udc_set_halt(struct usb_ep *_ep, int value)
2770 {
2771 struct sunxi_udc_ep *ep = NULL;
2772 unsigned long flags = 0;
2773 u32 idx = 0;
2774 __u8 old_ep_index = 0;
2775
2776 if (_ep == NULL) {
2777 DMSG_PANIC("ERR: invalid argment\n");
2778 return -EINVAL;
2779 }
2780
2781 ep = to_sunxi_udc_ep(_ep);
2782 if (ep == NULL) {
2783 DMSG_PANIC("ERR: invalid argment\n");
2784 return -EINVAL;
2785 }
2786
2787 if (!ep->desc && ep->ep.name != ep0name) {
2788 DMSG_PANIC("ERR: !ep->desc && ep->ep.name != ep0name\n");
2789 return -EINVAL;
2790 }
2791
2792 if (!is_peripheral_active()) {
2793 DMSG_INFO_UDC("%s_%d: usb device is not active\n",
2794 __func__, __LINE__);
2795 return 0;
2796 }
2797
2798 spin_lock_irqsave(&ep->dev->lock, flags);
2799
2800 idx = ep->bEndpointAddress & 0x7F;
2801
2802 old_ep_index = USBC_GetActiveEp(g_sunxi_udc_io.usb_bsp_hdle);
2803 USBC_SelectActiveEp(g_sunxi_udc_io.usb_bsp_hdle, idx);
2804
2805 if (idx == 0) {
2806 USBC_Dev_EpClearStall(
2807 g_sunxi_udc_io.usb_bsp_hdle,
2808 USBC_EP_TYPE_EP0);
2809 } else {
2810 if ((ep->bEndpointAddress & USB_DIR_IN) != 0) {
2811 if (value)
2812 USBC_Dev_EpSendStall(
2813 g_sunxi_udc_io.usb_bsp_hdle,
2814 USBC_EP_TYPE_TX);
2815 else
2816 USBC_Dev_EpClearStall(
2817 g_sunxi_udc_io.usb_bsp_hdle,
2818 USBC_EP_TYPE_TX);
2819 } else {
2820 if (value)
2821 USBC_Dev_EpSendStall(
2822 g_sunxi_udc_io.usb_bsp_hdle,
2823 USBC_EP_TYPE_RX);
2824 else
2825 USBC_Dev_EpClearStall(
2826 g_sunxi_udc_io.usb_bsp_hdle,
2827 USBC_EP_TYPE_RX);
2828 }
2829 }
2830
2831 ep->halted = value ? 1 : 0;
2832
2833 USBC_SelectActiveEp(g_sunxi_udc_io.usb_bsp_hdle, old_ep_index);
2834
2835 spin_unlock_irqrestore(&ep->dev->lock, flags);
2836 return 0;
2837 }
2838
2839 static const struct usb_ep_ops sunxi_udc_ep_ops = {
2840 .enable = sunxi_udc_ep_enable,
2841 .disable = sunxi_udc_ep_disable,
2842
2843 .alloc_request = sunxi_udc_alloc_request,
2844 .free_request = sunxi_udc_free_request,
2845
2846 .queue = sunxi_udc_queue,
2847 .dequeue = sunxi_udc_dequeue,
2848
2849 .set_halt = sunxi_udc_set_halt,
2850 };
2851
sunxi_udc_get_frame(struct usb_gadget * _gadget)2852 static int sunxi_udc_get_frame(struct usb_gadget *_gadget)
2853 {
2854 int ret = 0;
2855
2856 if (!is_peripheral_active()) {
2857 DMSG_INFO_UDC("%s_%d: usb device is not active\n",
2858 __func__, __LINE__);
2859 return 0;
2860 }
2861
2862 DMSG_INFO_UDC("sunxi_udc_get_frame is no susport\n");
2863
2864 return ret;
2865 }
2866
sunxi_udc_wakeup(struct usb_gadget * _gadget)2867 static int sunxi_udc_wakeup(struct usb_gadget *_gadget)
2868 {
2869 if (!is_peripheral_active()) {
2870 DMSG_INFO_UDC("%s_%d: usb device is not active\n",
2871 __func__, __LINE__);
2872 return 0;
2873 }
2874
2875 return 0;
2876 }
2877
sunxi_udc_set_selfpowered(struct usb_gadget * gadget,int value)2878 static int sunxi_udc_set_selfpowered(struct usb_gadget *gadget, int value)
2879 {
2880 if (!is_peripheral_active()) {
2881 DMSG_INFO_UDC("%s_%d: usb device is not active\n",
2882 __func__, __LINE__);
2883 return 0;
2884 }
2885
2886 return 0;
2887 }
2888
2889 static void sunxi_udc_disable(struct sunxi_udc *dev);
2890 static void sunxi_udc_enable(struct sunxi_udc *dev);
2891
sunxi_udc_set_pullup(struct sunxi_udc * udc,int is_on)2892 static int sunxi_udc_set_pullup(struct sunxi_udc *udc, int is_on)
2893 {
2894 DMSG_DBG_UDC("sunxi_udc_set_pullup\n");
2895
2896 is_udc_enable = is_on;
2897
2898 if (!is_peripheral_active()) {
2899 DMSG_INFO_UDC("%s_%d: usb device is not active\n",
2900 __func__, __LINE__);
2901 return 0;
2902 }
2903
2904 if (is_on) {
2905 sunxi_udc_enable(udc);
2906 } else {
2907 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
2908 if (udc->driver && udc->driver->disconnect)
2909 udc->driver->disconnect(&udc->gadget);
2910 }
2911
2912 sunxi_udc_disable(udc);
2913 }
2914
2915 return 0;
2916 }
2917
sunxi_udc_vbus_session(struct usb_gadget * gadget,int is_active)2918 static int sunxi_udc_vbus_session(struct usb_gadget *gadget, int is_active)
2919 {
2920 struct sunxi_udc *udc = to_sunxi_udc(gadget);
2921
2922 DMSG_DBG_UDC("sunxi_udc_vbus_session\n");
2923
2924 if (!is_peripheral_active()) {
2925 DMSG_INFO_UDC("%s_%d: usb device is not active\n",
2926 __func__, __LINE__);
2927 return 0;
2928 }
2929
2930 udc->vbus = (is_active != 0);
2931 sunxi_udc_set_pullup(udc, is_active);
2932
2933 return 0;
2934 }
2935
sunxi_udc_pullup(struct usb_gadget * gadget,int is_on)2936 static int sunxi_udc_pullup(struct usb_gadget *gadget, int is_on)
2937 {
2938 struct sunxi_udc *udc = to_sunxi_udc(gadget);
2939
2940 DMSG_INFO_UDC("sunxi_udc_pullup, is_on = %d\n", is_on);
2941
2942 sunxi_udc_set_pullup(udc, is_on);
2943 return 0;
2944 }
2945
sunxi_udc_vbus_draw(struct usb_gadget * _gadget,unsigned ma)2946 static int sunxi_udc_vbus_draw(struct usb_gadget *_gadget, unsigned ma)
2947 {
2948 if (!is_peripheral_active()) {
2949 DMSG_INFO("%s_%d: usb device is not active\n",
2950 __func__, __LINE__);
2951 return 0;
2952 }
2953
2954 DMSG_DBG_UDC("sunxi_udc_vbus_draw\n");
2955
2956 cfg_vbus_draw(ma);
2957 return 0;
2958 }
2959
sunxi_get_udc_base(struct platform_device * pdev,sunxi_udc_io_t * sunxi_udc_io)2960 static int sunxi_get_udc_base(struct platform_device *pdev,
2961 sunxi_udc_io_t *sunxi_udc_io)
2962 {
2963
2964 struct device_node *np = pdev->dev.of_node;
2965
2966 sunxi_udc_io->usb_vbase = of_iomap(np, 0);
2967 if (sunxi_udc_io->usb_vbase == NULL) {
2968 dev_err(&pdev->dev, "can't get usb_vbase resource\n");
2969 return -EINVAL;
2970 }
2971
2972 #if defined(CONFIG_ARCH_SUN50IW10)
2973 sunxi_udc_io->usb_common_phy_config = of_iomap(np, 2);
2974 if (sunxi_udc_io->usb_common_phy_config == NULL) {
2975 dev_err(&pdev->dev, "can't get common phy resource\n");
2976 return -EINVAL;
2977 }
2978 #endif
2979
2980 return 0;
2981 }
2982
sunxi_get_udc_clock(struct platform_device * pdev,sunxi_udc_io_t * sunxi_udc_io)2983 static int sunxi_get_udc_clock(struct platform_device *pdev,
2984 sunxi_udc_io_t *sunxi_udc_io)
2985 {
2986 sunxi_udc_io->clk_bus_otg = devm_clk_get(&pdev->dev, "bus_otg");
2987 if (IS_ERR(sunxi_udc_io->clk_bus_otg)) {
2988 dev_err(&pdev->dev, "Could not get bus_otg clock\n");
2989 return PTR_ERR(sunxi_udc_io->clk_bus_otg);
2990 }
2991
2992 #if !defined(CONFIG_ARCH_SUN8IW20) && !defined(CONFIG_ARCH_SUN20IW1) && !defined(CONFIG_ARCH_SUN50IW12)
2993 sunxi_udc_io->clk_phy = devm_clk_get(&pdev->dev, "phy");
2994 if (IS_ERR(sunxi_udc_io->clk_phy)) {
2995 dev_err(&pdev->dev, "Could not get phy clock\n");
2996 return PTR_ERR(sunxi_udc_io->clk_phy);
2997 }
2998 #endif
2999
3000 sunxi_udc_io->reset_otg = devm_reset_control_get(&pdev->dev, "otg");
3001 if (IS_ERR(sunxi_udc_io->reset_otg))
3002 dev_warn(&pdev->dev, "Could not get otg rst\n");
3003
3004 sunxi_udc_io->reset_phy = devm_reset_control_get_optional_shared(&pdev->dev, "phy");
3005 if (IS_ERR(sunxi_udc_io->reset_phy))
3006 dev_warn(&pdev->dev, "Could not get phy rst\n");
3007
3008 return 0;
3009 }
3010
3011 /* gadget driver handling */
sunxi_udc_reinit(struct sunxi_udc * dev)3012 static void sunxi_udc_reinit(struct sunxi_udc *dev)
3013 {
3014 u32 i = 0;
3015
3016 /* device/ep0 records init */
3017 INIT_LIST_HEAD(&dev->gadget.ep_list);
3018 INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
3019 dev->ep0state = EP0_IDLE;
3020
3021 for (i = 0; i < SW_UDC_ENDPOINTS; i++) {
3022 struct sunxi_udc_ep *ep = &dev->ep[i];
3023
3024 if (i != 0)
3025 list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
3026
3027 ep->dev = dev;
3028 ep->desc = NULL;
3029 ep->halted = 0;
3030 INIT_LIST_HEAD(&ep->queue);
3031 }
3032 }
3033
sunxi_udc_enable(struct sunxi_udc * dev)3034 static void sunxi_udc_enable(struct sunxi_udc *dev)
3035 {
3036 int ret;
3037
3038 DMSG_DBG_UDC("sunxi_udc_enable called\n");
3039
3040 if (!IS_ERR_OR_NULL(dev->udc_regulator)) {
3041 ret = regulator_enable(dev->udc_regulator);
3042 if (ret)
3043 DMSG_PANIC("ERR:udc regulator enable failed\n");
3044 }
3045
3046 dev->gadget.speed = USB_SPEED_UNKNOWN;
3047
3048 DMSG_INFO_UDC("CONFIG_USB_GADGET_DUALSPEED: USBC_TS_MODE_HS\n");
3049
3050 USBC_Dev_ConfigTransferMode(
3051 g_sunxi_udc_io.usb_bsp_hdle,
3052 USBC_TS_TYPE_BULK,
3053 USBC_TS_MODE_HS);
3054
3055 /* Enable reset and suspend interrupt interrupts */
3056 USBC_INT_EnableUsbMiscUint(g_sunxi_udc_io.usb_bsp_hdle,
3057 USBC_INTUSB_SUSPEND);
3058 USBC_INT_EnableUsbMiscUint(g_sunxi_udc_io.usb_bsp_hdle,
3059 USBC_INTUSB_RESUME);
3060 USBC_INT_EnableUsbMiscUint(g_sunxi_udc_io.usb_bsp_hdle,
3061 USBC_INTUSB_RESET);
3062
3063 /* Enable ep0 interrupt */
3064 USBC_INT_EnableEp(g_sunxi_udc_io.usb_bsp_hdle,
3065 USBC_EP_TYPE_TX, 0);
3066
3067 cfg_udc_command(SW_UDC_P_ENABLE);
3068 }
3069
sunxi_udc_disable(struct sunxi_udc * dev)3070 static void sunxi_udc_disable(struct sunxi_udc *dev)
3071 {
3072 DMSG_DBG_UDC("sunxi_udc_disable\n");
3073 /* Disable all interrupts */
3074 USBC_INT_DisableUsbMiscAll(g_sunxi_udc_io.usb_bsp_hdle);
3075 USBC_INT_DisableEpAll(g_sunxi_udc_io.usb_bsp_hdle, USBC_EP_TYPE_RX);
3076 USBC_INT_DisableEpAll(g_sunxi_udc_io.usb_bsp_hdle, USBC_EP_TYPE_TX);
3077
3078 /* Clear the interrupt registers */
3079 clear_all_irq();
3080 cfg_udc_command(SW_UDC_P_DISABLE);
3081
3082 /* Set speed to unknown */
3083 dev->gadget.speed = USB_SPEED_UNKNOWN;
3084
3085 if (!IS_ERR_OR_NULL(dev->udc_regulator))
3086 regulator_disable(dev->udc_regulator);
3087 }
3088
usbd_start_work(void)3089 static s32 usbd_start_work(void)
3090 {
3091 DMSG_INFO_UDC("usbd_start_work\n");
3092
3093 if (!is_peripheral_active()) {
3094 DMSG_INFO_UDC("%s_%d: usb device is not active\n",
3095 __func__, __LINE__);
3096 return 0;
3097 }
3098
3099 USBC_Dev_ConectSwitch(g_sunxi_udc_io.usb_bsp_hdle,
3100 USBC_DEVICE_SWITCH_ON);
3101 return 0;
3102 }
3103
usbd_stop_work(void)3104 static s32 usbd_stop_work(void)
3105 {
3106 DMSG_INFO_UDC("usbd_stop_work\n");
3107
3108 if (!is_peripheral_active()) {
3109 DMSG_INFO_UDC("%s_%d: usb device is not active\n",
3110 __func__, __LINE__);
3111 return 0;
3112 }
3113
3114 USBC_Dev_ConectSwitch(g_sunxi_udc_io.usb_bsp_hdle,
3115 USBC_DEVICE_SWITCH_OFF); /* default is pulldown */
3116 return 0;
3117 }
3118
sunxi_udc_start(struct usb_gadget * g,struct usb_gadget_driver * driver)3119 static int sunxi_udc_start(struct usb_gadget *g,
3120 struct usb_gadget_driver *driver)
3121 {
3122 struct sunxi_udc *udc = the_controller;
3123
3124 /* Sanity checks */
3125 if (!udc) {
3126 DMSG_PANIC("ERR: udc is null\n");
3127 return -ENODEV;
3128 }
3129
3130 if (udc->driver) {
3131 DMSG_PANIC("ERR: udc->driver is not null\n");
3132 return -EBUSY;
3133 }
3134
3135 /**
3136 * the struct usb_gadget_driver has a little change
3137 * between linux 3.0 and linux-3.3, speed->max_speed
3138 */
3139 if (!driver->setup || driver->max_speed < USB_SPEED_FULL) {
3140 DMSG_PANIC("ERR: Invalid setup %p speed %d\n",
3141 driver->setup, driver->max_speed);
3142 return -EINVAL;
3143 }
3144
3145 #if defined(MODULE)
3146 if (!driver->unbind) {
3147 DMSG_PANIC("Invalid driver: no unbind method\n");
3148 return -EINVAL;
3149 }
3150 #endif
3151
3152 /* Hook the driver */
3153 udc->driver = driver;
3154 udc->gadget.dev.driver = &driver->driver;
3155
3156 DMSG_INFO_UDC("[%s]: binding gadget driver '%s'\n",
3157 gadget_name, driver->driver.name);
3158
3159 return 0;
3160 }
3161
sunxi_udc_stop(struct usb_gadget * g)3162 static int sunxi_udc_stop(struct usb_gadget *g)
3163 {
3164 struct sunxi_udc *udc = the_controller;
3165 struct usb_gadget_driver *driver;
3166
3167 if (!udc) {
3168 DMSG_PANIC("ERR: udc is null\n");
3169 return -ENODEV;
3170 }
3171 driver = udc->driver;
3172 if (!driver || driver != udc->driver || !driver->unbind) {
3173 DMSG_PANIC("ERR: driver is null\n");
3174 return -EINVAL;
3175 }
3176
3177 DMSG_INFO_UDC("[%s]: usb_gadget_unregister_driver() '%s'\n",
3178 gadget_name, driver->driver.name);
3179
3180 udc->gadget.dev.driver = NULL;
3181 udc->driver = NULL;
3182
3183 /* Disable udc */
3184 sunxi_udc_disable(udc);
3185 return 0;
3186 }
3187
3188 static const struct usb_gadget_ops sunxi_udc_ops = {
3189 .get_frame = sunxi_udc_get_frame,
3190 .wakeup = sunxi_udc_wakeup,
3191 .set_selfpowered = sunxi_udc_set_selfpowered,
3192 .pullup = sunxi_udc_pullup,
3193 .vbus_session = sunxi_udc_vbus_session,
3194 .vbus_draw = sunxi_udc_vbus_draw,
3195 .udc_start = sunxi_udc_start,
3196 .udc_stop = sunxi_udc_stop,
3197 };
3198
3199 static struct sunxi_udc sunxi_udc = {
3200 .gadget = {
3201 .ops = &sunxi_udc_ops,
3202 .ep0 = &sunxi_udc.ep[0].ep,
3203 .name = gadget_name,
3204 .dev = {
3205 .init_name = "gadget",
3206 },
3207 },
3208
3209 .ep[0] = {
3210 .num = 0,
3211 .ep = {
3212 .name = ep0name,
3213 .ops = &sunxi_udc_ep_ops,
3214 .maxpacket = EP0_FIFO_SIZE,
3215 .maxpacket_limit = EP0_FIFO_SIZE,
3216 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL,
3217 USB_EP_CAPS_DIR_ALL),
3218 },
3219 .dev = &sunxi_udc,
3220 },
3221
3222 .ep[1] = {
3223 .num = 1,
3224 .ep = {
3225 .name = ep1in_bulk_name,
3226 .ops = &sunxi_udc_ep_ops,
3227 .maxpacket = SW_UDC_EP_FIFO_SIZE,
3228 .maxpacket_limit = SW_UDC_EP_FIFO_SIZE,
3229 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
3230 USB_EP_CAPS_DIR_IN),
3231 },
3232 .dev = &sunxi_udc,
3233 .bEndpointAddress = (USB_DIR_IN | 1),
3234 .bmAttributes = USB_ENDPOINT_XFER_BULK,
3235 },
3236
3237 .ep[2] = {
3238 .num = 1,
3239 .ep = {
3240 .name = ep1out_bulk_name,
3241 .ops = &sunxi_udc_ep_ops,
3242 .maxpacket = SW_UDC_EP_FIFO_SIZE,
3243 .maxpacket_limit = SW_UDC_EP_FIFO_SIZE,
3244 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
3245 USB_EP_CAPS_DIR_OUT),
3246 },
3247 .dev = &sunxi_udc,
3248 .bEndpointAddress = (USB_DIR_OUT | 1),
3249 .bmAttributes = USB_ENDPOINT_XFER_BULK,
3250 },
3251
3252 .ep[3] = {
3253 .num = 2,
3254 .ep = {
3255 .name = ep2in_bulk_name,
3256 .ops = &sunxi_udc_ep_ops,
3257 .maxpacket = SW_UDC_EP_FIFO_SIZE,
3258 .maxpacket_limit = SW_UDC_EP_FIFO_SIZE,
3259 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
3260 USB_EP_CAPS_DIR_IN),
3261 },
3262 .dev = &sunxi_udc,
3263 .bEndpointAddress = (USB_DIR_IN | 2),
3264 .bmAttributes = USB_ENDPOINT_XFER_BULK,
3265 },
3266
3267 .ep[4] = {
3268 .num = 2,
3269 .ep = {
3270 .name = ep2out_bulk_name,
3271 .ops = &sunxi_udc_ep_ops,
3272 .maxpacket = SW_UDC_EP_FIFO_SIZE,
3273 .maxpacket_limit = SW_UDC_EP_FIFO_SIZE,
3274 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
3275 USB_EP_CAPS_DIR_OUT),
3276 },
3277 .dev = &sunxi_udc,
3278 .bEndpointAddress = (USB_DIR_OUT | 2),
3279 .bmAttributes = USB_ENDPOINT_XFER_BULK,
3280 },
3281
3282 .ep[5] = {
3283 .num = 3,
3284 .ep = {
3285 .name = ep3_iso_name,
3286 .ops = &sunxi_udc_ep_ops,
3287 .maxpacket = SW_UDC_EP_ISO_FIFO_SIZE,
3288 .maxpacket_limit = SW_UDC_EP_ISO_FIFO_SIZE,
3289 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
3290 USB_EP_CAPS_DIR_ALL),
3291 },
3292 .dev = &sunxi_udc,
3293 .bEndpointAddress = 3,
3294 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
3295 },
3296
3297 .ep[6] = {
3298 .num = 4,
3299 .ep = {
3300 .name = ep4_int_name,
3301 .ops = &sunxi_udc_ep_ops,
3302 .maxpacket = SW_UDC_EP_FIFO_SIZE,
3303 .maxpacket_limit = SW_UDC_EP_FIFO_SIZE,
3304 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
3305 USB_EP_CAPS_DIR_ALL),
3306 },
3307 .dev = &sunxi_udc,
3308 .bEndpointAddress = 4,
3309 .bmAttributes = USB_ENDPOINT_XFER_INT,
3310 },
3311
3312 #if defined(CONFIG_ARCH_SUN50IW1) || defined(CONFIG_ARCH_SUN50IW3) \
3313 || defined(CONFIG_ARCH_SUN8IW6) || defined(CONFIG_ARCH_SUN8IW15) \
3314 || defined(CONFIG_ARCH_SUN50IW10) || defined(CONFIG_ARCH_SUN50IW9) \
3315 || defined(CONFIG_ARCH_SUN8IW20) || defined(CONFIG_ARCH_SUN20IW1)
3316 .ep[7] = {
3317 .num = 5,
3318 .ep = {
3319 .name = ep5in_bulk_name,
3320 .ops = &sunxi_udc_ep_ops,
3321 .maxpacket = SW_UDC_EP_FIFO_SIZE,
3322 .maxpacket_limit = SW_UDC_EP_FIFO_SIZE,
3323 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
3324 USB_EP_CAPS_DIR_IN),
3325 },
3326 .dev = &sunxi_udc,
3327 .bEndpointAddress = (USB_DIR_IN | 5),
3328 .bmAttributes = USB_ENDPOINT_XFER_BULK,
3329 },
3330
3331 .ep[8] = {
3332 .num = 5,
3333 .ep = {
3334 .name = ep5out_bulk_name,
3335 .ops = &sunxi_udc_ep_ops,
3336 .maxpacket = SW_UDC_EP_FIFO_SIZE,
3337 .maxpacket_limit = SW_UDC_EP_FIFO_SIZE,
3338 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
3339 USB_EP_CAPS_DIR_OUT),
3340 },
3341 .dev = &sunxi_udc,
3342 .bEndpointAddress = (USB_DIR_OUT | 5),
3343 .bmAttributes = USB_ENDPOINT_XFER_BULK,
3344 },
3345 #endif
3346
3347 };
3348
sunxi_vbus_det_work(struct work_struct * work)3349 static void sunxi_vbus_det_work(struct work_struct *work)
3350 {
3351 struct sunxi_udc *udc = NULL;
3352 #if defined(CONFIG_POWER_SUPPLY)
3353 struct power_supply *psy = NULL;
3354 union power_supply_propval temp;
3355 struct device_node *np = NULL;
3356 #endif
3357
3358 /* wait for axp vbus detect ready */
3359 msleep(100);
3360
3361 udc = container_of(work, struct sunxi_udc, vbus_det_work);
3362
3363 #if defined(CONFIG_POWER_SUPPLY)
3364 if (of_find_property(g_udc_pdev->dev.of_node, "det_vbus_supply", NULL))
3365 psy = devm_power_supply_get_by_phandle(&g_udc_pdev->dev,
3366 "det_vbus_supply");
3367
3368 if (!psy || IS_ERR(psy)) {
3369 DMSG_PANIC("%s()%d WARN: get power supply failed\n",
3370 __func__, __LINE__);
3371 } else {
3372 power_supply_get_property(psy,
3373 POWER_SUPPLY_PROP_ONLINE, &temp);
3374
3375 while (temp.intval) {
3376 msleep(1000);
3377
3378 /* after resume */
3379 if (usb_connect)
3380 return;
3381 }
3382 }
3383 #endif
3384 if (udc->driver && udc->driver->disconnect) {
3385 udc->driver->disconnect(&udc->gadget);
3386 #if !defined(SUNXI_USB_FPGA) && defined(CONFIG_POWER_SUPPLY)
3387 /*
3388 * When disconnect from PC, we should recover current limit value.
3389 * If get failed, we will set original value.
3390 */
3391 if (psy && !IS_ERR(psy)) {
3392 power_supply_get_property(psy,
3393 POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT, &temp);
3394 np = of_parse_phandle(g_udc_pdev->dev.of_node, "det_vbus_supply", 0);
3395 if (np)
3396 of_property_read_u32(np, "pmu_usbad_cur", &temp.intval);
3397 power_supply_set_property(psy,
3398 POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT, &temp);
3399 }
3400 #endif
3401 }
3402 }
3403
get_otgc_vbase(void)3404 void __iomem *get_otgc_vbase(void)
3405 {
3406 return g_sunxi_udc_io.usb_vbase;
3407
3408 }
3409 EXPORT_SYMBOL_GPL(get_otgc_vbase);
3410
get_dp_dm_status_normal(void)3411 int get_dp_dm_status_normal(void)
3412 {
3413 __u32 reg_val = 0;
3414 __u32 dp = 0;
3415 __u32 dm = 0;
3416
3417 if (g_sunxi_udc_io.usb_vbase == NULL)
3418 return 0;
3419 /* USBC_EnableDpDmPullUp */
3420 reg_val = USBC_Readl(USBC_REG_ISCR(g_sunxi_udc_io.usb_vbase));
3421 reg_val |= (1 << USBC_BP_ISCR_DPDM_PULLUP_EN);
3422 USBC_Writel(reg_val, USBC_REG_ISCR(g_sunxi_udc_io.usb_vbase));
3423
3424 /* USBC_EnableIdPullUp */
3425 reg_val = USBC_Readl(USBC_REG_ISCR(g_sunxi_udc_io.usb_vbase));
3426 reg_val |= (1 << USBC_BP_ISCR_ID_PULLUP_EN);
3427 USBC_Writel(reg_val, USBC_REG_ISCR(g_sunxi_udc_io.usb_vbase));
3428
3429 msleep(20);
3430
3431 reg_val = USBC_Readl(USBC_REG_ISCR(g_sunxi_udc_io.usb_vbase));
3432 dp = (reg_val >> USBC_BP_ISCR_EXT_DP_STATUS) & 0x01;
3433 dm = (reg_val >> USBC_BP_ISCR_EXT_DM_STATUS) & 0x01;
3434
3435 return ((dp << 1) | dm);
3436 }
3437 EXPORT_SYMBOL_GPL(get_dp_dm_status_normal);
3438 static int sunxi_get_udc_resource(struct platform_device *pdev,
3439 sunxi_udc_io_t *sunxi_udc_io);
3440
sunxi_usb_device_enable(void)3441 int sunxi_usb_device_enable(void)
3442 {
3443 struct platform_device *pdev = g_udc_pdev;
3444 struct sunxi_udc *udc = &sunxi_udc;
3445 int retval = 0;
3446 #if defined(CONFIG_ARCH_SUN50IW10)
3447 int val;
3448 #endif
3449
3450 if (pdev == NULL) {
3451 DMSG_PANIC("pdev is null\n");
3452 return -1;
3453 }
3454
3455 usb_connect = 0;
3456 crq_bRequest = 0;
3457 is_controller_alive = 1;
3458
3459 #if defined(CONFIG_ARCH_SUN8IW6)
3460 retval = sunxi_get_udc_resource(pdev, &g_sunxi_udc_io);
3461 if (retval != 0) {
3462 DMSG_PANIC("ERR: sunxi_get_udc_resource, is fail\n");
3463 return -ENODEV;
3464 }
3465
3466 retval = sunxi_udc_io_init(usbd_port_no, &g_sunxi_udc_io);
3467 if (retval != 0) {
3468 DMSG_PANIC("ERR: sunxi_udc_io_init fail\n");
3469 return -1;
3470 }
3471 #endif
3472
3473 #if defined(CONFIG_ARCH_SUN50IW10)
3474 /*phy reg, offset:0x10 bit3 set 0, enable siddq*/
3475 val = USBC_Readl(g_sunxi_udc_io.usb_common_phy_config + SUNXI_HCI_PHY_CTRL);
3476 val &= ~(0x1 << SUNXI_HCI_PHY_CTRL_SIDDQ);
3477 USBC_Writel(val, g_sunxi_udc_io.usb_common_phy_config + SUNXI_HCI_PHY_CTRL);
3478 #endif
3479
3480 retval = sunxi_udc_bsp_init(&g_sunxi_udc_io);
3481 if (retval != 0) {
3482 DMSG_PANIC("ERR: sunxi_udc_bsp_init failed\n");
3483 return -1;
3484 }
3485
3486 sunxi_udc_disable(udc);
3487
3488 udc->irq_no = platform_get_irq(pdev, 0);
3489
3490 if (udc->irq_no < 0) {
3491 DMSG_PANIC("%s,%d: error to get irq\n", __func__, __LINE__);
3492 return -EINVAL;
3493 }
3494
3495 udc->sunxi_udc_io = &g_sunxi_udc_io;
3496 udc->usbc_no = usbd_port_no;
3497 strcpy((char *)udc->driver_name, gadget_name);
3498 udc->pdev = pdev;
3499 udc->controller = &(pdev->dev);
3500
3501 #if IS_ENABLED(CONFIG_OF)
3502 udc->controller->dma_mask = &sunxi_udc_mask;
3503 udc->controller->coherent_dma_mask = DMA_BIT_MASK(64);
3504 #endif
3505
3506 if (is_udc_support_dma()) {
3507 retval = sunxi_udc_dma_probe(udc);
3508 if (retval != 0) {
3509 DMSG_PANIC("ERR: sunxi_udc_dma_probe failef\n");
3510 retval = -EBUSY;
3511 goto err;
3512 }
3513 }
3514
3515
3516 if (first_enable) {
3517 first_enable = 0;
3518 INIT_WORK(&udc->vbus_det_work, sunxi_vbus_det_work);
3519 #if !defined(SUNXI_USB_FPGA) && defined(CONFIG_POWER_SUPPLY)
3520 INIT_WORK(&udc->set_cur_vol_work, sunxi_set_cur_vol_work);
3521 #endif
3522 udc->udc_regulator = devm_regulator_get(&(pdev->dev), "udc");
3523
3524 if (!IS_ERR_OR_NULL(udc->udc_regulator)) {
3525 retval = regulator_enable(udc->udc_regulator);
3526 if (retval)
3527 DMSG_PANIC("ERR:udc regulator enable failed\n");
3528 }
3529 }
3530
3531 retval = request_irq(udc->irq_no, sunxi_udc_irq,
3532 0, gadget_name, udc);
3533 if (retval != 0) {
3534 DMSG_PANIC("ERR: cannot get irq %i, err %d\n",
3535 udc->irq_no, retval);
3536 retval = -EBUSY;
3537 goto err;
3538 }
3539
3540 if (udc->driver && is_udc_enable) {
3541 sunxi_udc_enable(udc);
3542 cfg_udc_command(SW_UDC_P_ENABLE);
3543 }
3544
3545 return 0;
3546 err:
3547 if (is_udc_support_dma())
3548 sunxi_udc_dma_remove(udc);
3549
3550 sunxi_udc_bsp_exit(&g_sunxi_udc_io);
3551 #if defined(CONFIG_ARCH_SUN8IW6)
3552 sunxi_udc_io_exit(&g_sunxi_udc_io);
3553 #endif
3554
3555 return retval;
3556 }
3557 EXPORT_SYMBOL_GPL(sunxi_usb_device_enable);
3558
sunxi_usb_device_disable(void)3559 int sunxi_usb_device_disable(void)
3560 __releases(sunxi_udc.lock)
3561 __acquires(sunxi_udc.lock)
3562 {
3563 struct platform_device *pdev = g_udc_pdev;
3564 struct sunxi_udc *udc = NULL;
3565 unsigned long flags = 0;
3566
3567 DMSG_INFO_UDC("sunxi_usb_device_disable start\n");
3568
3569 if (pdev == NULL) {
3570 DMSG_PANIC("pdev is null\n");
3571 return -1;
3572 }
3573
3574 udc = platform_get_drvdata(pdev);
3575 if (udc == NULL) {
3576 DMSG_PANIC("udc is null\n");
3577 return -1;
3578 }
3579
3580 /* disable usb controller */
3581 if (udc->driver && udc->driver->disconnect)
3582 udc->driver->disconnect(&udc->gadget);
3583
3584 if (is_udc_support_dma()) {
3585 spin_lock_irqsave(&udc->lock, flags);
3586 sunxi_udc_stop_dma_work(udc, 0);
3587 spin_unlock_irqrestore(&udc->lock, flags);
3588 sunxi_udc_dma_remove(udc);
3589 }
3590
3591 free_irq(udc->irq_no, udc);
3592
3593 sunxi_udc_bsp_exit(&g_sunxi_udc_io);
3594
3595 spin_lock_irqsave(&udc->lock, flags);
3596
3597 usb_connect = 0;
3598 if (!charger_mode) {
3599 __pm_relax(udc->ws);
3600 pr_debug("usb_connecting: release wake lock\n");
3601 }
3602
3603 crq_bRequest = 0;
3604 is_controller_alive = 0;
3605
3606 spin_unlock_irqrestore(&udc->lock, flags);
3607
3608 DMSG_INFO_UDC("sunxi_usb_device_disable end\n");
3609
3610 return 0;
3611 }
3612 EXPORT_SYMBOL_GPL(sunxi_usb_device_disable);
3613
sunxi_udc_is_enable(struct platform_device * pdev)3614 int sunxi_udc_is_enable(struct platform_device *pdev)
3615 {
3616 struct device_node *usbc_np = NULL;
3617 int ret = 0;
3618 int is_enable = 0;
3619
3620 const char *used_status;
3621
3622 usbc_np = of_find_node_by_type(NULL, SET_USB0);
3623 ret = of_property_read_string(usbc_np, "status", &used_status);
3624 if (ret) {
3625 DMSG_PANIC("get sunxi_udc_is_enable is fail, %d\n", -ret);
3626 is_enable = 0;
3627 } else if (!strcmp(used_status, "okay")) {
3628 is_enable = 1;
3629 } else {
3630 is_enable = 0;
3631 }
3632
3633 return is_enable;
3634 }
3635
sunxi_get_udc_resource(struct platform_device * pdev,sunxi_udc_io_t * sunxi_udc_io)3636 static int sunxi_get_udc_resource(struct platform_device *pdev,
3637 sunxi_udc_io_t *sunxi_udc_io)
3638 {
3639 int retval = 0;
3640
3641 memset(&g_sunxi_udc_io, 0, sizeof(sunxi_udc_io_t));
3642
3643 retval = sunxi_get_udc_base(pdev, sunxi_udc_io);
3644 if (retval != 0) {
3645 dev_err(&pdev->dev, "can't get udc base\n");
3646 goto err0;
3647 }
3648
3649 retval = sunxi_get_udc_clock(pdev, sunxi_udc_io);
3650 if (retval != 0) {
3651 dev_err(&pdev->dev, "can't get udc clock\n");
3652 goto err0;
3653 }
3654
3655 charger_mode = of_property_read_bool(pdev->dev.of_node, "charger_mode");
3656
3657 return 0;
3658 err0:
3659 return retval;
3660
3661 }
3662
3663 static ssize_t
udc_reg_show(struct class * class,struct class_attribute * attr,char * buf)3664 udc_reg_show(struct class *class, struct class_attribute *attr, char *buf)
3665 {
3666 struct resource res;
3667
3668 of_address_to_resource(sunxi_udc.pdev->dev.of_node, 0, &res);
3669 DMSG_INFO("usbc%d, udc, base[0x%08x]:\n",
3670 0, (unsigned int)res.start);
3671 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 4, 4,
3672 g_sunxi_udc_io.usb_vbase, 0x98, false);
3673
3674 DMSG_INFO("usbc%d, udc phy, base[0x%08x]:\n",
3675 0, (unsigned int)(res.start + SUNXI_UDC_TEST_PACKET));
3676 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 4, 4,
3677 (g_sunxi_udc_io.usb_vbase + SUNXI_UDC_TEST_PACKET), 0x200, false);
3678 DMSG_INFO("\n");
3679
3680 return 0;
3681 }
3682
3683 static ssize_t
udc_reg_store(struct class * class,struct class_attribute * attr,const char * buf,size_t size)3684 udc_reg_store(struct class *class, struct class_attribute *attr, const char *buf, size_t size)
3685 {
3686 return 0;
3687 }
3688 static CLASS_ATTR_RW(udc_reg);
3689
3690 static struct attribute *udc_reg_class_attrs[] = {
3691 &class_attr_udc_reg.attr,
3692 NULL,
3693 };
3694 ATTRIBUTE_GROUPS(udc_reg_class);
3695
3696 static struct class udc_reg_class = {
3697 .name = "udc_reg",
3698 .owner = THIS_MODULE,
3699 .class_groups = udc_reg_class_groups,
3700 };
3701
3702 static const struct of_device_id sunxi_udc_match[] = {
3703 {.compatible = "allwinner,sunxi-udc", },
3704 {},
3705 };
3706 MODULE_DEVICE_TABLE(of, sunxi_udc_match);
3707
sunxi_udc_probe_otg(struct platform_device * pdev)3708 static int sunxi_udc_probe_otg(struct platform_device *pdev)
3709 {
3710 struct sunxi_udc *udc = &sunxi_udc;
3711 int retval = 0;
3712
3713 g_udc_pdev = pdev;
3714
3715 spin_lock_init(&udc->lock);
3716
3717 if (!sunxi_udc_is_enable(pdev)) {
3718 DMSG_INFO("sunxi udc is no enable\n");
3719 return -ENODEV;
3720 }
3721
3722 udc->gadget.dev.parent = &pdev->dev;
3723
3724 #if IS_ENABLED(CONFIG_OF)
3725 udc->gadget.dev.dma_mask = &sunxi_udc_mask;
3726 udc->gadget.dev.coherent_dma_mask = DMA_BIT_MASK(64);
3727 #endif
3728 retval = sunxi_get_udc_resource(pdev, &g_sunxi_udc_io);
3729 if (retval != 0) {
3730 DMSG_PANIC("ERR: sunxi_get_udc_resource, is fail\n");
3731 return -ENODEV;
3732 }
3733
3734 sunxi_udc_io_init(usbd_port_no, &g_sunxi_udc_io);
3735
3736 sunxi_udc_reinit(udc);
3737
3738 the_controller = udc;
3739
3740 platform_set_drvdata(pdev, udc);
3741
3742 retval = usb_add_gadget_udc(&pdev->dev, &udc->gadget);
3743 if (retval != 0) {
3744 dev_err(&pdev->dev, "can't usb_add_gadget_udc\n");
3745 return retval;
3746 }
3747
3748 udc->gadget.max_speed = USB_SPEED_HIGH;
3749
3750 retval = class_register(&udc_reg_class);
3751 if (retval) {
3752 dev_err(&pdev->dev, "register class fialed\n");
3753 return retval ;
3754 }
3755
3756 device_create_file(&pdev->dev, &dev_attr_otg_ed_test);
3757 device_create_file(&pdev->dev, &dev_attr_otg_phy_range);
3758 device_create_file(&pdev->dev, &dev_attr_queue_debug);
3759 device_create_file(&pdev->dev, &dev_attr_dma_debug);
3760 device_create_file(&pdev->dev, &dev_attr_write_debug);
3761 device_create_file(&pdev->dev, &dev_attr_read_debug);
3762 device_create_file(&pdev->dev, &dev_attr_irq_debug);
3763 device_create_file(&pdev->dev, &dev_attr_msc_read_debug);
3764 device_create_file(&pdev->dev, &dev_attr_msc_write_debug);
3765
3766 #if !IS_ENABLED(CONFIG_USB_SUNXI_USB_MANAGER)
3767 sunxi_usb_device_enable();
3768 #endif
3769 pr_debug("usb_connecting: init wake lock.\n");
3770 if (!charger_mode) {
3771 udc->ws = wakeup_source_register(&pdev->dev, "usb_connecting");
3772 }
3773 return 0;
3774
3775 }
3776
sunxi_udc_remove_otg(struct platform_device * pdev)3777 static int sunxi_udc_remove_otg(struct platform_device *pdev)
3778 {
3779 struct sunxi_udc *udc = NULL;
3780
3781 udc = platform_get_drvdata(pdev);
3782
3783 #if !IS_ENABLED(CONFIG_USB_SUNXI_USB_MANAGER)
3784 sunxi_usb_device_disable();
3785 #endif
3786
3787 device_remove_file(&pdev->dev, &dev_attr_otg_ed_test);
3788 device_remove_file(&pdev->dev, &dev_attr_otg_phy_range);
3789 device_remove_file(&pdev->dev, &dev_attr_queue_debug);
3790 device_remove_file(&pdev->dev, &dev_attr_dma_debug);
3791 device_remove_file(&pdev->dev, &dev_attr_write_debug);
3792 device_remove_file(&pdev->dev, &dev_attr_read_debug);
3793 device_remove_file(&pdev->dev, &dev_attr_irq_debug);
3794 device_remove_file(&pdev->dev, &dev_attr_msc_read_debug);
3795 device_remove_file(&pdev->dev, &dev_attr_msc_write_debug);
3796
3797 if (!charger_mode)
3798 wakeup_source_unregister(udc->ws);
3799
3800 class_unregister(&udc_reg_class);
3801
3802 g_udc_pdev = NULL;
3803
3804 usb_del_gadget_udc(&udc->gadget);
3805
3806 sunxi_udc_io_exit(&g_sunxi_udc_io);
3807 memset(&g_sunxi_udc_io, 0, sizeof(sunxi_udc_io_t));
3808
3809 return 0;
3810 }
3811
sunxi_udc_probe(struct platform_device * pdev)3812 static int sunxi_udc_probe(struct platform_device *pdev)
3813 {
3814 return sunxi_udc_probe_otg(pdev);
3815 }
3816
sunxi_udc_remove(struct platform_device * pdev)3817 static int sunxi_udc_remove(struct platform_device *pdev)
3818 {
3819 return sunxi_udc_remove_otg(pdev);
3820 }
3821
3822 #if IS_ENABLED(CONFIG_PM)
sunxi_udc_suspend(struct device * dev)3823 static int sunxi_udc_suspend(struct device *dev)
3824 {
3825 struct sunxi_udc *udc = the_controller;
3826
3827 DMSG_INFO_UDC("sunxi_udc_suspend start\n");
3828
3829 if (udc == NULL) {
3830 DMSG_INFO_UDC("udc is NULL, need not enter to suspend\n");
3831 return 0;
3832 }
3833
3834 if (!is_peripheral_active()) {
3835 DMSG_INFO("udc is disable, need not enter to suspend\n");
3836 return 0;
3837 }
3838
3839 /* soft disconnect */
3840 cfg_udc_command(SW_UDC_P_DISABLE);
3841
3842 /* disable usb controller */
3843 sunxi_udc_disable(udc);
3844
3845 /* close USB clock */
3846 close_usb_clock(&g_sunxi_udc_io);
3847
3848 DMSG_INFO_UDC("sunxi_udc_suspend end\n");
3849 return 0;
3850 }
3851
sunxi_udc_resume(struct device * dev)3852 static int sunxi_udc_resume(struct device *dev)
3853 {
3854 struct sunxi_udc *udc = the_controller;
3855 #if defined(CONFIG_ARCH_SUN50IW10)
3856 int val;
3857 #endif
3858
3859 DMSG_INFO_UDC("sunxi_udc_resume start\n");
3860
3861 if (udc == NULL) {
3862 DMSG_INFO_UDC("udc is NULL, need not enter to suspend\n");
3863 return 0;
3864 }
3865
3866 if (!is_peripheral_active()) {
3867 DMSG_INFO("udc is disable, need not enter to resume\n");
3868 return 0;
3869 }
3870
3871 #if defined(CONFIG_ARCH_SUN50IW10)
3872 /*phy reg, offset:0x10 bit3 set 0, enable siddq*/
3873 val = USBC_Readl(g_sunxi_udc_io.usb_common_phy_config + SUNXI_HCI_PHY_CTRL);
3874 val &= ~(0x1 << SUNXI_HCI_PHY_CTRL_SIDDQ);
3875 USBC_Writel(val, g_sunxi_udc_io.usb_common_phy_config + SUNXI_HCI_PHY_CTRL);
3876 #endif
3877
3878 sunxi_udc_bsp_init(&g_sunxi_udc_io);
3879 if (is_udc_enable) {
3880
3881 if (udc->driver && udc->driver->disconnect)
3882 udc->driver->disconnect(&udc->gadget);
3883
3884 /* enable usb controller */
3885 sunxi_udc_enable(udc);
3886
3887 /* soft connect */
3888 cfg_udc_command(SW_UDC_P_ENABLE);
3889 }
3890
3891 DMSG_INFO_UDC("sunxi_udc_resume end\n");
3892 return 0;
3893 }
3894 static const struct dev_pm_ops sunxi_udc_pm_ops = {
3895 .suspend = sunxi_udc_suspend,
3896 .resume = sunxi_udc_resume,
3897 };
3898
3899 #define UDC_PM_OPS (&sunxi_udc_pm_ops)
3900
3901 #else /* !CONFIG_PM */
3902
3903 #define UDC_PM_OPS NULL
3904 #endif /* CONFIG_PM */
3905
3906 static struct platform_driver sunxi_udc_driver = {
3907 .driver = {
3908 .name = (char *)gadget_name,
3909 .pm = UDC_PM_OPS,
3910 .bus = &platform_bus_type,
3911 .owner = THIS_MODULE,
3912 .of_match_table = sunxi_udc_match,
3913 },
3914
3915 .probe = sunxi_udc_probe,
3916 .remove = sunxi_udc_remove,
3917 };
3918
cfg_udc_command(enum sunxi_udc_cmd_e cmd)3919 static void cfg_udc_command(enum sunxi_udc_cmd_e cmd)
3920 {
3921 struct sunxi_udc *udc = the_controller;
3922
3923 switch (cmd) {
3924 case SW_UDC_P_ENABLE:
3925 {
3926 if (udc->driver)
3927 usbd_start_work();
3928 else
3929 DMSG_INFO_UDC("udc->driver is null, ");
3930 DMSG_INFO_UDC("udc is need not start\n");
3931 }
3932 break;
3933 case SW_UDC_P_DISABLE:
3934 {
3935 if (udc->driver)
3936 usbd_stop_work();
3937 else
3938 DMSG_INFO_UDC("udc->driver is null, ");
3939 DMSG_INFO_UDC("udc is need not stop\n");
3940 }
3941 break;
3942 case SW_UDC_P_RESET:
3943 DMSG_PANIC("ERR: reset is not support\n");
3944 break;
3945 default:
3946 DMSG_PANIC("ERR: unknown cmd(%d)\n", cmd);
3947 break;
3948 }
3949 }
3950
cfg_vbus_draw(unsigned int ma)3951 static void cfg_vbus_draw(unsigned int ma)
3952 {
3953 }
3954
udc_init(void)3955 static int udc_init(void)
3956 {
3957 int retval = 0;
3958 usb_connect = 0;
3959
3960 /* driver register */
3961 retval = platform_driver_register(&sunxi_udc_driver);
3962 if (retval) {
3963 DMSG_PANIC("ERR: platform_driver_register failed\n");
3964 retval = -1;
3965 goto err;
3966 }
3967
3968 return 0;
3969
3970 err:
3971 return retval;
3972 }
3973
udc_exit(void)3974 static void udc_exit(void)
3975 {
3976 platform_driver_unregister(&sunxi_udc_driver);
3977 }
3978
3979 fs_initcall(udc_init);
3980 module_exit(udc_exit);
3981
3982 MODULE_AUTHOR(DRIVER_AUTHOR);
3983 MODULE_DESCRIPTION(DRIVER_DESC);
3984 MODULE_VERSION("1.0.14");
3985 MODULE_LICENSE("GPL v2");
3986 MODULE_ALIAS("platform:softwinner-usbgadget");
3987