1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2019 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 #ifndef __DRV_TYPES_SDIO_H__ 16 #define __DRV_TYPES_SDIO_H__ 17 18 /* SDIO Header Files */ 19 #ifdef PLATFORM_LINUX 20 #include <linux/mmc/sdio_func.h> 21 #include <linux/mmc/sdio_ids.h> 22 #include <linux/mmc/host.h> 23 #include <linux/mmc/card.h> 24 25 #ifdef CONFIG_PLATFORM_SPRD 26 #include <linux/gpio.h> 27 #include <custom_gpio.h> 28 #endif /* CONFIG_PLATFORM_SPRD */ 29 #endif 30 31 #define RTW_SDIO_CLK_33M 33000000 32 #define RTW_SDIO_CLK_40M 40000000 33 #define RTW_SDIO_CLK_80M 80000000 34 #define RTW_SDIO_CLK_160M 160000000 35 36 typedef struct sdio_data { 37 u8 func_number; 38 39 u8 tx_block_mode; 40 u8 rx_block_mode; 41 u32 block_transfer_len; 42 43 #ifdef PLATFORM_LINUX 44 struct mmc_card *card; 45 struct sdio_func *func; 46 _thread_hdl_ sys_sdio_irq_thd; 47 unsigned int clock; 48 unsigned int timing; 49 u8 sd3_bus_mode; 50 #endif 51 52 #ifdef DBG_SDIO 53 #ifdef PLATFORM_LINUX 54 struct proc_dir_entry *proc_sdio_dbg; 55 #endif /* PLATFORM_LINUX */ 56 57 u32 cmd52_err_cnt; /* CMD52 I/O error count */ 58 u32 cmd53_err_cnt; /* CMD53 I/O error count */ 59 60 #if (DBG_SDIO >= 1) 61 u32 reg_dump_mark; /* reg dump at specific error count */ 62 #endif /* DBG_SDIO >= 1 */ 63 64 #if (DBG_SDIO >= 2) 65 u8 *dbg_msg; /* Messages for debug */ 66 u8 dbg_msg_size; 67 u8 *reg_mac; /* Device MAC register, 0x0~0x800 */ 68 u8 *reg_mac_ext; /* Device MAC extend register, 0x1000~0x1800 */ 69 u8 *reg_local; /* Device SDIO local register, 0x0~0xFF */ 70 u8 *reg_cia; /* SDIO CIA(CCCR, FBR and etc.), 0x0~0x1FF */ 71 #endif /* DBG_SDIO >= 2 */ 72 73 #if (DBG_SDIO >= 3) 74 u8 dbg_enable; /* 0/1: disable/enable debug mode */ 75 u8 err_stop; /* Stop(surprise remove) when I/O error happen */ 76 u8 err_test; /* Simulate error happen */ 77 u8 err_test_triggered; /* Simulate error already triggered */ 78 #endif /* DBG_SDIO >= 3 */ 79 #endif /* DBG_SDIO */ 80 } SDIO_DATA, *PSDIO_DATA; 81 82 #define dvobj_to_sdio_func(d) ((d)->intf_data.func) 83 84 #define RTW_SDIO_ADDR_CMD52_BIT (1<<17) 85 #define RTW_SDIO_ADDR_CMD52_GEN(a) (a | RTW_SDIO_ADDR_CMD52_BIT) 86 #define RTW_SDIO_ADDR_CMD52_CLR(a) (a&~RTW_SDIO_ADDR_CMD52_BIT) 87 #define RTW_SDIO_ADDR_CMD52_CHK(a) (a&RTW_SDIO_ADDR_CMD52_BIT ? 1 : 0) 88 89 #define RTW_SDIO_ADDR_F0_BIT (1<<18) 90 #define RTW_SDIO_ADDR_F0_GEN(a) (a | RTW_SDIO_ADDR_F0_BIT) 91 #define RTW_SDIO_ADDR_F0_CLR(a) (a&~RTW_SDIO_ADDR_F0_BIT) 92 #define RTW_SDIO_ADDR_F0_CHK(a) (a&RTW_SDIO_ADDR_F0_BIT ? 1 : 0) 93 94 #endif 95