1 // Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #include "esp_efuse_utility.h"
16 #include "soc/efuse_periph.h"
17 #include "esp32/clk.h"
18 #include "esp_log.h"
19 #include "assert.h"
20 #include "sdkconfig.h"
21 #include <sys/param.h>
22
23 static const char *TAG = "efuse";
24
25 #ifdef CONFIG_EFUSE_VIRTUAL
26 extern uint32_t virt_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK];
27 #endif // CONFIG_EFUSE_VIRTUAL
28
29 /*Range addresses to read blocks*/
30 const esp_efuse_range_addr_t range_read_addr_blocks[] = {
31 {EFUSE_BLK0_RDATA0_REG, EFUSE_BLK0_RDATA6_REG}, // range address of EFUSE_BLK0
32 {EFUSE_BLK1_RDATA0_REG, EFUSE_BLK1_RDATA7_REG}, // range address of EFUSE_BLK1
33 {EFUSE_BLK2_RDATA0_REG, EFUSE_BLK2_RDATA7_REG}, // range address of EFUSE_BLK2
34 {EFUSE_BLK3_RDATA0_REG, EFUSE_BLK3_RDATA7_REG} // range address of EFUSE_BLK3
35 };
36
37 /*Range addresses to write blocks*/
38 const esp_efuse_range_addr_t range_write_addr_blocks[] = {
39 {EFUSE_BLK0_WDATA0_REG, EFUSE_BLK0_WDATA6_REG}, // range address of EFUSE_BLK0
40 {EFUSE_BLK1_WDATA0_REG, EFUSE_BLK1_WDATA7_REG}, // range address of EFUSE_BLK1
41 {EFUSE_BLK2_WDATA0_REG, EFUSE_BLK2_WDATA7_REG}, // range address of EFUSE_BLK2
42 {EFUSE_BLK3_WDATA0_REG, EFUSE_BLK3_WDATA7_REG} // range address of EFUSE_BLK3
43 };
44
45 #define EFUSE_CONF_WRITE 0x5A5A /* eFuse_pgm_op_ena, force no rd/wr disable. */
46 #define EFUSE_CONF_READ 0x5AA5 /* eFuse_read_op_ena, release force. */
47 #define EFUSE_CMD_PGM 0x02 /* Command to program. */
48 #define EFUSE_CMD_READ 0x01 /* Command to read. */
49
50 #ifndef CONFIG_EFUSE_VIRTUAL
51 // Update Efuse timing configuration
esp_efuse_set_timing(void)52 static esp_err_t esp_efuse_set_timing(void)
53 {
54 uint32_t apb_freq_mhz = esp_clk_apb_freq() / 1000000;
55 uint32_t clk_sel0, clk_sel1, dac_clk_div;
56 if (apb_freq_mhz <= 26) {
57 clk_sel0 = 250;
58 clk_sel1 = 255;
59 dac_clk_div = 52;
60 } else if (apb_freq_mhz <= 40) {
61 clk_sel0 = 160;
62 clk_sel1 = 255;
63 dac_clk_div = 80;
64 } else {
65 clk_sel0 = 80;
66 clk_sel1 = 128;
67 dac_clk_div = 100;
68 }
69 REG_SET_FIELD(EFUSE_DAC_CONF_REG, EFUSE_DAC_CLK_DIV, dac_clk_div);
70 REG_SET_FIELD(EFUSE_CLK_REG, EFUSE_CLK_SEL0, clk_sel0);
71 REG_SET_FIELD(EFUSE_CLK_REG, EFUSE_CLK_SEL1, clk_sel1);
72 return ESP_OK;
73 }
74 #endif // ifndef CONFIG_EFUSE_VIRTUAL
75
76 // Efuse read operation: copies data from physical efuses to efuse read registers.
esp_efuse_utility_clear_program_registers(void)77 void esp_efuse_utility_clear_program_registers(void)
78 {
79 REG_WRITE(EFUSE_CONF_REG, EFUSE_CONF_READ);
80 }
81
82 // Burn values written to the efuse write registers
esp_efuse_utility_burn_efuses(void)83 void esp_efuse_utility_burn_efuses(void)
84 {
85 #ifdef CONFIG_EFUSE_VIRTUAL
86 ESP_LOGW(TAG, "Virtual efuses enabled: Not really burning eFuses");
87 for (int num_block = EFUSE_BLK0; num_block < EFUSE_BLK_MAX; num_block++) {
88 esp_efuse_coding_scheme_t scheme = esp_efuse_get_coding_scheme(num_block);
89 if (scheme == EFUSE_CODING_SCHEME_3_4) {
90 uint8_t buf[COUNT_EFUSE_REG_PER_BLOCK * 4] = { 0 };
91 int i = 0;
92 for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4, ++i) {
93 *((uint32_t*)buf + i) = REG_READ(addr_wr_block);
94 }
95 int j = 0;
96 uint32_t out_buf[COUNT_EFUSE_REG_PER_BLOCK] = { 0 };
97 for (int k = 0; k < 4; ++k, ++j) {
98 memcpy((uint8_t*)out_buf + j * 6, &buf[k * 8], 6);
99 }
100 for (int k = 0; k < COUNT_EFUSE_REG_PER_BLOCK; ++k) {
101 REG_WRITE(range_write_addr_blocks[num_block].start + k * 4, out_buf[k]);
102 }
103 }
104 int subblock = 0;
105 for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
106 virt_blocks[num_block][subblock++] |= REG_READ(addr_wr_block);
107 }
108 }
109 #else
110 esp_efuse_set_timing();
111 // Permanently update values written to the efuse write registers
112 REG_WRITE(EFUSE_CONF_REG, EFUSE_CONF_WRITE);
113 REG_WRITE(EFUSE_CMD_REG, EFUSE_CMD_PGM);
114 while (REG_READ(EFUSE_CMD_REG) != 0) {};
115 REG_WRITE(EFUSE_CONF_REG, EFUSE_CONF_READ);
116 REG_WRITE(EFUSE_CMD_REG, EFUSE_CMD_READ);
117 while (REG_READ(EFUSE_CMD_REG) != 0) {};
118 #endif // CONFIG_EFUSE_VIRTUAL
119 esp_efuse_utility_reset();
120 }
121
esp_efuse_utility_apply_34_encoding(const uint8_t * in_bytes,uint32_t * out_words,size_t in_bytes_len)122 esp_err_t esp_efuse_utility_apply_34_encoding(const uint8_t *in_bytes, uint32_t *out_words, size_t in_bytes_len)
123 {
124 if (in_bytes == NULL || out_words == NULL || in_bytes_len % 6 != 0) {
125 return ESP_ERR_INVALID_ARG;
126 }
127
128 while (in_bytes_len > 0) {
129 uint8_t out[8];
130 uint8_t xor = 0;
131 uint8_t mul = 0;
132 for (int i = 0; i < 6; i++) {
133 xor ^= in_bytes[i];
134 mul += (i + 1) * __builtin_popcount(in_bytes[i]);
135 }
136
137 memcpy(out, in_bytes, 6); // Data bytes
138 out[6] = xor;
139 out[7] = mul;
140
141 memcpy(out_words, out, 8);
142
143 in_bytes_len -= 6;
144 in_bytes += 6;
145 out_words += 2;
146 }
147
148 return ESP_OK;
149 }
150
read_w_data_and_check_fill(esp_efuse_block_t num_block,uint32_t * buf_w_data)151 static bool read_w_data_and_check_fill(esp_efuse_block_t num_block, uint32_t *buf_w_data)
152 {
153 bool blk_is_filled = false;
154 int i = 0;
155 for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4, ++i) {
156 buf_w_data[i] = REG_READ(addr_wr_block);
157 if (buf_w_data[i] != 0) {
158 REG_WRITE(addr_wr_block, 0);
159 blk_is_filled = true;
160 }
161 }
162 return blk_is_filled;
163 }
164
read_r_data(esp_efuse_block_t num_block,uint32_t * buf_r_data)165 static void read_r_data(esp_efuse_block_t num_block, uint32_t* buf_r_data)
166 {
167 int i = 0;
168 for (uint32_t addr_rd_block = range_read_addr_blocks[num_block].start; addr_rd_block <= range_read_addr_blocks[num_block].end; addr_rd_block += 4, ++i) {
169 buf_r_data[i] = esp_efuse_utility_read_reg(num_block, i);
170 }
171 }
172
173 // After esp_efuse_write.. functions EFUSE_BLKx_WDATAx_REG were filled is not coded values.
174 // This function reads EFUSE_BLKx_WDATAx_REG registers, applies coding scheme and writes encoded values back to EFUSE_BLKx_WDATAx_REG.
esp_efuse_utility_apply_new_coding_scheme()175 esp_err_t esp_efuse_utility_apply_new_coding_scheme()
176 {
177 uint8_t buf_w_data[COUNT_EFUSE_REG_PER_BLOCK * 4];
178 uint8_t buf_r_data[COUNT_EFUSE_REG_PER_BLOCK * 4];
179 uint32_t reg[COUNT_EFUSE_REG_PER_BLOCK];
180 // start with EFUSE_BLK1. EFUSE_BLK0 - always uses EFUSE_CODING_SCHEME_NONE.
181 for (int num_block = EFUSE_BLK1; num_block < EFUSE_BLK_MAX; num_block++) {
182 esp_efuse_coding_scheme_t scheme = esp_efuse_get_coding_scheme(num_block);
183 // check and apply a new coding scheme.
184 if (scheme != EFUSE_CODING_SCHEME_NONE) {
185 memset(buf_w_data, 0, sizeof(buf_w_data));
186 memset((uint8_t*)reg, 0, sizeof(reg));
187 if (read_w_data_and_check_fill(num_block, (uint32_t*)buf_w_data) == true) {
188 read_r_data(num_block, (uint32_t*)buf_r_data);
189 if (scheme == EFUSE_CODING_SCHEME_3_4) {
190 if (*((uint32_t*)buf_w_data + 6) != 0 || *((uint32_t*)buf_w_data + 7) != 0) {
191 return ESP_ERR_CODING;
192 }
193 for (int i = 0; i < 24; ++i) {
194 if (buf_w_data[i] != 0) {
195 int st_offset_buf = (i / 6) * 6;
196 // check that place is free.
197 for (int n = st_offset_buf; n < st_offset_buf + 6; ++n) {
198 if (buf_r_data[n] != 0) {
199 ESP_LOGE(TAG, "Bits are not empty. Write operation is forbidden.");
200 return ESP_ERR_CODING;
201 }
202 }
203
204 esp_err_t err = esp_efuse_utility_apply_34_encoding(&buf_w_data[st_offset_buf], reg, 6);
205 if (err != ESP_OK) {
206 return err;
207 }
208
209 int num_reg = (st_offset_buf / 6) * 2;
210 for (int r = 0; r < 2; r++) {
211 REG_WRITE(range_write_addr_blocks[num_block].start + (num_reg + r) * 4, reg[r]);
212 }
213 i = st_offset_buf + 5;
214 }
215 }
216 } else if (scheme == EFUSE_CODING_SCHEME_REPEAT) {
217 uint32_t* buf_32 = (uint32_t*)buf_w_data;
218 for (int i = 4; i < 8; ++i) {
219 if (*(buf_32 + i) != 0) {
220 return ESP_ERR_CODING;
221 }
222 }
223 for (int i = 0; i < 4; ++i) {
224 if (buf_32[i] != 0) {
225 REG_WRITE(range_write_addr_blocks[num_block].start + i * 4, buf_32[i]);
226 REG_WRITE(range_write_addr_blocks[num_block].start + (i + 4) * 4, buf_32[i]);
227 }
228 }
229 }
230 }
231 }
232 }
233 return ESP_OK;
234 }
235