1 /*
2 // Copyright (C) 2022 Beken Corporation
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15 #include <common/bk_include.h>
16 #include "bk_arm_arch.h"
17 #include <common/sys_config.h>
18 #include "flash.h"
19 #include "sys_ctrl.h"
20 #include "bk_flash.h"
21 #include "bk_drv_model.h"
22 #include <string.h>
23 #include "bk_uart.h"
24 #include "bk_sys_ctrl.h"
25 #include "bk_mcu_ps.h"
26 #include <os/mem.h>
27 #include <components/log.h>
28 #include <components/ate.h>
29 #include "bk_pm_model.h"
30 #include "sys_driver.h"
31 #include "flash_bypass.h"
32
33 #define TAG "flash"
34
35 static const flash_config_t flash_config[] = {
36 {0x1C7016, 1, 0x400000, 2, 0, 2, 0x1F, 0x1F, 0x00, 0x16, 0x01B, 0, 0, 0xA5, 0x01}, //en_25qh32b
37 {0x1C7015, 1, 0x200000, 2, 0, 2, 0x1F, 0x1F, 0x00, 0x0d, 0x0d, 0, 0, 0xA5, 0x01}, //en_25qh16b
38 {0x0B4014, 2, 0x100000, 2, 14, 2, 0x1F, 0x1F, 0x00, 0x0C, 0x101, 9, 1, 0xA0, 0x01}, //xtx_25f08b
39 {0x0B4015, 2, 0x200000, 2, 14, 2, 0x1F, 0x1F, 0x00, 0x0D, 0x101, 9, 1, 0xA0, 0x01}, //xtx_25f16b
40 #if CONFIG_FLASH_QUAD_ENABLE
41 {0x0B4016, 2, 0x400000, 4, 14, 2, 0x1F, 0x1F, 0x00, 0x0E, 0x101, 9, 1, 0xA0, 0x02}, //xtx_25f32b
42 #else
43 {0x0B4016, 2, 0x400000, 2, 14, 2, 0x1F, 0x1F, 0x00, 0x0E, 0x101, 9, 1, 0xA0, 0x01}, //xtx_25f32b
44 #endif
45 {0x0B4017, 2, 0x800000, 2, 14, 2, 0x1F, 0x05, 0x00, 0x0E, 0x109, 9, 1, 0xA0, 0x01}, //xtx_25f64b
46 {0x0E4016, 2, 0x400000, 2, 14, 2, 0x1F, 0x1F, 0x00, 0x0E, 0x101, 9, 1, 0xA0, 0x01}, //xtx_FT25H32
47 {0xC84015, 2, 0x200000, 2, 14, 2, 0x1F, 0x1F, 0x00, 0x0D, 0x101, 9, 1, 0xA0, 0x01}, //gd_25q16c
48 #if CONFIG_FLASH_QUAD_ENABLE
49 {0xC84016, 2, 0x400000, 4, 14, 2, 0x1F, 0x1F, 0x00, 0x0E, 0x00E, 9, 1, 0xA0, 0x02}, //gd_25q32c
50 #else
51 {0xC84016, 1, 0x400000, 2, 0, 2, 0x1F, 0x1F, 0x00, 0x0E, 0x00E, 0, 0, 0xA0, 0x01}, //gd_25q32c
52 #endif
53 {0xC86515, 2, 0x200000, 2, 14, 2, 0x1F, 0x1F, 0x00, 0x0D, 0x101, 9, 1, 0xA0, 0x01}, //gd_25w16e
54 {0xEF4016, 2, 0x400000, 2, 14, 2, 0x1F, 0x1F, 0x00, 0x00, 0x101, 9, 1, 0xA0, 0x01}, //w_25q32(bfj)
55 {0x204016, 2, 0x400000, 2, 14, 2, 0x1F, 0x1F, 0x00, 0x0E, 0x101, 9, 1, 0xA0, 0x01}, //xmc_25qh32b
56 {0xC22315, 1, 0x200000, 2, 0, 2, 0x0F, 0x0F, 0x00, 0x0A, 0x00E, 6, 1, 0xA5, 0x01}, //mx_25v16b
57 {0xEB6015, 2, 0x200000, 2, 14, 2, 0x1F, 0x1F, 0x00, 0x0D, 0x101, 9, 1, 0xA0, 0x01}, //zg_th25q16b
58 {0x000000, 2, 0x400000, 2, 0, 2, 0x1F, 0x00, 0x00, 0x00, 0x000, 0, 0, 0x00, 0x01}, //default
59 };
60
61 __maybe_unused static void flash_enable_cpu_data_wr(void);
62 static const flash_config_t *flash_current_config = NULL;
63 static UINT32 flash_id;
64 static const DD_OPERATIONS flash_op = {
65 NULL,
66 NULL,
67 flash_read,
68 flash_write,
69 flash_ctrl
70 };
71
flash_get_current_flash_config(void)72 static void flash_get_current_flash_config(void)
73 {
74 int i;
75
76 for (i = 0; i < (sizeof(flash_config) / sizeof(flash_config_t) - 1); i++) {
77 if (flash_id == flash_config[i].flash_id) {
78 flash_current_config = &flash_config[i];
79 break;
80 }
81 }
82
83 if (i == (sizeof(flash_config) / sizeof(flash_config_t) - 1)) {
84 flash_current_config = &flash_config[i];
85 BK_LOGI(TAG, "don't config this flash, choose default config\r\n");
86 }
87 }
88
flash_set_clk(UINT8 clk_conf)89 static void flash_set_clk(UINT8 clk_conf)
90 {
91 UINT32 value;
92
93 #if CONFIG_FLASH_SRC_CLK_60M
94 sys_drv_flash_set_clk_div(FLASH_DPLL_DIV_VALUE_TEN);
95 sys_drv_flash_set_dco();
96 #endif
97
98 value = REG_READ(REG_FLASH_CONF);
99 value &= ~(FLASH_CLK_CONF_MASK << FLASH_CLK_CONF_POSI);
100 value |= (clk_conf << FLASH_CLK_CONF_POSI);
101
102 #if CONFIG_JTAG
103 value &= ~(CRC_EN);
104 #endif
105
106 REG_WRITE(REG_FLASH_CONF, value);
107 }
108
flash_enable_cpu_data_wr(void)109 static void flash_enable_cpu_data_wr(void)
110 {
111 UINT32 value;
112
113 value = REG_READ(REG_FLASH_CONF);
114 value |= (CPU_DATA_WR_MASK << CPU_DATA_WR_POSI);
115 REG_WRITE(REG_FLASH_CONF, value);
116 }
117
118 #if (0 == CONFIG_JTAG)
flash_disable_cpu_data_wr(void)119 static void flash_disable_cpu_data_wr(void)
120 {
121 UINT32 value;
122
123 value = REG_READ(REG_FLASH_CONF);
124 value &= (~(CPU_DATA_WR_MASK << CPU_DATA_WR_POSI));
125
126 REG_WRITE(REG_FLASH_CONF, value);
127 }
128 #endif
129
flash_write_enable(void)130 static void flash_write_enable(void)
131 {
132 UINT32 value;
133
134 value = (FLASH_OPCODE_WREN << OP_TYPE_SW_POSI) | OP_SW | WP_VALUE;
135 REG_WRITE(REG_FLASH_OPERATE_SW, value);
136
137 while (REG_READ(REG_FLASH_OPERATE_SW) & BUSY_SW);
138 }
139
flash_write_disable(void)140 static void flash_write_disable(void)
141 {
142 UINT32 value;
143
144 value = (FLASH_OPCODE_WRDI << OP_TYPE_SW_POSI) | OP_SW | WP_VALUE;
145 REG_WRITE(REG_FLASH_OPERATE_SW, value);
146 while (REG_READ(REG_FLASH_OPERATE_SW) & BUSY_SW);
147 }
148
149 #define WRSR_CMD_MASK 0xff
150 #define WRSR_CMD_SEL 0x1
151 #define WRSR_CMD_POSI 16
152 #define WRSR_CMD_S0_S7 0x1
153 #define WRSR_CMD_S8_S15 0x31
154
flash_init_wrsr_cmd(uint8_t wrsr_cmd)155 void flash_init_wrsr_cmd(uint8_t wrsr_cmd)
156 {
157 uint32_t value;
158
159 value = REG_READ(REG_FLASH_SR_CMD);
160 value &= (~(WRSR_CMD_MASK));
161 value |= ((wrsr_cmd) | (WRSR_CMD_SEL << WRSR_CMD_POSI));
162 REG_WRITE(REG_FLASH_SR_CMD, value);
163
164 while (REG_READ(REG_FLASH_OPERATE_SW) & BUSY_SW);
165 }
166
flash_deinit_wrsr_cmd(void)167 void flash_deinit_wrsr_cmd(void)
168 {
169 uint32_t value;
170
171 value = REG_READ(REG_FLASH_SR_CMD);
172 value &= (~((WRSR_CMD_SEL << WRSR_CMD_POSI) | WRSR_CMD_MASK));
173 value |= (WRSR_CMD_S0_S7);
174 REG_WRITE(REG_FLASH_SR_CMD, value);
175
176 while (REG_READ(REG_FLASH_OPERATE_SW) & BUSY_SW);
177 }
178 #endif
179
flash_read_sr(UINT8 sr_width)180 UINT16 flash_read_sr(UINT8 sr_width)
181 {
182 UINT16 sr;
183 UINT32 value;
184
185 while (REG_READ(REG_FLASH_OPERATE_SW) & BUSY_SW);
186
187 value = (FLASH_OPCODE_RDSR << OP_TYPE_SW_POSI) | OP_SW | WP_VALUE;
188 REG_WRITE(REG_FLASH_OPERATE_SW, value);
189 while (REG_READ(REG_FLASH_OPERATE_SW) & BUSY_SW);
190
191 value = REG_READ(REG_FLASH_SR_DATA_CRC_CNT);
192 sr = value & 0x00FF;
193
194 if (sr_width == 2) {
195 value = (FLASH_OPCODE_RDSR2 << OP_TYPE_SW_POSI) | OP_SW | WP_VALUE;
196 REG_WRITE(REG_FLASH_OPERATE_SW, value);
197 while (REG_READ(REG_FLASH_OPERATE_SW) & BUSY_SW);
198
199 value = REG_READ(REG_FLASH_SR_DATA_CRC_CNT);
200 sr |= (value & 0x00FF) << 8;
201 }
202
203 BK_LOGD(TAG, "--read sr:%x--\r\n",sr);
204
205 return sr;
206 }
207
flash_write_sr(UINT8 sr_width,UINT16 val)208 static void flash_write_sr(UINT8 sr_width, UINT16 val)
209 {
210 UINT32 value;
211
212 #if (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A) || (CONFIG_SOC_BK7256XX)
213 GLOBAL_INT_DECLARATION();
214
215 GLOBAL_INT_DISABLE();
216 #endif
217 while (REG_READ(REG_FLASH_OPERATE_SW) & BUSY_SW);
218
219 value = REG_READ(REG_FLASH_CONF);
220 value &= ~(WRSR_DATA_MASK << WRSR_DATA_POSI);
221
222 value |= (val << WRSR_DATA_POSI);
223
224 REG_WRITE(REG_FLASH_CONF, value);
225 while (REG_READ(REG_FLASH_OPERATE_SW) & BUSY_SW);
226
227 if (sr_width == 1) {
228 value = (FLASH_OPCODE_WRSR << OP_TYPE_SW_POSI) | OP_SW | WP_VALUE;
229 REG_WRITE(REG_FLASH_OPERATE_SW, value);
230 } else if (sr_width == 2) {
231 if (FLASH_ID_GD25Q32C == flash_id) {
232 //write sr lower 8 bit
233 UINT32 cmd_l = (FLASH_OPCODE_WRSR << OP_TYPE_SW_POSI) | OP_SW | WP_VALUE;
234 REG_WRITE(REG_FLASH_OPERATE_SW, cmd_l);
235 while (REG_READ(REG_FLASH_OPERATE_SW) & BUSY_SW);
236
237 //write sr higher 8 bit
238 value = REG_READ(REG_FLASH_CONF);
239 value &= ~(WRSR_DATA_MASK << WRSR_DATA_POSI);
240 value |= ((val >> 8) << WRSR_DATA_POSI);
241 REG_WRITE(REG_FLASH_CONF, value);
242 while (REG_READ(REG_FLASH_OPERATE_SW) & BUSY_SW);
243
244 flash_init_wrsr_cmd(WRSR_CMD_S8_S15);
245 while (REG_READ(REG_FLASH_OPERATE_SW) & BUSY_SW);
246 UINT32 cmd_h = (FLASH_OPCODE_WRSR << OP_TYPE_SW_POSI) | OP_SW | WP_VALUE;
247 REG_WRITE(REG_FLASH_OPERATE_SW, cmd_h);
248 while (REG_READ(REG_FLASH_OPERATE_SW) & BUSY_SW);
249 flash_deinit_wrsr_cmd();
250 } else {
251 value = (FLASH_OPCODE_WRSR2 << OP_TYPE_SW_POSI) | OP_SW | WP_VALUE;
252 REG_WRITE(REG_FLASH_OPERATE_SW, value);
253 }
254 }
255
256 while (REG_READ(REG_FLASH_OPERATE_SW) & BUSY_SW);
257 #if (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A) || (CONFIG_SOC_BK7256XX)
258 GLOBAL_INT_RESTORE();
259 #endif
260 }
261
flash_read_qe(void)262 static UINT8 flash_read_qe(void)
263 {
264 UINT8 temp;
265 UINT32 value;
266
267 if (1 == flash_current_config->sr_size) {
268 value = (FLASH_OPCODE_RDSR << OP_TYPE_SW_POSI) | OP_SW | WP_VALUE;
269 REG_WRITE(REG_FLASH_OPERATE_SW, value);
270 } else {
271 value = (FLASH_OPCODE_RDSR2 << OP_TYPE_SW_POSI) | OP_SW | WP_VALUE;
272 REG_WRITE(REG_FLASH_OPERATE_SW, value);
273 }
274
275 while (REG_READ(REG_FLASH_OPERATE_SW) & BUSY_SW);
276
277 value = REG_READ(REG_FLASH_SR_DATA_CRC_CNT);
278 temp = (value & 0xFF);
279 return temp;
280 }
281
flash_set_qe(void)282 static void flash_set_qe(void)
283 {
284 UINT32 value, param;
285
286 while (REG_READ(REG_FLASH_OPERATE_SW) & BUSY_SW);
287 param = flash_read_sr(flash_current_config->sr_size);
288 if ((param & (flash_current_config->qe_bit << flash_current_config->qe_bit_post)))
289 return ;
290
291 value = REG_READ(REG_FLASH_CONF);
292 value &= ~(WRSR_DATA_MASK << WRSR_DATA_POSI);
293 value |= (((flash_current_config->qe_bit << flash_current_config->qe_bit_post)
294 | param) << WRSR_DATA_POSI);
295 REG_WRITE(REG_FLASH_CONF, value);
296
297 value = REG_READ(REG_FLASH_OPERATE_SW);
298
299 if (1 == flash_current_config->sr_size) {
300 value = (value & (ADDR_SW_REG_MASK << ADDR_SW_REG_POSI))
301 | (FLASH_OPCODE_WRSR << OP_TYPE_SW_POSI) | OP_SW | WP_VALUE;
302 } else {
303 if (FLASH_ID_GD25Q32C == flash_id) {
304 //write sr lower 8 bit
305 value = (value & (ADDR_SW_REG_MASK << ADDR_SW_REG_POSI))
306 | (FLASH_OPCODE_WRSR << OP_TYPE_SW_POSI) | OP_SW | WP_VALUE;
307 REG_WRITE(REG_FLASH_OPERATE_SW, value);
308 while (REG_READ(REG_FLASH_OPERATE_SW) & BUSY_SW);
309
310 //write sr higher 8 bit
311 value = REG_READ(REG_FLASH_CONF);
312 value &= ~(WRSR_DATA_MASK << WRSR_DATA_POSI);
313 value |= ((((flash_current_config->qe_bit << flash_current_config->qe_bit_post)
314 | param) >> 8) << WRSR_DATA_POSI);
315
316 REG_WRITE(REG_FLASH_CONF, value);
317 while (REG_READ(REG_FLASH_OPERATE_SW) & BUSY_SW);
318
319 value = REG_READ(REG_FLASH_OPERATE_SW);
320 flash_init_wrsr_cmd(WRSR_CMD_S8_S15);
321 value = (value & (ADDR_SW_REG_MASK << ADDR_SW_REG_POSI))
322 | (FLASH_OPCODE_WRSR << OP_TYPE_SW_POSI) | OP_SW | WP_VALUE;
323 } else {
324 value = (value & (ADDR_SW_REG_MASK << ADDR_SW_REG_POSI))
325 | (FLASH_OPCODE_WRSR2 << OP_TYPE_SW_POSI) | OP_SW | WP_VALUE;
326 }
327 }
328
329 REG_WRITE(REG_FLASH_OPERATE_SW, value);
330 while (REG_READ(REG_FLASH_OPERATE_SW) & BUSY_SW);
331
332 flash_deinit_wrsr_cmd();
333 }
334
flash_set_qwfr(void)335 static void flash_set_qwfr(void)
336 {
337 UINT32 value;
338
339 value = REG_READ(REG_FLASH_CONF);
340 value &= ~(MODEL_SEL_MASK << MODEL_SEL_POSI);
341 value |= (flash_current_config->mode_sel << MODEL_SEL_POSI);
342 REG_WRITE(REG_FLASH_CONF, value);
343 }
344
flash_clr_qwfr(void)345 static void flash_clr_qwfr(void)
346 {
347 UINT32 value;
348
349 value = REG_READ(REG_FLASH_CONF);
350 value &= ~(MODEL_SEL_MASK << MODEL_SEL_POSI);
351 REG_WRITE(REG_FLASH_CONF, value);
352
353 value = REG_READ(REG_FLASH_OPERATE_SW);
354 value = ((0 << ADDR_SW_REG_POSI)
355 | (FLASH_OPCODE_CRMR << OP_TYPE_SW_POSI)
356 | OP_SW
357 | (value & WP_VALUE));
358 REG_WRITE(REG_FLASH_OPERATE_SW, value);
359
360 while (REG_READ(REG_FLASH_OPERATE_SW) & BUSY_SW);
361 }
362
flash_set_wsr(UINT16 data)363 static void flash_set_wsr(UINT16 data)
364 {
365 UINT32 value;
366
367 while (REG_READ(REG_FLASH_OPERATE_SW) & BUSY_SW);
368
369 value = REG_READ(REG_FLASH_CONF);
370 value &= ~(WRSR_DATA_MASK << WRSR_DATA_POSI);
371 value |= (data << WRSR_DATA_POSI);
372 REG_WRITE(REG_FLASH_CONF, value);
373
374 value = REG_READ(REG_FLASH_OPERATE_SW);
375 value = (value & (ADDR_SW_REG_MASK << ADDR_SW_REG_POSI))
376 | (FLASH_OPCODE_WRSR2 << OP_TYPE_SW_POSI) | OP_SW | WP_VALUE;
377 REG_WRITE(REG_FLASH_OPERATE_SW, value);
378
379 while (REG_READ(REG_FLASH_OPERATE_SW) & BUSY_SW);
380 }
381
flash_get_line_mode(void)382 UINT8 flash_get_line_mode(void)
383 {
384 return flash_current_config->line_mode;
385 }
386
flash_set_line_mode(UINT8 mode)387 void flash_set_line_mode(UINT8 mode)
388 {
389 UINT32 value;
390
391 if (1 == mode)
392 flash_clr_qwfr();
393 if (2 == mode) {
394 flash_clr_qwfr();
395 value = REG_READ(REG_FLASH_CONF);
396 value &= ~(MODEL_SEL_MASK << MODEL_SEL_POSI);
397 value |= ((MODE_DUAL & MODEL_SEL_MASK) << MODEL_SEL_POSI);
398 REG_WRITE(REG_FLASH_CONF, value);
399 } else if (4 == mode) {
400 flash_clr_qwfr();
401 value = REG_READ(REG_FLASH_SR_DATA_CRC_CNT);
402 value &= ~(M_VALUE_MASK << M_VALUE_POST);
403 value |= (flash_current_config->m_value << M_VALUE_POST);
404
405 REG_WRITE(REG_FLASH_SR_DATA_CRC_CNT, value);
406
407 value = REG_READ(REG_FLASH_SR_DATA_CRC_CNT);
408
409 if (1 == flash_current_config->qe_bit)
410 flash_set_qe();
411
412 flash_set_qwfr();
413 }
414 }
415
flash_get_id(void)416 static UINT32 flash_get_id(void)
417 {
418 UINT32 value;
419
420 value = (FLASH_OPCODE_RDID << OP_TYPE_SW_POSI) | OP_SW | WP_VALUE;
421 REG_WRITE(REG_FLASH_OPERATE_SW, value);
422
423 while (REG_READ(REG_FLASH_OPERATE_SW) & BUSY_SW);
424 flash_id = REG_READ(REG_FLASH_RDID_DATA_FLASH);
425 return flash_id;
426 }
427
flash_read_mid(void)428 static UINT32 flash_read_mid(void)
429 {
430 UINT32 value;
431 UINT32 flash_id;
432
433 while (REG_READ(REG_FLASH_OPERATE_SW) & BUSY_SW);
434
435 value = REG_READ(REG_FLASH_OPERATE_SW);
436 value = ((value & (ADDR_SW_REG_MASK << ADDR_SW_REG_POSI))
437 | (FLASH_OPCODE_RDID << OP_TYPE_SW_POSI)
438 | OP_SW
439 | (value & WP_VALUE));
440 REG_WRITE(REG_FLASH_OPERATE_SW, value);
441 while (REG_READ(REG_FLASH_OPERATE_SW) & BUSY_SW);
442
443 flash_id = REG_READ(REG_FLASH_RDID_DATA_FLASH);
444
445 return flash_id;
446 }
447
get_flash_protect(void)448 PROTECT_TYPE get_flash_protect(void)
449 {
450 UINT16 sr_value, cmp, param, value, type;
451
452 sr_value = flash_read_sr(flash_current_config->sr_size);
453 param = (sr_value >> flash_current_config->protect_post) & flash_current_config->protect_mask;
454 cmp = (sr_value >> flash_current_config->cmp_post) & 0x01;
455 value = (cmp << 8) | param;
456
457 if (value == flash_current_config->protect_all)
458 type = FLASH_PROTECT_ALL;
459 else if (value == flash_current_config->protect_none)
460 type = FLASH_PROTECT_NONE;
461 else if (value == flash_current_config->protect_half)
462 type = FLASH_PROTECT_HALF;
463 else if (value == flash_current_config->unprotect_last_block)
464 type = FLASH_UNPROTECT_LAST_BLOCK;
465 else
466 type = -1;
467
468 return type;
469 }
470
set_flash_protect(PROTECT_TYPE type)471 static void set_flash_protect(PROTECT_TYPE type)
472 {
473 UINT32 param, value, cmp;
474
475 switch (type) {
476 case FLASH_PROTECT_NONE:
477 param = flash_current_config->protect_none & 0xff;
478 cmp = (flash_current_config->protect_none >> 8) & 0xff;
479 break;
480
481 case FLASH_PROTECT_ALL:
482 param = flash_current_config->protect_all & 0xff;
483 cmp = (flash_current_config->protect_all >> 8) & 0xff;
484 break;
485
486 case FLASH_PROTECT_HALF:
487 param = flash_current_config->protect_half & 0xff;
488 cmp = (flash_current_config->protect_half >> 8) & 0xff;
489 break;
490
491 case FLASH_UNPROTECT_LAST_BLOCK:
492 param = flash_current_config->unprotect_last_block & 0xff;
493 cmp = (flash_current_config->unprotect_last_block >> 8) & 0xff;
494 break;
495
496 default:
497 param = flash_current_config->protect_all & 0xff;
498 cmp = (flash_current_config->protect_all >> 8) & 0xff;
499 break;
500 }
501
502 value = flash_read_sr(flash_current_config->sr_size);
503
504 if (((param << flash_current_config->protect_post) !=
505 (value & (flash_current_config->protect_mask << flash_current_config->protect_post)))
506 || ((cmp << flash_current_config->cmp_post) !=
507 (value & (0x01 << flash_current_config->cmp_post)))) {
508 value = (value & (~(flash_current_config->protect_mask
509 << flash_current_config->protect_post)))
510 | (param << flash_current_config->protect_post);
511 value &= ~(1 << flash_current_config->cmp_post);
512 value |= ((cmp & 0x01) << flash_current_config->cmp_post);
513
514 BK_LOGD(TAG, "--write status reg:%x,%x--\r\n", value, flash_current_config->sr_size);
515 flash_write_sr(flash_current_config->sr_size, value);
516 }
517 }
518
flash_erase_sector(UINT32 address)519 static void flash_erase_sector(UINT32 address)
520 {
521 UINT32 value;
522 UINT32 erase_addr = address & 0xFFF000;
523 #if (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A) || (CONFIG_SOC_BK7256XX)
524 GLOBAL_INT_DECLARATION();
525 #endif
526
527 if (erase_addr >= flash_current_config->flash_size) {
528 BK_LOGE("Erase error:invalid address0x%x\r\n", erase_addr);
529 return;
530 }
531
532 #if (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A) || (CONFIG_SOC_BK7256XX)
533 GLOBAL_INT_DISABLE();
534 #endif
535 while (REG_READ(REG_FLASH_OPERATE_SW) & BUSY_SW);
536 value = REG_READ(REG_FLASH_OPERATE_SW);
537 value = ((erase_addr << ADDR_SW_REG_POSI)
538 | (FLASH_OPCODE_SE << OP_TYPE_SW_POSI)
539 | OP_SW
540 | (value & WP_VALUE));
541 REG_WRITE(REG_FLASH_OPERATE_SW, value);
542 while (REG_READ(REG_FLASH_OPERATE_SW) & BUSY_SW);
543 #if (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A) || (CONFIG_SOC_BK7256XX)
544 GLOBAL_INT_RESTORE();
545 #endif
546 }
547
flash_set_hpm(void)548 static void flash_set_hpm(void)
549 {
550 UINT32 value;
551
552 while (REG_READ(REG_FLASH_OPERATE_SW) & BUSY_SW);
553 value = REG_READ(REG_FLASH_OPERATE_SW);
554 value = ((0x0 << ADDR_SW_REG_POSI)
555 | (FLASH_OPCODE_HPM << OP_TYPE_SW_POSI)
556 | (OP_SW)
557 | (value & WP_VALUE));
558 REG_WRITE(REG_FLASH_OPERATE_SW, value);
559 while (REG_READ(REG_FLASH_OPERATE_SW) & BUSY_SW);
560 }
561
flash_read_data(UINT8 * buffer,UINT32 address,UINT32 len)562 static void flash_read_data(UINT8 *buffer, UINT32 address, UINT32 len)
563 {
564 UINT32 i, reg_value;
565 UINT32 addr = address & (~0x1F);
566 UINT32 buf[8];
567 UINT8 *pb = (UINT8 *)&buf[0];
568 #if (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A) || (CONFIG_SOC_BK7256XX)
569 GLOBAL_INT_DECLARATION();
570 #endif
571
572 if (len == 0)
573 return;
574
575 #if (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A) || (CONFIG_SOC_BK7256XX)
576 GLOBAL_INT_DISABLE();
577 #endif
578 while (REG_READ(REG_FLASH_OPERATE_SW) & BUSY_SW);
579 while (len) {
580 reg_value = REG_READ(REG_FLASH_OPERATE_SW);
581 reg_value = ((addr << ADDR_SW_REG_POSI)
582 | (FLASH_OPCODE_READ << OP_TYPE_SW_POSI)
583 | OP_SW
584 | (reg_value & WP_VALUE));
585 REG_WRITE(REG_FLASH_OPERATE_SW, reg_value);
586 while (REG_READ(REG_FLASH_OPERATE_SW) & BUSY_SW);
587 addr += 32;
588
589 for (i = 0; i < 8; i++)
590 buf[i] = REG_READ(REG_FLASH_DATA_FLASH_SW);
591
592 for (i = address % 32; i < 32; i++) {
593 *buffer++ = pb[i];
594 address++;
595 len--;
596 if (len == 0)
597 break;
598 }
599 }
600 #if (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A) || (CONFIG_SOC_BK7256XX)
601 GLOBAL_INT_RESTORE();
602 #endif
603 }
604
flash_write_data(UINT8 * buffer,UINT32 address,UINT32 len)605 static void flash_write_data(UINT8 *buffer, UINT32 address, UINT32 len)
606 {
607 UINT32 i, reg_value;
608 UINT32 addr = address & (~0x1F);
609 UINT32 buf[8];
610 UINT8 *pb = (UINT8 *)&buf[0];
611 #if (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A) || (CONFIG_SOC_BK7256XX)
612 GLOBAL_INT_DECLARATION();
613 #endif
614
615 if ((addr >= flash_current_config->flash_size)
616 || (len > flash_current_config->flash_size)
617 || ((addr + len) > flash_current_config->flash_size)) {
618 BK_LOGE("Write error[addr:0x%x len:0x%x]\r\n", addr, len);
619 return;
620 }
621
622 if (address % 32)
623 flash_read_data(pb, addr, 32);
624 else
625 os_memset(pb, 0xFF, 32);
626
627 while (REG_READ(REG_FLASH_OPERATE_SW) & BUSY_SW);
628 while (len) {
629 if (len < 32) {
630 flash_read_data(pb, addr, 32);
631 while (REG_READ(REG_FLASH_OPERATE_SW) & BUSY_SW);
632 }
633 for (i = address % 32; i < 32; i++) {
634 pb[i] = *buffer++;
635 address++;
636 len--;
637 if (len == 0)
638 break;
639 }
640
641 #if (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A) || (CONFIG_SOC_BK7256XX)
642 GLOBAL_INT_DISABLE();
643 #endif
644 for (i = 0; i < 8; i++)
645 REG_WRITE(REG_FLASH_DATA_SW_FLASH, buf[i]);
646
647 reg_value = REG_READ(REG_FLASH_OPERATE_SW);
648 reg_value = ((addr << ADDR_SW_REG_POSI)
649 | (FLASH_OPCODE_PP << OP_TYPE_SW_POSI)
650 | OP_SW
651 | (reg_value & WP_VALUE));
652 REG_WRITE(REG_FLASH_OPERATE_SW, reg_value);
653 while (REG_READ(REG_FLASH_OPERATE_SW) & BUSY_SW);
654 #if (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A) || (CONFIG_SOC_BK7256XX)
655 GLOBAL_INT_RESTORE();
656 #endif
657 addr += 32;
658 os_memset(pb, 0xFF, 32);
659 }
660 }
661
flash_protection_op(UINT8 mode,PROTECT_TYPE type)662 void flash_protection_op(UINT8 mode, PROTECT_TYPE type)
663 {
664 set_flash_protect(type);
665 }
666
flash_init(void)667 void flash_init(void)
668 {
669 UINT32 id;
670
671 while (REG_READ(REG_FLASH_OPERATE_SW) & BUSY_SW);
672
673 id = flash_get_id();
674 BK_LOGI(TAG, "id=0x%x\r\n", id);
675 flash_get_current_flash_config();
676
677 set_flash_protect(FLASH_UNPROTECT_LAST_BLOCK);
678
679 #if (0 == CONFIG_JTAG)
680 flash_disable_cpu_data_wr();
681 #endif
682
683 flash_set_line_mode(flash_current_config->line_mode);
684
685 flash_set_clk(5); // 5:clk_flash/2;8:clk_flash/1
686
687 ddev_register_dev(DD_DEV_TYPE_FLASH, (DD_OPERATIONS *)&flash_op);
688
689 BK_LOGD(TAG, "init over\r\n");
690 }
691
flash_exit(void)692 void flash_exit(void)
693 {
694 ddev_unregister_dev(DD_DEV_TYPE_FLASH);
695 }
696
flash_read(char * user_buf,UINT32 count,UINT32 address)697 UINT32 flash_read(char *user_buf, UINT32 count, UINT32 address)
698 {
699 peri_busy_count_add();
700
701 flash_read_data((UINT8 *)user_buf, address, count);
702
703 peri_busy_count_dec();
704
705 return FLASH_SUCCESS;
706 }
707
flash_write(char * user_buf,UINT32 count,UINT32 address)708 UINT32 flash_write(char *user_buf, UINT32 count, UINT32 address)
709 {
710 peri_busy_count_add();
711
712 if (4 == flash_current_config->line_mode)
713 flash_set_line_mode(LINE_MODE_TWO);
714
715 flash_write_data((UINT8 *)user_buf, address, count);
716
717 if (4 == flash_current_config->line_mode)
718 flash_set_line_mode(LINE_MODE_FOUR);
719 peri_busy_count_dec();
720
721 return FLASH_SUCCESS;
722 }
723
724
flash_ctrl(UINT32 cmd,void * parm)725 UINT32 flash_ctrl(UINT32 cmd, void *parm)
726 {
727 UINT8 clk;
728 UINT16 wsr;
729 UINT32 address;
730 UINT32 reg;
731 UINT32 ret = FLASH_SUCCESS;
732 peri_busy_count_add();
733
734 if (4 == flash_current_config->line_mode)
735 flash_set_line_mode(LINE_MODE_TWO);
736
737 switch (cmd) {
738 case CMD_FLASH_SET_CLK:
739 clk = (*(UINT8 *)parm);
740 flash_set_clk(clk);
741 break;
742
743 case CMD_FLASH_SET_DPLL:
744 //sddev_control(DD_DEV_TYPE_SCTRL, CMD_SCTRL_SET_FLASH_DPLL, 0);
745 sys_drv_flash_set_dpll();
746
747 reg = REG_READ(REG_FLASH_CONF);
748 reg &= ~(FLASH_CLK_CONF_MASK << FLASH_CLK_CONF_POSI);
749 reg = reg | (5 << FLASH_CLK_CONF_POSI);
750 REG_WRITE(REG_FLASH_CONF, reg);
751 break;
752
753 case CMD_FLASH_SET_DCO:
754 //sddev_control(DD_DEV_TYPE_SCTRL, CMD_SCTRL_SET_FLASH_DCO, 0);
755 sys_drv_flash_set_dco();
756
757 reg = REG_READ(REG_FLASH_CONF);
758 reg &= ~(FLASH_CLK_CONF_MASK << FLASH_CLK_CONF_POSI);
759 if (ate_is_enabled())
760 reg = reg | (0xB << FLASH_CLK_CONF_POSI);
761 else
762 reg = reg | (9 << FLASH_CLK_CONF_POSI);
763 REG_WRITE(REG_FLASH_CONF, reg);
764 break;
765
766 case CMD_FLASH_WRITE_ENABLE:
767 flash_write_enable();
768 break;
769
770 case CMD_FLASH_WRITE_DISABLE:
771 flash_write_disable();
772 break;
773
774 case CMD_FLASH_READ_SR:
775 (*(UINT16 *)parm) = flash_read_sr(2);
776 break;
777
778 case CMD_FLASH_WRITE_SR:
779 flash_write_sr(*(unsigned long *)parm & 0x00FF, ((*(unsigned long *)parm) >> 8) & 0x00FFFF);
780 break;
781
782 case CMD_FLASH_READ_QE:
783 (*(UINT8 *)parm) = flash_read_qe();
784 break;
785
786 case CMD_FLASH_SET_QE:
787 if (flash_current_config->qe_bit)
788 flash_set_qe();
789 break;
790
791 case CMD_FLASH_SET_QWFR:
792 flash_set_qwfr();
793 break;
794
795 case CMD_FLASH_CLR_QWFR:
796 flash_clr_qwfr();
797 break;
798
799 case CMD_FLASH_SET_WSR:
800 wsr = (*(UINT16 *)parm);
801 flash_set_wsr(wsr);
802 break;
803
804 case CMD_FLASH_GET_ID:
805 (*(UINT32 *)parm) = flash_get_id();
806 break;
807
808 case CMD_FLASH_READ_MID:
809 (*(UINT32 *)parm) = flash_read_mid();
810 break;
811
812 case CMD_FLASH_GET_PROTECT:
813 (*(UINT32 *)parm) = get_flash_protect();
814 break;
815
816 case CMD_FLASH_ERASE_SECTOR:
817 address = (*(UINT32 *)parm);
818 flash_erase_sector(address);
819 break;
820
821 case CMD_FLASH_SET_HPM:
822 flash_set_hpm();
823 break;
824
825 case CMD_FLASH_SET_PROTECT:
826 reg = (*(UINT32 *)parm);
827 flash_protection_op(FLASH_XTX_16M_SR_WRITE_DISABLE, reg);
828 break;
829
830 default:
831 ret = FLASH_FAILURE;
832 break;
833 }
834
835 if (4 == flash_current_config->line_mode) {
836 flash_set_line_mode(LINE_MODE_FOUR);
837 //BK_LOGI(TAG, "change line mode 4\r\n");
838 }
839
840 peri_busy_count_dec();
841 return ret;
842 }
843
844
sctrl_flash_select_dco(void)845 void sctrl_flash_select_dco(void)
846 {
847 DD_HANDLE flash_hdl;
848 UINT32 status;
849
850 /* Flash 26MHz clock select dco clock*/
851 flash_hdl = ddev_open(DD_DEV_TYPE_FLASH, &status, 0);
852 ddev_control(flash_hdl, CMD_FLASH_SET_DCO, 0);
853
854 //flash get id shouldn't remove
855 ddev_control(flash_hdl, CMD_FLASH_GET_ID, &status);
856 }
857
858
859
860
861 // eof
862
863