1 /* 2 * SiliconBackplane GCI core hardware definitions 3 * 4 * Copyright (C) 2020, Broadcom. 5 * 6 * Unless you and Broadcom execute a separate written software license 7 * agreement governing use of this software, this software is licensed to you 8 * under the terms of the GNU General Public License version 2 (the "GPL"), 9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 10 * following added to such license: 11 * 12 * As a special exception, the copyright holders of this software give you 13 * permission to link this software with independent modules, and to copy and 14 * distribute the resulting executable under terms of your choice, provided that 15 * you also meet, for each linked independent module, the terms and conditions of 16 * the license of that module. An independent module is a module which is not 17 * derived from this software. The special exception does not apply to any 18 * modifications of the software. 19 * 20 * 21 * <<Broadcom-WL-IPTag/Dual:>> 22 */ 23 24 #ifndef _SBGCI_H 25 #define _SBGCI_H 26 27 #include <bcmutils.h> 28 29 #if !defined(_LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLY__) 30 31 /* cpp contortions to concatenate w/arg prescan */ 32 #ifndef PAD 33 #define _PADLINE(line) pad ## line 34 #define _XSTR(line) _PADLINE(line) 35 #define PAD _XSTR(__LINE__) 36 #endif /* PAD */ 37 38 #define GCI_OFFSETOF(sih, reg) \ 39 (AOB_ENAB(sih) ? OFFSETOF(gciregs_t, reg) : OFFSETOF(chipcregs_t, reg)) 40 #define GCI_CORE_IDX(sih) (AOB_ENAB(sih) ? si_findcoreidx(sih, GCI_CORE_ID, 0) : SI_CC_IDX) 41 42 typedef volatile struct { 43 uint32 gci_corecaps0; /* 0x000 */ 44 uint32 gci_corecaps1; /* 0x004 */ 45 uint32 gci_corecaps2; /* 0x008 */ 46 uint32 gci_corectrl; /* 0x00c */ 47 uint32 gci_corestat; /* 0x010 */ 48 uint32 gci_intstat; /* 0x014 */ 49 uint32 gci_intmask; /* 0x018 */ 50 uint32 gci_wakemask; /* 0x01c */ 51 uint32 gci_levelintstat; /* 0x020 */ 52 uint32 gci_eventintstat; /* 0x024 */ 53 uint32 gci_wakelevelintstat; /* 0x028 */ 54 uint32 gci_wakeeventintstat; /* 0x02c */ 55 uint32 semaphoreintstatus; /* 0x030 */ 56 uint32 semaphoreintmask; /* 0x034 */ 57 uint32 semaphorerequest; /* 0x038 */ 58 uint32 semaphorereserve; /* 0x03c */ 59 uint32 gci_indirect_addr; /* 0x040 */ 60 uint32 gci_gpioctl; /* 0x044 */ 61 uint32 gci_gpiostatus; /* 0x048 */ 62 uint32 gci_gpiomask; /* 0x04c */ 63 uint32 gci_eventsummary; /* 0x050 */ 64 uint32 gci_miscctl; /* 0x054 */ 65 uint32 gci_gpiointmask; /* 0x058 */ 66 uint32 gci_gpiowakemask; /* 0x05c */ 67 uint32 gci_input[32]; /* 0x060 */ 68 uint32 gci_event[32]; /* 0x0e0 */ 69 uint32 gci_output[4]; /* 0x160 */ 70 uint32 gci_control_0; /* 0x170 */ 71 uint32 gci_control_1; /* 0x174 */ 72 uint32 gci_intpolreg; /* 0x178 */ 73 uint32 gci_levelintmask; /* 0x17c */ 74 uint32 gci_eventintmask; /* 0x180 */ 75 uint32 wakelevelintmask; /* 0x184 */ 76 uint32 wakeeventintmask; /* 0x188 */ 77 uint32 hwmask; /* 0x18c */ 78 uint32 PAD; 79 uint32 gci_inbandeventintmask; /* 0x194 */ 80 uint32 PAD; 81 uint32 gci_inbandeventstatus; /* 0x19c */ 82 uint32 gci_seciauxtx; /* 0x1a0 */ 83 uint32 gci_seciauxrx; /* 0x1a4 */ 84 uint32 gci_secitx_datatag; /* 0x1a8 */ 85 uint32 gci_secirx_datatag; /* 0x1ac */ 86 uint32 gci_secitx_datamask; /* 0x1b0 */ 87 uint32 gci_seciusef0tx_reg; /* 0x1b4 */ 88 uint32 gci_secif0tx_offset; /* 0x1b8 */ 89 uint32 gci_secif0rx_offset; /* 0x1bc */ 90 uint32 gci_secif1tx_offset; /* 0x1c0 */ 91 uint32 gci_rxfifo_common_ctrl; /* 0x1c4 */ 92 uint32 gci_rxfifoctrl; /* 0x1c8 */ 93 uint32 gci_hw_sema_status; /* 0x1cc */ 94 uint32 gci_seciuartescval; /* 0x1d0 */ 95 uint32 gic_seciuartautobaudctr; /* 0x1d4 */ 96 uint32 gci_secififolevel; /* 0x1d8 */ 97 uint32 gci_seciuartdata; /* 0x1dc */ 98 uint32 gci_secibauddiv; /* 0x1e0 */ 99 uint32 gci_secifcr; /* 0x1e4 */ 100 uint32 gci_secilcr; /* 0x1e8 */ 101 uint32 gci_secimcr; /* 0x1ec */ 102 uint32 gci_secilsr; /* 0x1f0 */ 103 uint32 gci_secimsr; /* 0x1f4 */ 104 uint32 gci_baudadj; /* 0x1f8 */ 105 uint32 gci_inbandintmask; /* 0x1fc */ 106 uint32 gci_chipctrl; /* 0x200 */ 107 uint32 gci_chipsts; /* 0x204 */ 108 uint32 gci_gpioout; /* 0x208 */ 109 uint32 gci_gpioout_read; /* 0x20C */ 110 uint32 gci_mpwaketx; /* 0x210 */ 111 uint32 gci_mpwakedetect; /* 0x214 */ 112 uint32 gci_seciin_ctrl; /* 0x218 */ 113 uint32 gci_seciout_ctrl; /* 0x21C */ 114 uint32 gci_seciin_auxfifo_en; /* 0x220 */ 115 uint32 gci_seciout_txen_txbr; /* 0x224 */ 116 uint32 gci_seciin_rxbrstatus; /* 0x228 */ 117 uint32 gci_seciin_rxerrstatus; /* 0x22C */ 118 uint32 gci_seciin_fcstatus; /* 0x230 */ 119 uint32 gci_seciout_txstatus; /* 0x234 */ 120 uint32 gci_seciout_txbrstatus; /* 0x238 */ 121 uint32 wlan_mem_info; /* 0x23C */ 122 uint32 wlan_bankxinfo; /* 0x240 */ 123 uint32 bt_smem_select; /* 0x244 */ 124 uint32 bt_smem_stby; /* 0x248 */ 125 uint32 bt_smem_status; /* 0x24C */ 126 uint32 wlan_bankxactivepda; /* 0x250 */ 127 uint32 wlan_bankxsleeppda; /* 0x254 */ 128 uint32 wlan_bankxkill; /* 0x258 */ 129 uint32 reset_override; /* 0x25C */ 130 uint32 ip_id; /* 0x260 */ 131 uint32 lpo_safe_zone; /* 0x264 */ 132 uint32 function_sel_control_and_status; /* 0x268 */ 133 uint32 bt_smem_control0; /* 0x26C */ 134 uint32 bt_smem_control1; /* 0x270 */ 135 uint32 PAD[PADSZ(0x274, 0x2fc)]; /* 0x274-0x2fc */ 136 uint32 gci_chipid; /* 0x300 */ 137 uint32 PAD[PADSZ(0x304, 0x30c)]; /* 0x304-0x30c */ 138 uint32 otpstatus; /* 0x310 */ 139 uint32 otpcontrol; /* 0x314 */ 140 uint32 otpprog; /* 0x318 */ 141 uint32 otplayout; /* 0x31c */ 142 uint32 otplayoutextension; /* 0x320 */ 143 uint32 otpcontrol1; /* 0x324 */ 144 uint32 otpprogdata; /* 0x328 */ 145 uint32 PAD[PADSZ(0x32c, 0x3f8)]; /* 0x32c-0x3f8 */ 146 uint32 otpECCstatus; /* 0x3FC */ 147 uint32 gci_rffe_rfem_data0; /* 0x400 */ 148 uint32 gci_rffe_rfem_data1; /* 0x404 */ 149 uint32 gci_rffe_rfem_data2; /* 0x408 */ 150 uint32 gci_rffe_rfem_data3; /* 0x40c */ 151 uint32 gci_rffe_rfem_addr; /* 0x410 */ 152 uint32 gci_rffe_config; /* 0x414 */ 153 uint32 gci_rffe_clk_ctrl; /* 0x418 */ 154 uint32 gci_rffe_ctrl; /* 0x41c */ 155 uint32 gci_rffe_misc_ctrl; /* 0x420 */ 156 uint32 gci_rffe_rfem_reg0_field_ctrl; /* 0x424 */ 157 uint32 PAD[PADSZ(0x428, 0x438)]; /* 0x428-0x438 */ 158 uint32 gci_rffe_rfem_mapping_mux0; /* 0x43c */ 159 uint32 gci_rffe_rfem_mapping_mux1; /* 0x440 */ 160 uint32 gci_rffe_rfem_mapping_mux2; /* 0x444 */ 161 uint32 gci_rffe_rfem_mapping_mux3; /* 0x448 */ 162 uint32 gci_rffe_rfem_mapping_mux4; /* 0x44c */ 163 uint32 gci_rffe_rfem_mapping_mux5; /* 0x450 */ 164 uint32 gci_rffe_rfem_mapping_mux6; /* 0x454 */ 165 uint32 gci_rffe_rfem_mapping_mux7; /* 0x458 */ 166 uint32 gci_rffe_change_detect_ovr_wlmc; /* 0x45c */ 167 uint32 gci_rffe_change_detect_ovr_wlac; /* 0x460 */ 168 uint32 gci_rffe_change_detect_ovr_wlsc; /* 0x464 */ 169 uint32 gci_rffe_change_detect_ovr_btmc; /* 0x468 */ 170 uint32 gci_rffe_change_detect_ovr_btsc; /* 0x46c */ 171 uint32 gci_cncb_ctrl_status; /* 0x470 */ 172 uint32 gci_cncb_2g_force_unlock; /* 0x474 */ 173 uint32 gci_cncb_5g_force_unlock; /* 0x478 */ 174 uint32 gci_cncb_2g_reset_pulse_width; /* 0x47c */ 175 uint32 gci_cncb_5g_reset_pulse_width; /* 0x480 */ 176 uint32 gci_cncb_lut_indirect_addr; /* 0x484 */ 177 uint32 gci_cncb_2g_lut; /* 0x488 */ 178 uint32 gci_cncb_5g_lut; /* 0x48c */ 179 uint32 gci_cncb_glitch_filter_width; /* 0x490 */ 180 uint32 PAD[PADSZ(0x494, 0x5fc)]; /* 0x494-0x5fc */ 181 uint32 sgr_fifo_control_reg_5g; /* 0x600 */ 182 uint32 sgr_fifo_control_reg_2g; /* 0x604 */ 183 uint32 sgr_fifo_control_reg_bt; /* 0x608 */ 184 uint32 PAD; /* 0x60c */ 185 uint32 sgr_rx_fifo0_read_reg0; /* 0x610 */ 186 uint32 sgr_rx_fifo0_read_reg1; /* 0x614 */ 187 uint32 sgr_rx_fifo0_read_reg2; /* 0x618 */ 188 uint32 sgr_rx_fifo1_read_reg0; /* 0x61c */ 189 uint32 sgr_rx_fifo1_read_reg1; /* 0x620 */ 190 uint32 sgr_rx_fifo1_read_reg2; /* 0x624 */ 191 uint32 sgr_rx_fifo2_read_reg0; /* 0x628 */ 192 uint32 sgr_rx_fifo2_read_reg1; /* 0x62c */ 193 uint32 sgr_rx_fifo2_read_reg2; /* 0x630 */ 194 uint32 sgr_rx_fifo3_read_reg0; /* 0x634 */ 195 uint32 sgr_rx_fifo3_read_reg1; /* 0x638 */ 196 uint32 sgr_rx_fifo3_read_reg2; /* 0x63c */ 197 uint32 sgr_rx_fifo4_read_reg0; /* 0x640 */ 198 uint32 sgr_rx_fifo4_read_reg1; /* 0x644 */ 199 uint32 sgr_rx_fifo4_read_reg2; /* 0x648 */ 200 uint32 sgr_rx_fifo5_read_reg0; /* 0x64c */ 201 uint32 sgr_rx_fifo5_read_reg1; /* 0x650 */ 202 uint32 sgr_rx_fifo5_read_reg2; /* 0x654 */ 203 uint32 sgr_rx_fifo6_read_reg0; /* 0x658 */ 204 uint32 sgr_rx_fifo6_read_reg1; /* 0x65c */ 205 uint32 sgr_rx_fifo6_read_reg2; /* 0x660 */ 206 uint32 sgr_rx_fifo7_read_reg0; /* 0x664 */ 207 uint32 sgr_rx_fifo7_read_reg1; /* 0x668 */ 208 uint32 sgr_rx_fifo7_read_reg2; /* 0x66c */ 209 uint32 sgr_rx_fifo8_read_reg0; /* 0x670 */ 210 uint32 sgr_rx_fifo8_read_reg1; /* 0x674 */ 211 uint32 sgr_rx_fifo8_read_reg2; /* 0x678 */ 212 uint32 sgr_rx_fifo0_read_status; /* 0x67c */ 213 uint32 sgr_rx_fifo1_read_status; /* 0x680 */ 214 uint32 sgr_rx_fifo2_read_status; /* 0x684 */ 215 uint32 sgr_rx_fifo3_read_status; /* 0x688 */ 216 uint32 sgr_rx_fifo4_read_status; /* 0x68c */ 217 uint32 sgr_rx_fifo5_read_status; /* 0x690 */ 218 uint32 sgr_rx_fifo6_read_status; /* 0x694 */ 219 uint32 sgr_rx_fifo7_read_status; /* 0x698 */ 220 uint32 sgr_rx_fifo8_read_status; /* 0x69c */ 221 uint32 wl_tx_fifo_data_idx_reg; /* 0x6a0 */ 222 uint32 wl_tx_fifo_data_reg0; /* 0x6a4 */ 223 uint32 wl_tx_fifo_data_reg1; /* 0x6a8 */ 224 uint32 wl_tx_fifo_data_reg2; /* 0x6ac */ 225 uint32 mac_main_core_tx_fifo_data_idx_reg; /* 0x6b0 */ 226 uint32 mac_main_core_tx_fifo_data_reg0; /* 0x6b4 */ 227 uint32 mac_main_core_tx_fifo_data_reg1; /* 0x6b8 */ 228 uint32 mac_main_core_tx_fifo_data_reg2; /* 0x6bc */ 229 uint32 mac_aux_core_tx_fifo_data_idx_reg; /* 0x6c0 */ 230 uint32 mac_aux_core_tx_fifo_data_reg0; /* 0x6c4 */ 231 uint32 mac_aux_core_tx_fifo_data_reg1; /* 0x6c8 */ 232 uint32 mac_aux_core_tx_fifo_data_reg2; /* 0x6cc */ 233 uint32 bt_tx_fifo_data_idx_reg; /* 0x6d0 */ 234 uint32 bt_tx_fifo_data_reg0; /* 0x6d4 */ 235 uint32 bt_tx_fifo_data_reg1; /* 0x6d8 */ 236 uint32 bt_tx_fifo_data_reg2; /* 0x6dc */ 237 uint32 wci2_tx_fifo_data_reg0; /* 0x6e0 */ 238 uint32 wci2_tx_fifo_data_reg1; /* 0x6e4 */ 239 uint32 sgt_tx_fifo_ctrl; /* 0x6e8 */ 240 uint32 sgt_fifo_status_hpri; /* 0x6ec */ 241 uint32 sgt_fifo_status_norm; /* 0x6f0 */ 242 uint32 sgt_fifo_status_lpri; /* 0x6f4 */ 243 uint32 PAD[PADSZ(0x6f8, 0x7a0)]; /* 0x6f8-0x7a0 */ 244 uint32 sg_timestamp_fifo_ctrl; /* 0x7a4 */ 245 uint32 sgr_timestamp_data_rx; /* 0x7a8 */ 246 uint32 sgr_timestamp_data_tx; /* 0x7ac */ 247 uint32 sgr_fifo_int_reg; /* 0x7b0 */ 248 uint32 sgr_fifo_int_mask_reg; /* 0x7b4 */ 249 uint32 sgt_fifo_int_reg; /* 0x7b8 */ 250 uint32 sgt_fifo_int_mask_reg; /* 0x7bc */ 251 uint32 sg_fifo_debug_bus; /* 0x7c0 */ 252 uint32 PAD[PADSZ(0x7c4, 0xbfc)]; /* 0x7c4-0xbfc */ 253 uint32 lhl_core_capab_adr; /* 0xC00 */ 254 uint32 lhl_main_ctl_adr; /* 0xC04 */ 255 uint32 lhl_pmu_ctl_adr; /* 0xC08 */ 256 uint32 lhl_extlpo_ctl_adr; /* 0xC0C */ 257 uint32 lpo_ctl_adr; /* 0xC10 */ 258 uint32 lhl_lpo2_ctl_adr; /* 0xC14 */ 259 uint32 lhl_osc32k_ctl_adr; /* 0xC18 */ 260 uint32 lhl_clk_status_adr; /* 0xC1C */ 261 uint32 lhl_clk_det_ctl_adr; /* 0xC20 */ 262 uint32 lhl_clk_sel_adr; /* 0xC24 */ 263 uint32 hidoff_cnt_adr[2]; /* 0xC28-0xC2C */ 264 uint32 lhl_autoclk_ctl_adr; /* 0xC30 */ 265 uint32 PAD; /* reserved */ 266 uint32 lhl_hibtim_adr; /* 0xC38 */ 267 uint32 lhl_wl_ilp_val_adr; /* 0xC3C */ 268 uint32 lhl_wl_armtim0_intrp_adr; /* 0xC40 */ 269 uint32 lhl_wl_armtim0_st_adr; /* 0xC44 */ 270 uint32 lhl_wl_armtim0_adr; /* 0xC48 */ 271 uint32 PAD[PADSZ(0xc4c, 0xc6c)]; /* 0xC4C-0xC6C */ 272 uint32 lhl_wl_mactim0_intrp_adr; /* 0xC70 */ 273 uint32 lhl_wl_mactim0_st_adr; /* 0xC74 */ 274 uint32 lhl_wl_mactim_int0_adr; /* 0xC78 */ 275 uint32 lhl_wl_mactim_frac0_adr; /* 0xC7C */ 276 uint32 lhl_wl_mactim1_intrp_adr; /* 0xC80 */ 277 uint32 lhl_wl_mactim1_st_adr; /* 0xC84 */ 278 uint32 lhl_wl_mactim_int1_adr; /* 0xC88 */ 279 uint32 lhl_wl_mactim_frac1_adr; /* 0xC8C */ 280 uint32 lhl_wl_mactim2_intrp_adr; /* 0xC90 */ 281 uint32 lhl_wl_mactim2_st_adr; /* 0xC94 */ 282 uint32 lhl_wl_mactim_int2_adr; /* 0xC98 */ 283 uint32 lhl_wl_mactim_frac2_adr; /* 0xC9C */ 284 uint32 PAD[PADSZ(0xca0, 0xcac)]; /* 0xCA0-0xCAC */ 285 uint32 gpio_int_en_port_adr[4]; /* 0xCB0-0xCBC */ 286 uint32 gpio_int_st_port_adr[4]; /* 0xCC0-0xCCC */ 287 uint32 gpio_ctrl_iocfg_p_adr[40]; /* 0xCD0-0xD6C */ 288 uint32 lhl_lp_up_ctl1_adr; /* 0xd70 */ 289 uint32 lhl_lp_dn_ctl1_adr; /* 0xd74 */ 290 uint32 PAD[PADSZ(0xd78, 0xdb4)]; /* 0xd78-0xdb4 */ 291 uint32 lhl_sleep_timer_adr; /* 0xDB8 */ 292 uint32 lhl_sleep_timer_ctl_adr; /* 0xDBC */ 293 uint32 lhl_sleep_timer_load_val_adr; /* 0xDC0 */ 294 uint32 lhl_lp_main_ctl_adr; /* 0xDC4 */ 295 uint32 lhl_lp_up_ctl_adr; /* 0xDC8 */ 296 uint32 lhl_lp_dn_ctl_adr; /* 0xDCC */ 297 uint32 gpio_gctrl_iocfg_p0_p39_adr; /* 0xDD0 */ 298 uint32 gpio_gdsctrl_iocfg_p0_p25_p30_p39_adr; /* 0xDD4 */ 299 uint32 gpio_gdsctrl_iocfg_p26_p29_adr; /* 0xDD8 */ 300 uint32 PAD[PADSZ(0xddc, 0xdf8)]; /* 0xDDC-0xDF8 */ 301 uint32 lhl_gpio_din0_adr; /* 0xDFC */ 302 uint32 lhl_gpio_din1_adr; /* 0xE00 */ 303 uint32 lhl_wkup_status_adr; /* 0xE04 */ 304 uint32 lhl_ctl_adr; /* 0xE08 */ 305 uint32 lhl_adc_ctl_adr; /* 0xE0C */ 306 uint32 lhl_qdxyz_in_dly_adr; /* 0xE10 */ 307 uint32 lhl_optctl_adr; /* 0xE14 */ 308 uint32 lhl_optct2_adr; /* 0xE18 */ 309 uint32 lhl_scanp_cntr_init_val_adr; /* 0xE1C */ 310 uint32 lhl_opt_togg_val_adr[6]; /* 0xE20-0xE34 */ 311 uint32 lhl_optx_smp_val_adr; /* 0xE38 */ 312 uint32 lhl_opty_smp_val_adr; /* 0xE3C */ 313 uint32 lhl_optz_smp_val_adr; /* 0xE40 */ 314 uint32 lhl_hidoff_keepstate_adr[3]; /* 0xE44-0xE4C */ 315 uint32 lhl_bt_slmboot_ctl0_adr[4]; /* 0xE50-0xE5C */ 316 uint32 lhl_wl_fw_ctl; /* 0xE60 */ 317 uint32 lhl_wl_hw_ctl_adr[2]; /* 0xE64-0xE68 */ 318 uint32 lhl_bt_hw_ctl_adr; /* 0xE6C */ 319 uint32 lhl_top_pwrseq_en_adr; /* 0xE70 */ 320 uint32 lhl_top_pwrdn_ctl_adr; /* 0xE74 */ 321 uint32 lhl_top_pwrup_ctl_adr; /* 0xE78 */ 322 uint32 lhl_top_pwrseq_ctl_adr; /* 0xE7C */ 323 uint32 lhl_top_pwrdn2_ctl_adr; /* 0xE80 */ 324 uint32 lhl_top_pwrup2_ctl_adr; /* 0xE84 */ 325 uint32 wpt_regon_intrp_cfg_adr; /* 0xE88 */ 326 uint32 bt_regon_intrp_cfg_adr; /* 0xE8C */ 327 uint32 wl_regon_intrp_cfg_adr; /* 0xE90 */ 328 uint32 regon_intrp_st_adr; /* 0xE94 */ 329 uint32 regon_intrp_en_adr; /* 0xE98 */ 330 uint32 PAD[PADSZ(0xe9c, 0xeb4)]; /* 0xe9c-0xeb4 */ 331 uint32 lhl_lp_main_ctl1_adr; /* 0xeb8 */ 332 uint32 lhl_lp_up_ctl2_adr; /* 0xebc */ 333 uint32 lhl_lp_dn_ctl2_adr; /* 0xec0 */ 334 uint32 lhl_lp_up_ctl3_adr; /* 0xec4 */ 335 uint32 lhl_lp_dn_ctl3_adr; /* 0xec8 */ 336 uint32 PAD[PADSZ(0xecc, 0xed8)]; /* 0xecc-0xed8 */ 337 uint32 lhl_lp_main_ctl2_adr; /* 0xedc */ 338 uint32 lhl_lp_up_ctl4_adr; /* 0xee0 */ 339 uint32 lhl_lp_dn_ctl4_adr; /* 0xee4 */ 340 uint32 lhl_lp_up_ctl5_adr; /* 0xee8 */ 341 uint32 lhl_lp_dn_ctl5_adr; /* 0xeec */ 342 uint32 lhl_top_pwrdn3_ctl_adr; /* 0xEF0 */ 343 uint32 lhl_top_pwrup3_ctl_adr; /* 0xEF4 */ 344 uint32 PAD[PADSZ(0xef8, 0xf00)]; /* 0xEF8 - 0xF00 */ 345 uint32 error_status; /* 0xF04 */ 346 uint32 error_parity; /* 0xF08 */ 347 uint32 PAD; /* 0xF0C */ 348 uint32 msg_buf_0[8]; /* 0xF10 - 0xF2C */ 349 uint32 PAD[PADSZ(0xf30, 0xf3c)]; /* 0xF30 - 0xF3C */ 350 uint32 CTRL_REG0; /* 0xF40 */ 351 uint32 CTRL_REG1; /* 0xF44 */ 352 uint32 chipID; /* 0xF48 */ 353 uint32 PAD[PADSZ(0xf4c, 0xf54)]; /* 0xF4C - 0xF54 */ 354 uint32 timestamp_mask0; /* 0xf58 */ 355 uint32 timestamp_mask1; /* 0xf5c */ 356 uint32 wl_event_rdAddress; /* 0xF60 */ 357 uint32 bt_event_rdAddress; /* 0xF64 */ 358 uint32 interrupt_Address; /* 0xF68 */ 359 uint32 PAD[PADSZ(0xf6c, 0xf70)]; /* 0xF6c - 0xF70 */ 360 uint32 coex_error_status; /* 0xF74 */ 361 uint32 coex_error_parity; /* 0xF78 */ 362 uint32 PAD; /* 0xF7C */ 363 uint32 ar_buf_01[4]; /* 0xF80 - 0xF8C */ 364 uint32 PAD[PADSZ(0xf90,0xfac)]; /* 0xF90 - 0xFAC */ 365 uint32 coex_ctrl_reg0; /* 0xFB0 */ 366 uint32 coex_ctrl_reg1; /* 0xFB4 */ 367 uint32 coex_chip_id; /* 0xFB8 */ 368 uint32 PAD[PADSZ(0xfbc, 0xfcc)]; /* 0xFBC - 0xFCC */ 369 uint32 coex_wl_event_rd; /* 0xFD0 */ 370 uint32 coex_bt_event_rd; /* 0xFD4 */ 371 uint32 coex_interrupt; /* 0xFD8 */ 372 uint32 PAD; /* 0xFDC */ 373 uint32 spmi_shared_reg_status_intMask_adr; /* 0xFE0 */ 374 uint32 spmi_shared_reg_status_intStatus_adr; /* 0xFE4 */ 375 uint32 spmi_shared_reg_status_wakeMask_adr; /* 0xFE8 */ 376 uint32 spmi_shared_event_map_idx_adr; /* 0xFEC */ 377 uint32 spmi_shared_event_map_data_adr; /* 0xFF0 */ 378 uint32 spmi_coex_event_gpr_status_adr; /* 0xFF4 */ 379 } gciregs_t; 380 381 #define GCI_CAP0_REV_MASK 0x000000ff 382 383 /* GCI Capabilities registers */ 384 #define GCI_CORE_CAP_0_COREREV_MASK 0xFF 385 #define GCI_CORE_CAP_0_COREREV_SHIFT 0 386 387 #define GCI_INDIRECT_ADDRESS_REG_REGINDEX_MASK 0x3F 388 #define GCI_INDIRECT_ADDRESS_REG_REGINDEX_SHIFT 0 389 #define GCI_INDIRECT_ADDRESS_REG_GPIOINDEX_MASK 0xF 390 #define GCI_INDIRECT_ADDRESS_REG_GPIOINDEX_SHIFT 16 391 392 #define WLAN_BANKX_SLEEPPDA_REG_SLEEPPDA_MASK 0xFFFF 393 394 #define WLAN_BANKX_PKILL_REG_SLEEPPDA_MASK 0x1 395 396 /* WLAN BankXInfo Register */ 397 #define WLAN_BANKXINFO_BANK_SIZE_MASK 0x00FFF000 398 #define WLAN_BANKXINFO_BANK_SIZE_SHIFT 12 399 400 /* WLAN Mem Info Register */ 401 #define WLAN_MEM_INFO_REG_NUMSOCRAMBANKS_MASK 0x000000FF 402 #define WLAN_MEM_INFO_REG_NUMSOCRAMBANKS_SHIFT 0 403 404 #define WLAN_MEM_INFO_REG_NUMD11MACBM_MASK 0x0000FF00 405 #define WLAN_MEM_INFO_REG_NUMD11MACBM_SHIFT 8 406 407 #define WLAN_MEM_INFO_REG_NUMD11MACUCM_MASK 0x00FF0000 408 #define WLAN_MEM_INFO_REG_NUMD11MACUCM_SHIFT 16 409 410 #define WLAN_MEM_INFO_REG_NUMD11MACSHM_MASK 0xFF000000 411 #define WLAN_MEM_INFO_REG_NUMD11MACSHM_SHIFT 24 412 413 /* GCI chip status register 9 */ 414 #define GCI_CST9_SCAN_DIS (1u << 31u) /* scan core disable */ 415 416 /* GCI Output register indices */ 417 #define GCI_OUTPUT_IDX_0 0 418 #define GCI_OUTPUT_IDX_1 1 419 #define GCI_OUTPUT_IDX_2 2 420 #define GCI_OUTPUT_IDX_3 3 421 422 #endif /* !_LANGUAGE_ASSEMBLY && !__ASSEMBLY__ */ 423 424 #endif /* _SBGCI_H */ 425