1 /* 2 * Copyright (c) 2021 Bestechnic (Shanghai) Co., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 #ifndef __HAL_DSI_H__ 16 #define __HAL_DSI_H__ 17 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 22 #include "stdint.h" 23 #include "stdbool.h" 24 25 typedef void (*HAL_DSI_TE_GPIO_IRQ_HANDLER)(void); 26 27 struct HAL_DSI_CFG_T { 28 uint32_t active_width; 29 uint32_t active_height;//screen size 30 uint32_t h_front_porch; 31 uint32_t h_back_porch; 32 uint32_t v_front_porch; 33 uint32_t v_back_porch; 34 uint32_t total_width; 35 uint32_t total_height; 36 37 // pn video 38 uint32_t y_mem_pitch; 39 uint32_t uv_mem_pitch; 40 uint32_t c_mem_pitch; 41 uint32_t image_h_sa; 42 uint32_t image_v_sa; 43 uint32_t image_width; 44 uint32_t image_height; 45 uint32_t zm_image_width; 46 uint32_t zm_image_height; 47 48 // pn graphic 49 uint32_t g_mem_pitch; 50 uint32_t graphic_h_sa; 51 uint32_t graphic_v_sa; 52 uint32_t graphic_width; 53 uint32_t graphic_height; 54 uint32_t zm_graphic_width; 55 uint32_t zm_graphic_height; 56 57 // tv graphic 58 uint32_t g_tv_mem_pitch; 59 uint32_t tvg_h_sa; 60 uint32_t tvg_v_sa; 61 uint32_t tvg_width; 62 uint32_t tvg_height; 63 uint32_t zm_tvg_width; 64 uint32_t zm_tvg_height; 65 66 // pn cursor 67 uint32_t cursor_h_sa; 68 uint32_t cursor_v_sa; 69 uint32_t cursor_width; 70 uint32_t cursor_height; 71 int hwc_color1; 72 int hwc_color2; 73 74 //background 75 int blankcolor; 76 77 // pn viedo setting 78 int cos0; 79 int sin0; 80 int c_mult_s; 81 int saturation; 82 int brightness; 83 int contrast; 84 85 // pn keys 86 int cfg_alpha_y; 87 int cfg_ckey_y; 88 int cfg_ckey_y1; 89 int cfg_ckey_y2; 90 int cfg_alpha_u; 91 int cfg_ckey_u; 92 int cfg_ckey_u1; 93 int cfg_ckey_u2; 94 int cfg_alpha_v; 95 int cfg_ckey_v; 96 int cfg_ckey_v1; 97 int cfg_ckey_v2; 98 }; 99 100 enum DSI_MODE_T { 101 /** Video mode */ 102 DSI_MODE_VIDEO, 103 /** Command mode */ 104 DSI_MODE_CMD, 105 }; 106 107 typedef void (*HAL_DSI_XFER_COMPLETE_CALLBACK_T)(uint8_t layerId, uint8_t channel, uint32_t addr); 108 109 /** 110 * @param 111 * h_res horizontal resolution 112 * mode @see enum DSI_MODE_T 113 * dsi_bitclk Mbps 114 * dsi_pclk KHz 115 * @note 116 * Total-pixel = H-total * V-total * fps 117 * Bitclk = Total-pixel * bpp(bit) / lane-number 118 * Byteclk = Bitclk / 8 119 * dsi_clk = Byteclk * lane-number = Total-pixel * bpp(bit) / 8 120 * dsi_pclk = dsi_clk / bpp(byte) = H-total * V-total * fps 121 */ 122 void hal_dsi_init_v2(uint16_t h_res, enum DSI_MODE_T mode, uint8_t lane_number, uint32_t dsi_bitclk, uint32_t dsi_pclk); 123 124 void hal_lcdc_init(const struct HAL_DSI_CFG_T *cfg, const uint8_t *layer0, 125 const uint8_t *layer1, const uint8_t *layer2); 126 127 void hal_lcdc_gamma_enable(const uint8_t * config_R, const uint8_t * config_G, const uint8_t * config_B); 128 129 void hal_lcdc_gamma_disable(void); 130 131 void hal_lcdc_start(void); 132 133 void hal_dsi_send_cmd(uint8_t cmd); 134 int hal_dsi_read_cmd(uint8_t cmd, uint8_t *read_buf, uint8_t len); 135 void hal_dsi_send_cmd_data(uint8_t cmd, uint32_t len, uint8_t p0, uint8_t p1, uint8_t p2, uint8_t p3); 136 void hal_dsi_send_long_array(uint32_t len,uint32_t *data); 137 void hal_dsi_send_cmd_list(unsigned cmd, unsigned char para_count, unsigned char *para_list); 138 139 void hal_lcdc_update_addr(uint8_t layerId, uint8_t channel, uint32_t addr); 140 void hal_lcdc_set_callback(HAL_DSI_XFER_COMPLETE_CALLBACK_T callback); 141 142 /** 143 * @brief hal_dsi_init - init dsi phy 144 * 145 * @param h_res : panel horizontal resolution 146 */ 147 #if defined(NUTTX_BUILD) 148 void hal_dsi_init(uint16_t h_res); 149 #else 150 void hal_dsi_init(uint16_t h_res ,uint8_t lane_number); 151 #endif 152 /** 153 * @brief hal_dsi_reset - reset phy, besause hs mode phy work error, 154 * lp cmd send has some errors. 155 * 156 * @param h_res : panel horizontal resolution 157 */ 158 void hal_dsi_reset(uint16_t h_res); 159 160 /** 161 * @brief hal_dsi_send_cmd - send cmd by lp mode 162 * 163 * @param cmd 164 */ 165 void hal_dsi_send_cmd(uint8_t cmd); 166 167 /** 168 * @brief hal_dsi_read_cmd - read data by lp mode 169 * 170 * @param cmd : cmd 171 * @param read_buf : read buffer 172 * @param len : read len 173 * @return int 174 */ 175 int hal_dsi_read_cmd(uint8_t cmd,uint8_t* read_buf,uint8_t len); 176 177 /** 178 * @brief hal_dsi_send_cmd_data - send cmd with data by lp mode 179 * 180 * @param cmd : cmd 181 * @param len : send param num 182 * @param p0 : param0 183 * @param p1 : param1 184 * @param p2 : param2 185 * @param p3 : param3 186 */ 187 void hal_dsi_send_cmd_data(uint8_t cmd, uint32_t len, uint8_t p0, 188 uint8_t p1, uint8_t p2, uint8_t p3); 189 /** 190 * @brief hal_dsi_send_long_array - send cmd with data with array 191 * 192 * @param len : array len 193 * @param data : array data 194 */ 195 void hal_dsi_send_long_array(uint32_t len,uint32_t *data); 196 197 /** 198 * @brief hal_dsi_send_cmd_list - send cmd with data list 199 * 200 * @param cmd 201 * @param para_count 202 * @param para_list 203 */ 204 void hal_dsi_send_cmd_list(unsigned cmd, unsigned char para_count, 205 unsigned char *para_list); 206 207 /** 208 * hal_dsi_irqn - get dsi irq number 209 */ 210 int hal_dsi_irqn(void); 211 212 /** 213 * hal_dsi_get_irqstate - get dsi irq state 214 */ 215 uint32_t hal_dsi_get_irqstate(void); 216 217 /** 218 * hal_dsi_teirq_enable - enable dsi te irq 219 */ 220 void hal_dsi_teirq_enable(void); 221 222 /** 223 * hal_dsi_irq_disable - disable dsi all irqs 224 */ 225 void hal_dsi_irq_disable(void); 226 227 /** 228 * hal_dsi_clear_teirq_flag - clear dsi te irq state 229 */ 230 void hal_dsi_clear_teirq_flag(void); 231 232 /** 233 * hal_dsi_irq_is_te - irq is te 234 * @regval : dsi ISR value 235 */ 236 bool hal_dsi_irq_is_te(uint32_t regval); 237 238 /** 239 * hal_dsi_irq_is_err - dsi is irq err 240 */ 241 bool hal_dsi_irq_is_err(uint32_t regval); 242 243 /** 244 * hal_dsi_irq_clear_err - clear dsi error flag. 245 */ 246 void hal_dsi_irq_clear_err(uint32_t status); 247 248 /** 249 * hal_dsi_enter_ulps_mode - enter ulps mode 250 */ 251 void hal_dsi_enter_ulps_mode(); 252 253 /** 254 * hal_dsi_exit_ulps_mode - exit ulps mode 255 */ 256 void hal_dsi_exit_ulps_mode(); 257 258 void hal_dsi_start(void); 259 260 void hal_dsi_sleep(void); 261 262 void hal_dsi_wakeup(void); 263 264 void hal_dsi_te_gpio_irq_register(HAL_DSI_TE_GPIO_IRQ_HANDLER hdlr); 265 266 void hal_dsi_te_gpio_irq_enable(void); 267 268 void hal_dsi_te_gpio_irq_disable(void); 269 270 #ifdef __cplusplus 271 } 272 #endif 273 274 #endif 275 276