1 /*
2 * Copyright (c) 2021 Bestechnic (Shanghai) Co., Ltd. All rights reserved.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15 #include "plat_addr_map.h"
16 #include CHIP_SPECIFIC_HDR(reg_cmu)
17 #include CHIP_SPECIFIC_HDR(reg_aoncmu)
18 #include CHIP_SPECIFIC_HDR(reg_btcmu)
19 #include CHIP_SPECIFIC_HDR(reg_wfcmu)
20 #include "hal_cmu.h"
21 #include "hal_aud.h"
22 #include "hal_bootmode.h"
23 #include "hal_chipid.h"
24 #include "hal_codec.h"
25 #include "hal_location.h"
26 #include "hal_psc.h"
27 #include "hal_sec.h"
28 #include "hal_sysfreq.h"
29 #include "hal_timer.h"
30 #include "hal_trace.h"
31 #include "cmsis_nvic.h"
32 #include "pmu.h"
33 #include "analog.h"
34 #include "system_cp.h"
35 #include "hal_psram.h"
36 #include "hal_psramuhs.h"
37 #include "hal_norflash.h"
38 #include "hal_wdt.h"
39 #include "tgt_hardware.h"
40 #include "hal_dma.h"
41 #include CHIP_SPECIFIC_HDR(hal_dmacfg)
42
43 #ifdef FLASH_SUSPEND
44 #include "norflash_api.h"
45 #endif
46
47 #define HAL_CMU_USB_PLL_CLOCK (192 * 1000 * 1000)
48 #define HAL_CMU_AUD_PLL_CLOCK (CODEC_FREQ_48K_SERIES * CODEC_CMU_DIV)
49
50 #define HAL_CMU_USB_CLOCK_60M (60 * 1000 * 1000)
51 #define HAL_CMU_USB_CLOCK_48M (48 * 1000 * 1000)
52
53 #define HAL_CMU_PWM_SLOW_CLOCK (32 * 1000)
54
55 #define HAL_CMU_PLL_LOCKED_TIMEOUT US_TO_TICKS(200)
56 #define HAL_CMU_26M_READY_TIMEOUT MS_TO_TICKS(3)
57 #define HAL_CMU_LPU_EXTRA_TIMEOUT MS_TO_TICKS(1)
58
59 enum CMU_USB_CLK_SRC_T {
60 CMU_USB_CLK_SRC_PLL_48M = 0,
61 CMU_USB_CLK_SRC_PLL_60M = 1,
62 CMU_USB_CLK_SRC_OSC_24M_X2 = 2,
63 };
64
65 enum CMU_AUD_26M_X4_USER_T {
66 CMU_AUD_26M_X4_USER_IIR,
67 CMU_AUD_26M_X4_USER_RS,
68
69 CMU_AUD_26M_X4_USER_QTY,
70 };
71
72 enum CMU_DEBUG_REG_SEL_T {
73 CMU_DEBUG_REG_SEL_MCU_PC = 0,
74 CMU_DEBUG_REG_SEL_MCU_LR = 1,
75 CMU_DEBUG_REG_SEL_MCU_SP = 2,
76 CMU_DEBUG_REG_SEL_CP_PC = 3,
77 CMU_DEBUG_REG_SEL_CP_LR = 4,
78 CMU_DEBUG_REG_SEL_CP_SP = 5,
79 CMU_DEBUG_REG_SEL_DEBUG = 7,
80 };
81
82 enum CMU_DMA_REQ_T {
83 CMU_DMA_REQ_CODEC_RX = 0,
84 CMU_DMA_REQ_CODEC_TX = 1,
85 CMU_DMA_REQ_DSD_RX = 2,
86 CMU_DMA_REQ_DSD_TX = 3,
87 CMU_DMA_REQ_IR_RX = 6,
88 CMU_DMA_REQ_IR_TX = 7,
89 CMU_DMA_REQ_FLS1 = 8,
90 CMU_DMA_REQ_FLS0 = 10,
91 CMU_DMA_REQ_BTDUMP = 12,
92 CMU_DMA_REQ_SDEMMC = 13,
93 CMU_DMA_REQ_I2C0_RX = 14,
94 CMU_DMA_REQ_I2C0_TX = 15,
95 CMU_DMA_REQ_I2C1_RX = 16,
96 CMU_DMA_REQ_I2C1_TX = 17,
97 CMU_DMA_REQ_SPILCD0_RX = 18,
98 CMU_DMA_REQ_SPILCD0_TX = 19,
99 CMU_DMA_REQ_SPILCD1_RX = 20,
100 CMU_DMA_REQ_SPILCD1_TX = 21,
101 CMU_DMA_REQ_SPI_ITN_RX = 22,
102 CMU_DMA_REQ_SPI_ITN_TX = 23,
103 CMU_DMA_REQ_UART0_RX = 24,
104 CMU_DMA_REQ_UART0_TX = 25,
105 CMU_DMA_REQ_UART1_RX = 26,
106 CMU_DMA_REQ_UART1_TX = 27,
107 CMU_DMA_REQ_UART2_RX = 28,
108 CMU_DMA_REQ_UART2_TX = 29,
109 CMU_DMA_REQ_PCM_RX = 30,
110 CMU_DMA_REQ_PCM_TX = 31,
111 CMU_DMA_REQ_I2S0_RX = 32,
112 CMU_DMA_REQ_I2S0_TX = 33,
113 CMU_DMA_REQ_SPDIF0_RX = 34,
114 CMU_DMA_REQ_SPDIF0_TX = 35,
115 CMU_DMA_REQ_I2C2_RX = 36,
116 CMU_DMA_REQ_I2C2_TX = 37,
117 CMU_DMA_REQ_UART3_RX = 38,
118 CMU_DMA_REQ_UART3_TX = 39,
119 CMU_DMA_REQ_I2S1_RX = 40,
120 CMU_DMA_REQ_I2S1_TX = 41,
121
122 CMU_DMA_REQ_NULL = 5,
123 };
124
125 struct CP_STARTUP_CFG_T {
126 __IO uint32_t stack;
127 __IO uint32_t reset_hdlr;
128 };
129
130 static struct CMU_T * const cmu = (struct CMU_T *)CMU_BASE;
131
132 static struct AONCMU_T * const aoncmu = (struct AONCMU_T *)AON_CMU_BASE;
133
134 static struct BTCMU_T * const POSSIBLY_UNUSED btcmu = (struct BTCMU_T *)BT_CMU_BASE;
135
136 static struct WLANCMU_T * const POSSIBLY_UNUSED wlancmu = (struct WLANCMU_T *)WIFI_CMU_BASE;
137
138 static uint32_t cp_entry;
139
140 static uint8_t BOOT_BSS_LOC pll_user_map[HAL_CMU_PLL_QTY];
141 STATIC_ASSERT(HAL_CMU_PLL_USER_QTY <= sizeof(pll_user_map[0]) * 8, "Too many PLL users");
142
143 #ifdef __AUDIO_RESAMPLE__
144 static bool aud_resample_en = true;
145 #ifdef ANA_26M_X4_ENABLE
146 static uint8_t aud_26m_x4_map;
147 STATIC_ASSERT(CMU_AUD_26M_X4_USER_QTY <= sizeof(aud_26m_x4_map) * 8, "Too many aud_26m_x4 users");
148 #endif
149 #endif
150
151 #ifdef ANA_26M_X4_ENABLE
152 #error "CHIP_BEST2003 don't support X4"
153 #endif
154
155 #ifdef LOW_SYS_FREQ
156 static enum HAL_CMU_FREQ_T BOOT_BSS_LOC cmu_sys_freq;
157 #endif
158
hal_cmu_audio_resample_enable(void)159 void hal_cmu_audio_resample_enable(void)
160 {
161 #ifdef __AUDIO_RESAMPLE__
162 aud_resample_en = true;
163 #endif
164 }
165
hal_cmu_audio_resample_disable(void)166 void hal_cmu_audio_resample_disable(void)
167 {
168 #ifdef __AUDIO_RESAMPLE__
169 aud_resample_en = false;
170 #endif
171 }
172
hal_cmu_get_audio_resample_status(void)173 int hal_cmu_get_audio_resample_status(void)
174 {
175 #ifdef __AUDIO_RESAMPLE__
176 return aud_resample_en;
177 #else
178 return false;
179 #endif
180 }
181
aocmu_reg_update_wait(void)182 static inline void aocmu_reg_update_wait(void)
183 {
184 // Make sure AOCMU (26M clock domain) write opertions finish before return
185 aoncmu->CHIP_ID;
186 }
187
hal_cmu_clock_enable(enum HAL_CMU_MOD_ID_T id)188 int hal_cmu_clock_enable(enum HAL_CMU_MOD_ID_T id)
189 {
190 if (id >= HAL_CMU_AON_A7) {
191 return 1;
192 }
193
194 if (id < HAL_CMU_MOD_P_CMU) {
195 cmu->HCLK_ENABLE = (1 << id);
196 } else if (id < HAL_CMU_MOD_O_SLEEP) {
197 cmu->PCLK_ENABLE = (1 << (id - HAL_CMU_MOD_P_CMU));
198 } else if (id < HAL_CMU_MOD_Q_NULL) {
199 cmu->OCLK_ENABLE = (1 << (id - HAL_CMU_MOD_O_SLEEP));
200 } else if (id < HAL_CMU_AON_A_CMU) {
201 cmu->QCLK_ENABLE = (1 << (id - HAL_CMU_MOD_Q_NULL));
202 } else {
203 aoncmu->MOD_CLK_ENABLE = (1 << (id - HAL_CMU_AON_A_CMU));
204 aocmu_reg_update_wait();
205 }
206
207 return 0;
208 }
209
hal_cmu_clock_disable(enum HAL_CMU_MOD_ID_T id)210 int hal_cmu_clock_disable(enum HAL_CMU_MOD_ID_T id)
211 {
212 if (id >= HAL_CMU_AON_A7) {
213 return 1;
214 }
215
216 if (id == HAL_CMU_MOD_P_TZC)
217 return 0;
218
219 if (id < HAL_CMU_MOD_P_CMU) {
220 cmu->HCLK_DISABLE = (1 << id);
221 } else if (id < HAL_CMU_MOD_O_SLEEP) {
222 cmu->PCLK_DISABLE = (1 << (id - HAL_CMU_MOD_P_CMU));
223 } else if (id < HAL_CMU_MOD_Q_NULL) {
224 cmu->OCLK_DISABLE = (1 << (id - HAL_CMU_MOD_O_SLEEP));
225 } else if (id < HAL_CMU_AON_A_CMU) {
226 cmu->QCLK_DISABLE = (1 << (id - HAL_CMU_MOD_Q_NULL));
227 } else {
228 aoncmu->MOD_CLK_DISABLE = (1 << (id - HAL_CMU_AON_A_CMU));
229 }
230
231 return 0;
232 }
233
hal_cmu_clock_get_status(enum HAL_CMU_MOD_ID_T id)234 enum HAL_CMU_CLK_STATUS_T hal_cmu_clock_get_status(enum HAL_CMU_MOD_ID_T id)
235 {
236 uint32_t status;
237
238 if (id >= HAL_CMU_AON_A7) {
239 return HAL_CMU_CLK_DISABLED;
240 }
241
242 if (id < HAL_CMU_MOD_P_CMU) {
243 status = cmu->HCLK_ENABLE & (1 << id);
244 } else if (id < HAL_CMU_MOD_O_SLEEP) {
245 status = cmu->PCLK_ENABLE & (1 << (id - HAL_CMU_MOD_P_CMU));
246 } else if (id < HAL_CMU_MOD_Q_NULL) {
247 status = cmu->OCLK_ENABLE & (1 << (id - HAL_CMU_MOD_O_SLEEP));
248 } else if (id < HAL_CMU_AON_A_CMU) {
249 status = cmu->QCLK_ENABLE & (1 << (id - HAL_CMU_MOD_Q_NULL));
250 } else {
251 status = aoncmu->MOD_CLK_ENABLE & (1 << (id - HAL_CMU_AON_A_CMU));
252 }
253
254 return status ? HAL_CMU_CLK_ENABLED : HAL_CMU_CLK_DISABLED;
255 }
256
hal_cmu_clock_set_mode(enum HAL_CMU_MOD_ID_T id,enum HAL_CMU_CLK_MODE_T mode)257 int hal_cmu_clock_set_mode(enum HAL_CMU_MOD_ID_T id, enum HAL_CMU_CLK_MODE_T mode)
258 {
259 __IO uint32_t *reg;
260 uint32_t val;
261 uint32_t lock;
262
263 if (id >= HAL_CMU_AON_A7) {
264 return 1;
265 }
266
267 if (id < HAL_CMU_MOD_P_CMU) {
268 reg = &cmu->HCLK_MODE;
269 val = (1 << id);
270 } else if (id < HAL_CMU_MOD_O_SLEEP) {
271 reg = &cmu->PCLK_MODE;
272 val = (1 << (id - HAL_CMU_MOD_P_CMU));
273 } else if (id < HAL_CMU_MOD_Q_NULL) {
274 reg = &cmu->OCLK_MODE;
275 val = (1 << (id - HAL_CMU_MOD_O_SLEEP));
276 } else if (id < HAL_CMU_AON_A_CMU) {
277 reg = &cmu->QCLK_MODE;
278 val = (1 << (id - HAL_CMU_MOD_Q_NULL));
279 } else {
280 reg = &aoncmu->MOD_CLK_MODE;
281 val = (1 << (id - HAL_CMU_AON_A_CMU));
282 }
283
284 lock = int_lock();
285 if (mode == HAL_CMU_CLK_MANUAL) {
286 *reg |= val;
287 } else {
288 *reg &= ~val;
289 }
290 int_unlock(lock);
291
292 return 0;
293 }
294
hal_cmu_clock_get_mode(enum HAL_CMU_MOD_ID_T id)295 enum HAL_CMU_CLK_MODE_T hal_cmu_clock_get_mode(enum HAL_CMU_MOD_ID_T id)
296 {
297 uint32_t mode;
298
299 if (id >= HAL_CMU_AON_A7) {
300 return HAL_CMU_CLK_AUTO;
301 }
302
303 if (id < HAL_CMU_MOD_P_CMU) {
304 mode = cmu->HCLK_MODE & (1 << id);
305 } else if (id < HAL_CMU_MOD_O_SLEEP) {
306 mode = cmu->PCLK_MODE & (1 << (id - HAL_CMU_MOD_P_CMU));
307 } else if (id < HAL_CMU_MOD_Q_NULL) {
308 mode = cmu->OCLK_MODE & (1 << (id - HAL_CMU_MOD_O_SLEEP));
309 } else if (id < HAL_CMU_AON_A_CMU) {
310 mode = cmu->QCLK_MODE & (1 << (id - HAL_CMU_MOD_Q_NULL));
311 } else {
312 mode = aoncmu->MOD_CLK_MODE & (1 << (id - HAL_CMU_AON_A_CMU));
313 }
314
315 return mode ? HAL_CMU_CLK_MANUAL : HAL_CMU_CLK_AUTO;
316 }
317
hal_cmu_reset_set(enum HAL_CMU_MOD_ID_T id)318 int hal_cmu_reset_set(enum HAL_CMU_MOD_ID_T id)
319 {
320 if (id >= HAL_CMU_MOD_QTY) {
321 return 1;
322 }
323
324 if (id == HAL_CMU_MOD_P_TZC)
325 return 0;
326
327 if (id < HAL_CMU_MOD_P_CMU) {
328 cmu->HRESET_SET = (1 << id);
329 } else if (id < HAL_CMU_MOD_O_SLEEP) {
330 cmu->PRESET_SET = (1 << (id - HAL_CMU_MOD_P_CMU));
331 } else if (id < HAL_CMU_MOD_Q_NULL) {
332 cmu->ORESET_SET = (1 << (id - HAL_CMU_MOD_O_SLEEP));
333 } else if (id < HAL_CMU_AON_A_CMU) {
334 cmu->QRESET_SET = (1 << (id - HAL_CMU_MOD_Q_NULL));
335 } else if (id < HAL_CMU_AON_A7) {
336 aoncmu->RESET_SET = (1 << (id - HAL_CMU_AON_A_CMU));
337 } else {
338 aoncmu->SOFT_RSTN_SET = (1 << (id - HAL_CMU_AON_A7));
339 }
340
341 return 0;
342 }
343
hal_cmu_reset_clear(enum HAL_CMU_MOD_ID_T id)344 int hal_cmu_reset_clear(enum HAL_CMU_MOD_ID_T id)
345 {
346 if (id >= HAL_CMU_MOD_QTY) {
347 return 1;
348 }
349
350 if (id < HAL_CMU_MOD_P_CMU) {
351 cmu->HRESET_CLR = (1 << id);
352 asm volatile("nop; nop; nop; nop; nop; nop; nop; nop;");
353 asm volatile("nop; nop; nop; nop;");
354 } else if (id < HAL_CMU_MOD_O_SLEEP) {
355 cmu->PRESET_CLR = (1 << (id - HAL_CMU_MOD_P_CMU));
356 asm volatile("nop; nop; nop; nop; nop; nop; nop; nop;");
357 asm volatile("nop; nop; nop; nop;");
358 } else if (id < HAL_CMU_MOD_Q_NULL) {
359 cmu->ORESET_CLR = (1 << (id - HAL_CMU_MOD_O_SLEEP));
360 asm volatile("nop; nop; nop; nop; nop; nop; nop; nop;");
361 asm volatile("nop; nop; nop; nop;");
362 } else if (id < HAL_CMU_AON_A_CMU) {
363 cmu->QRESET_CLR = (1 << (id - HAL_CMU_MOD_Q_NULL));
364 asm volatile("nop; nop; nop; nop; nop; nop; nop; nop;");
365 asm volatile("nop; nop; nop; nop;");
366 } else if (id < HAL_CMU_AON_A7) {
367 aoncmu->RESET_CLR = (1 << (id - HAL_CMU_AON_A_CMU));
368 aocmu_reg_update_wait();
369 } else {
370 aoncmu->SOFT_RSTN_CLR = (1 << (id - HAL_CMU_AON_A7));
371 aocmu_reg_update_wait();
372 }
373
374 return 0;
375 }
376
hal_cmu_reset_get_status(enum HAL_CMU_MOD_ID_T id)377 enum HAL_CMU_RST_STATUS_T hal_cmu_reset_get_status(enum HAL_CMU_MOD_ID_T id)
378 {
379 uint32_t status;
380
381 if (id >= HAL_CMU_MOD_QTY) {
382 return HAL_CMU_RST_SET;
383 }
384
385 if (id < HAL_CMU_MOD_P_CMU) {
386 status = cmu->HRESET_SET & (1 << id);
387 } else if (id < HAL_CMU_MOD_O_SLEEP) {
388 status = cmu->PRESET_SET & (1 << (id - HAL_CMU_MOD_P_CMU));
389 } else if (id < HAL_CMU_MOD_Q_NULL) {
390 status = cmu->ORESET_SET & (1 << (id - HAL_CMU_MOD_O_SLEEP));
391 } else if (id < HAL_CMU_AON_A_CMU) {
392 status = cmu->QRESET_SET & (1 << (id - HAL_CMU_MOD_Q_NULL));
393 } else if (id < HAL_CMU_AON_A7) {
394 status = aoncmu->RESET_SET & (1 << (id - HAL_CMU_AON_A_CMU));
395 } else {
396 status = aoncmu->SOFT_RSTN_SET & (1 << (id - HAL_CMU_AON_A7));
397 }
398
399 return status ? HAL_CMU_RST_CLR : HAL_CMU_RST_SET;
400 }
401
hal_cmu_reset_pulse(enum HAL_CMU_MOD_ID_T id)402 int hal_cmu_reset_pulse(enum HAL_CMU_MOD_ID_T id)
403 {
404 volatile int i;
405
406 if (id >= HAL_CMU_MOD_QTY) {
407 return 1;
408 }
409
410 if (hal_cmu_reset_get_status(id) == HAL_CMU_RST_SET) {
411 return hal_cmu_reset_clear(id);
412 }
413
414 if (id < HAL_CMU_MOD_P_CMU) {
415 cmu->HRESET_PULSE = (1 << id);
416 } else if (id < HAL_CMU_MOD_O_SLEEP) {
417 cmu->PRESET_PULSE = (1 << (id - HAL_CMU_MOD_P_CMU));
418 } else if (id < HAL_CMU_MOD_Q_NULL) {
419 cmu->ORESET_PULSE = (1 << (id - HAL_CMU_MOD_O_SLEEP));
420 } else if (id < HAL_CMU_AON_A_CMU) {
421 cmu->QRESET_PULSE = (1 << (id - HAL_CMU_MOD_Q_NULL));
422 } else if (id < HAL_CMU_AON_A7) {
423 aoncmu->RESET_PULSE = (1 << (id - HAL_CMU_AON_A_CMU));
424 // Total 3 CLK-26M cycles needed
425 // AOCMU runs in 26M clock domain and its read operations consume at least 1 26M-clock cycle.
426 // (Whereas its write operations will finish at 1 HCLK cycle -- finish once in async bridge fifo)
427 aoncmu->CHIP_ID;
428 aoncmu->CHIP_ID;
429 aoncmu->CHIP_ID;
430 } else {
431 aoncmu->SOFT_RSTN_PULSE = (1 << (id - HAL_CMU_AON_A7));
432 // Total 3 CLK-26M cycles needed
433 // AOCMU runs in 26M clock domain and its read operations consume at least 1 26M-clock cycle.
434 // (Whereas its write operations will finish at 1 HCLK cycle -- finish once in async bridge fifo)
435 aoncmu->CHIP_ID;
436 aoncmu->CHIP_ID;
437 aoncmu->CHIP_ID;
438 }
439 // Delay 5+ PCLK cycles (10+ HCLK cycles)
440 for (i = 0; i < 3; i++);
441
442 return 0;
443 }
444
hal_cmu_timer_set_div(enum HAL_CMU_TIMER_ID_T id,uint32_t div)445 int hal_cmu_timer_set_div(enum HAL_CMU_TIMER_ID_T id, uint32_t div)
446 {
447 uint32_t lock;
448
449 if (div < 1) {
450 return 1;
451 }
452
453 div -= 1;
454 if ((div & (CMU_CFG_DIV_TIMER00_MASK >> CMU_CFG_DIV_TIMER00_SHIFT)) != div) {
455 return 1;
456 }
457
458 lock = int_lock();
459 if (id == HAL_CMU_TIMER_ID_00) {
460 cmu->TIMER0_CLK = SET_BITFIELD(cmu->TIMER0_CLK, CMU_CFG_DIV_TIMER00, div);
461 } else if (id == HAL_CMU_TIMER_ID_01) {
462 cmu->TIMER0_CLK = SET_BITFIELD(cmu->TIMER0_CLK, CMU_CFG_DIV_TIMER01, div);
463 } else if (id == HAL_CMU_TIMER_ID_10) {
464 cmu->TIMER1_CLK = SET_BITFIELD(cmu->TIMER1_CLK, CMU_CFG_DIV_TIMER10, div);
465 } else if (id == HAL_CMU_TIMER_ID_11) {
466 cmu->TIMER1_CLK = SET_BITFIELD(cmu->TIMER1_CLK, CMU_CFG_DIV_TIMER11, div);
467 } else if (id == HAL_CMU_TIMER_ID_20) {
468 cmu->TIMER2_CLK = SET_BITFIELD(cmu->TIMER2_CLK, CMU_CFG_DIV_TIMER20, div);
469 } else if (id == HAL_CMU_TIMER_ID_21) {
470 cmu->TIMER2_CLK = SET_BITFIELD(cmu->TIMER2_CLK, CMU_CFG_DIV_TIMER21, div);
471 }
472 int_unlock(lock);
473
474 return 0;
475 }
476
hal_cmu_timer0_select_fast(void)477 void hal_cmu_timer0_select_fast(void)
478 {
479 uint32_t lock;
480
481 lock = int_lock();
482 // 6.5M
483 cmu->PERIPH_CLK |= (1 << CMU_SEL_TIMER_FAST_SHIFT);
484 // AON Timer
485 aoncmu->TIMER_CLK |= AON_CMU_SEL_TIMER_FAST;
486 int_unlock(lock);
487 }
488
hal_cmu_timer0_select_slow(void)489 void BOOT_TEXT_FLASH_LOC hal_cmu_timer0_select_slow(void)
490 {
491 uint32_t lock;
492
493 lock = int_lock();
494 // 16K
495 cmu->PERIPH_CLK &= ~(1 << CMU_SEL_TIMER_FAST_SHIFT);
496 // AON Timer
497 aoncmu->TIMER_CLK &= ~AON_CMU_SEL_TIMER_FAST;
498 int_unlock(lock);
499 }
500
hal_cmu_timer1_select_fast(void)501 void BOOT_TEXT_FLASH_LOC hal_cmu_timer1_select_fast(void)
502 {
503 uint32_t lock;
504
505 lock = int_lock();
506 // 6.5M
507 cmu->PERIPH_CLK |= (1 << (CMU_SEL_TIMER_FAST_SHIFT + 1));
508 int_unlock(lock);
509 }
510
hal_cmu_timer1_select_slow(void)511 void BOOT_TEXT_FLASH_LOC hal_cmu_timer1_select_slow(void)
512 {
513 uint32_t lock;
514
515 lock = int_lock();
516 // 16K
517 cmu->PERIPH_CLK &= ~(1 << (CMU_SEL_TIMER_FAST_SHIFT + 1));
518 int_unlock(lock);
519 }
520
hal_cmu_timer2_select_fast(void)521 void hal_cmu_timer2_select_fast(void)
522 {
523 uint32_t lock;
524
525 lock = int_lock();
526 // 6.5M
527 cmu->PERIPH_CLK |= (1 << (CMU_SEL_TIMER_FAST_SHIFT + 2));
528 int_unlock(lock);
529 }
530
hal_cmu_timer2_select_slow(void)531 void hal_cmu_timer2_select_slow(void)
532 {
533 uint32_t lock;
534
535 lock = int_lock();
536 // 16K
537 cmu->PERIPH_CLK &= ~(1 << (CMU_SEL_TIMER_FAST_SHIFT + 2));
538 int_unlock(lock);
539 }
540
hal_cmu_dsp_timer0_select_fast(void)541 void hal_cmu_dsp_timer0_select_fast(void)
542 {
543 uint32_t lock;
544
545 lock = int_lock();
546 // 6.5M
547 cmu->DSP_DIV |= (1 << CMU_SEL_TIMER_FAST_AP_SHIFT);
548 int_unlock(lock);
549 }
550
hal_cmu_dsp_timer0_select_slow(void)551 void hal_cmu_dsp_timer0_select_slow(void)
552 {
553 uint32_t lock;
554
555 lock = int_lock();
556 // 16K
557 cmu->DSP_DIV &= ~(1 << CMU_SEL_TIMER_FAST_AP_SHIFT);
558 int_unlock(lock);
559 }
560
hal_cmu_dsp_timer1_select_fast(void)561 void hal_cmu_dsp_timer1_select_fast(void)
562 {
563 uint32_t lock;
564
565 lock = int_lock();
566 // 6.5M
567 cmu->DSP_DIV |= (1 << (CMU_SEL_TIMER_FAST_AP_SHIFT + 1));
568 int_unlock(lock);
569 }
570
hal_cmu_dsp_timer1_select_slow(void)571 void hal_cmu_dsp_timer1_select_slow(void)
572 {
573 uint32_t lock;
574
575 lock = int_lock();
576 // 16K
577 cmu->DSP_DIV &= ~(1 << (CMU_SEL_TIMER_FAST_AP_SHIFT + 1));
578 int_unlock(lock);
579 }
580
hal_cmu_sdmmc_set_pll_div(uint32_t div)581 int hal_cmu_sdmmc_set_pll_div(uint32_t div)
582 {
583 uint32_t lock;
584 if (div < 2) {
585 return 1;
586 }
587 div -= 2;
588 if ((div & (CMU_CFG_DIV_SDMMC_MASK >> CMU_CFG_DIV_SDMMC_SHIFT)) != div) {
589 return 1;
590 }
591 lock = int_lock();
592 cmu->PERIPH_CLK = SET_BITFIELD(cmu->PERIPH_CLK, CMU_CFG_DIV_SDMMC, div) |
593 CMU_SEL_OSCX2_SDMMC | CMU_SEL_PLL_SDMMC | CMU_EN_PLL_SDMMC;
594 int_unlock(lock);
595 return 0;
596 }
597
hal_cmu_flash_set_freq(enum HAL_CMU_FREQ_T freq)598 int BOOT_TEXT_SRAM_LOC hal_cmu_flash_set_freq(enum HAL_CMU_FREQ_T freq)
599 {
600 uint32_t set;
601 uint32_t clr;
602 uint32_t lock;
603 bool clk_en;
604
605 if (freq >= HAL_CMU_FREQ_QTY) {
606 return 1;
607 }
608 if (freq == HAL_CMU_FREQ_32K) {
609 return 2;
610 }
611
612 switch (freq) {
613 case HAL_CMU_FREQ_26M:
614 set = 0;
615 clr = AON_CMU_RSTN_DIV_FLS | AON_CMU_BYPASS_DIV_FLS | AON_CMU_SEL_FLS_OSCX2 | AON_CMU_SEL_FLS_OSCX4 | AON_CMU_SEL_FLS_PLL;
616 break;
617 case HAL_CMU_FREQ_52M:
618 set = AON_CMU_SEL_FLS_OSCX2;
619 clr = AON_CMU_RSTN_DIV_FLS | AON_CMU_BYPASS_DIV_FLS | AON_CMU_SEL_FLS_OSCX4 | AON_CMU_SEL_FLS_PLL;
620 break;
621 case HAL_CMU_FREQ_78M:
622 case HAL_CMU_FREQ_104M:
623 #ifdef OSC_26M_X4_AUD2BB
624 set = AON_CMU_SEL_FLS_OSCX4;
625 clr = AON_CMU_RSTN_DIV_FLS | AON_CMU_BYPASS_DIV_FLS | AON_CMU_SEL_FLS_OSCX2 | AON_CMU_SEL_FLS_PLL;
626 break;
627 #endif
628 case HAL_CMU_FREQ_156M:
629 case HAL_CMU_FREQ_208M:
630 case HAL_CMU_FREQ_260M:
631 set = AON_CMU_RSTN_DIV_FLS | AON_CMU_SEL_FLS_PLL;
632 clr = AON_CMU_CFG_DIV_FLS_MASK | AON_CMU_BYPASS_DIV_FLS | AON_CMU_SEL_FLS_OSCX2 | AON_CMU_SEL_FLS_OSCX4;
633 if (0) {
634 #ifndef OSC_26M_X4_AUD2BB
635 } else if (freq <= HAL_CMU_FREQ_78M) {
636 set |= AON_CMU_CFG_DIV_FLS(3);
637 } else if (freq <= HAL_CMU_FREQ_104M) {
638 set |= AON_CMU_CFG_DIV_FLS(2);
639 #endif
640 } else if (freq <= HAL_CMU_FREQ_156M) {
641 set |= AON_CMU_CFG_DIV_FLS(1);
642 } else { // 208M or 260M
643 set |= AON_CMU_CFG_DIV_FLS(0);
644 }
645 break;
646 case HAL_CMU_FREQ_390M:
647 case HAL_CMU_FREQ_780M:
648 default:
649 set = AON_CMU_BYPASS_DIV_FLS | AON_CMU_SEL_FLS_PLL;
650 clr = AON_CMU_RSTN_DIV_FLS | AON_CMU_SEL_FLS_OSCX2 | AON_CMU_SEL_FLS_OSCX4;
651 break;
652 };
653
654 lock = int_lock();
655 clk_en = !!(cmu->OCLK_DISABLE & SYS_OCLK_FLASH);
656 if (clk_en) {
657 cmu->OCLK_DISABLE = SYS_OCLK_FLASH;
658 cmu->HCLK_DISABLE = SYS_HCLK_FLASH;
659 // Wait at least 2 cycles of flash controller. The min freq is 26M, the same as AON.
660 aocmu_reg_update_wait();
661 aocmu_reg_update_wait();
662 }
663 aoncmu->FLS_PSR_CLK = (aoncmu->FLS_PSR_CLK & ~clr) | set;
664 if (clk_en) {
665 cmu->HCLK_ENABLE = SYS_HCLK_FLASH;
666 cmu->OCLK_ENABLE = SYS_OCLK_FLASH;
667 }
668 int_unlock(lock);
669
670 return 0;
671 }
672
hal_cmu_flash1_set_freq(enum HAL_CMU_FREQ_T freq)673 int BOOT_TEXT_SRAM_LOC hal_cmu_flash1_set_freq(enum HAL_CMU_FREQ_T freq)
674 {
675 aoncmu->FLASH_IOCFG |= AON_CMU_PU_FLASH1_IO;
676 //TODO: 2003 flash0 and flash1 use same clock source, so don't change clk freq in case of flash0 error
677 #ifdef ROM_BUILD //2003 rom only use one flash
678 return hal_cmu_flash_set_freq(freq);
679 #else
680 return 0;
681 #endif
682 }
683
hal_cmu_mem_set_freq(enum HAL_CMU_FREQ_T freq)684 int hal_cmu_mem_set_freq(enum HAL_CMU_FREQ_T freq)
685 {
686 uint32_t set;
687 uint32_t clr;
688 uint32_t lock;
689 bool clk_en;
690
691 if (freq >= HAL_CMU_FREQ_QTY) {
692 return 1;
693 }
694 if (freq == HAL_CMU_FREQ_32K) {
695 return 2;
696 }
697
698 // 2003 psram ctrl use 400M clk from bbpsram
699 switch (freq) {
700 case HAL_CMU_FREQ_26M:
701 set = 0;
702 clr = AON_CMU_RSTN_DIV_PSR | AON_CMU_BYPASS_DIV_PSR | AON_CMU_SEL_PSR_OSCX2 | AON_CMU_SEL_PSR_OSCX4 | AON_CMU_SEL_PSR_PLL;
703 break;
704 case HAL_CMU_FREQ_52M:
705 set = AON_CMU_SEL_PSR_OSCX2;
706 clr = AON_CMU_RSTN_DIV_PSR | AON_CMU_BYPASS_DIV_PSR | AON_CMU_SEL_PSR_OSCX4 | AON_CMU_SEL_PSR_PLL;
707 break;
708 case HAL_CMU_FREQ_78M:
709 case HAL_CMU_FREQ_104M:
710 #ifdef OSC_26M_X4_AUD2BB
711 set = AON_CMU_SEL_PSR_OSCX4;
712 clr = AON_CMU_RSTN_DIV_PSR | AON_CMU_BYPASS_DIV_PSR | AON_CMU_SEL_PSR_OSCX2 | AON_CMU_SEL_PSR_PLL;
713 break;
714 #endif
715 case HAL_CMU_FREQ_156M:
716 case HAL_CMU_FREQ_208M:
717 case HAL_CMU_FREQ_260M:
718 set = AON_CMU_RSTN_DIV_PSR | AON_CMU_SEL_PSR_PLL | AON_CMU_SEL_PSR_INT;
719 clr = AON_CMU_CFG_DIV_PSR_MASK | AON_CMU_BYPASS_DIV_PSR | AON_CMU_SEL_PSR_OSCX2 | AON_CMU_SEL_PSR_OSCX4;
720 if (0) {
721 #ifndef OSC_26M_X4_AUD2BB
722 } else if (freq <= HAL_CMU_FREQ_78M) {
723 set |= AON_CMU_CFG_DIV_PSR(3);
724 } else if (freq <= HAL_CMU_FREQ_104M) {
725 set |= AON_CMU_CFG_DIV_PSR(2);
726 #endif
727 } else if (freq <= HAL_CMU_FREQ_156M) {
728 set |= AON_CMU_CFG_DIV_PSR(1);
729 } else { // 208M or 260M
730 set |= AON_CMU_CFG_DIV_PSR(0);
731 }
732 break;
733 case HAL_CMU_FREQ_390M:
734 case HAL_CMU_FREQ_780M:
735 default:
736 set = AON_CMU_BYPASS_DIV_PSR | AON_CMU_SEL_PSR_PLL | AON_CMU_SEL_PSR_INT;
737 clr = AON_CMU_RSTN_DIV_PSR | AON_CMU_SEL_PSR_OSCX2 | AON_CMU_SEL_PSR_OSCX4;
738 break;
739 };
740
741 lock = int_lock();
742 clk_en = !!(cmu->OCLK_DISABLE & SYS_OCLK_PSRAM200);
743 if (clk_en) {
744 aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_TOP_PHY_PS_DISABLE;
745 cmu->OCLK_DISABLE = SYS_OCLK_PSRAM200;
746 cmu->HCLK_DISABLE = SYS_HCLK_PSRAM200;
747 // Wait at least 2 cycles of psram controller. The min freq is 26M, the same as AON.
748 aocmu_reg_update_wait();
749 aocmu_reg_update_wait();
750 }
751 aoncmu->FLS_PSR_CLK = (aoncmu->FLS_PSR_CLK & ~clr) | set;
752 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_PHY_PS_ENABLE;
753 if (clk_en) {
754 cmu->HCLK_ENABLE = SYS_HCLK_PSRAM200;
755 cmu->OCLK_ENABLE = SYS_OCLK_PSRAM200;
756 }
757 int_unlock(lock);
758
759 return 0;
760 }
761
hal_cmu_ddr_clock_enable()762 int hal_cmu_ddr_clock_enable()
763 {
764 uint32_t set;
765 uint32_t clr;
766 uint32_t lock;
767 bool clk_en;
768
769 hal_cmu_pll_enable(HAL_CMU_PLL_DDR, HAL_CMU_PLL_USER_PSRAM);
770 #if 1
771 //pxclk use xclk, works in synchronous mode
772 //a7 can change sys freq in this mode
773 cmu->PERIPH_CLK &= ~CMU_SEL_PSRAMX2;
774 *(volatile uint32_t *)(GPV_PSRAM1G_BASE+0x42020) = 0;
775 #else
776 //pxclk use psram2, works in asynchronous mode
777 *(volatile uint32_t *)(GPV_PSRAM1G_BASE+0x42020) = 4;
778 cmu->PERIPH_CLK |= CMU_SEL_PSRAMX2;
779 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_PSRAMX2_ENABLE;
780 #endif
781
782 // PSRAMUHS can't use ddr pll divider
783 set = AON_CMU_BYPASS_DIV_DDR | AON_CMU_SEL_DDR_PLL | AON_CMU_CFG_DIV_PSRAMX2(2);
784 clr = AON_CMU_RSTN_DIV_DDR | AON_CMU_SEL_DDR_OSCX2 | AON_CMU_SEL_DDR_OSCX4 | AON_CMU_CFG_DIV_PSRAMX2_MASK;
785
786 lock = int_lock();
787 clk_en = !!(cmu->OCLK_DISABLE & SYS_OCLK_PSRAM1G);
788 if (clk_en) {
789 cmu->OCLK_DISABLE = SYS_OCLK_PSRAM1G;
790 cmu->HCLK_DISABLE = SYS_HCLK_PSRAM1G;
791 // Wait at least 2 cycles of psram controller. The min freq is 26M, the same as AON.
792 aocmu_reg_update_wait();
793 aocmu_reg_update_wait();
794 }
795 aoncmu->DDR_CLK = (aoncmu->DDR_CLK & ~clr) | set;
796
797 cmu->XCLK_ENABLE = SYS_XCLK_PSRAM1G | SYS_XCLK_PSRAM1GMX | SYS_XCLK_GPV_PSRAM1G;
798 cmu->HCLK_ENABLE = SYS_HCLK_PSRAM1G;
799 cmu->OCLK_ENABLE = SYS_OCLK_PSRAM1G;
800
801 int_unlock(lock);
802
803 return 0;
804 }
805
hal_cmu_ddr_clock_disable()806 void hal_cmu_ddr_clock_disable()
807 {
808 cmu->XCLK_DISABLE = SYS_XCLK_PSRAM1G | SYS_XCLK_PSRAM1GMX | SYS_XCLK_GPV_PSRAM1G;
809 cmu->OCLK_DISABLE = SYS_OCLK_PSRAM1G;
810 cmu->HCLK_DISABLE = SYS_HCLK_PSRAM1G;
811 hal_cmu_pll_disable(HAL_CMU_PLL_DDR, HAL_CMU_PLL_USER_PSRAM);
812 }
813
hal_cmu_ddr_reset_set()814 void hal_cmu_ddr_reset_set()
815 {
816 cmu->XRESET_SET = SYS_XRST_PSRAM1G | SYS_XRST_PSRAM1GMX | SYS_XRST_GPV_PSRAM1G;
817 cmu->ORESET_SET = SYS_ORST_PSRAM1G;
818 cmu->HRESET_SET = SYS_HRST_PSRAM1G;
819 }
820
hal_cmu_ddr_reset_clear()821 void hal_cmu_ddr_reset_clear()
822 {
823 cmu->XRESET_CLR = SYS_XRST_PSRAM1G | SYS_XRST_PSRAM1GMX | SYS_XRST_GPV_PSRAM1G;
824 cmu->ORESET_CLR = SYS_ORST_PSRAM1G;
825 cmu->HRESET_CLR = SYS_HRST_PSRAM1G;
826 }
827
828 int hal_cmu_dsp_set_freq(enum HAL_CMU_FREQ_T freq);
829
hal_cmu_dsi_phy_reset_set(void)830 void hal_cmu_dsi_phy_reset_set(void)
831 {
832 hal_cmu_reset_set(HAL_CMU_MOD_Q_DSI_32K);
833 hal_cmu_reset_set(HAL_CMU_MOD_Q_DSI_PN);
834 hal_cmu_reset_set(HAL_CMU_MOD_Q_DSI_TV);
835 hal_cmu_reset_set(HAL_CMU_MOD_Q_DSI_PIX);
836 hal_cmu_reset_set(HAL_CMU_MOD_Q_DSI_DSI);
837 }
838
hal_cmu_dsi_phy_reset_clear(void)839 void hal_cmu_dsi_phy_reset_clear(void)
840 {
841 // TODO: Move clock enable APIs out
842 hal_cmu_clock_enable(HAL_CMU_MOD_Q_DSI_32K);
843 hal_cmu_clock_enable(HAL_CMU_MOD_Q_DSI_PN);
844 hal_cmu_clock_enable(HAL_CMU_MOD_Q_DSI_TV);
845 hal_cmu_clock_enable(HAL_CMU_MOD_Q_DSI_PIX);
846 hal_cmu_clock_enable(HAL_CMU_MOD_Q_DSI_DSI);
847
848 hal_cmu_reset_clear(HAL_CMU_MOD_Q_DSI_32K);
849 hal_cmu_reset_clear(HAL_CMU_MOD_Q_DSI_PN);
850 hal_cmu_reset_clear(HAL_CMU_MOD_Q_DSI_TV);
851 hal_cmu_reset_clear(HAL_CMU_MOD_Q_DSI_PIX);
852 hal_cmu_reset_clear(HAL_CMU_MOD_Q_DSI_DSI);
853 }
854
hal_cmu_dsi_clock_enable(void)855 void hal_cmu_dsi_clock_enable(void)
856 {
857 #if !defined(DSP_ENABLE) && !defined(CHIP_BEST2003_DSP)
858 hal_cmu_dsp_clock_enable();
859 hal_cmu_dsp_reset_clear();
860 hal_sys_timer_delay(US_TO_TICKS(10));
861 #endif
862 hal_cmu_dsp_set_freq(HAL_CMU_FREQ_780M);
863 cmu->DSP_DIV = SET_BITFIELD(cmu->DSP_DIV, CMU_CFG_DIV_APCLK, 0x0);
864 hal_cmu_pll_enable(HAL_CMU_PLL_DSI, HAL_CMU_PLL_USER_DSI);
865 cmu->APCLK_ENABLE = SYS_APCLK_DISPLAY;
866 aoncmu->MIPI_CLK = AON_CMU_EN_CLK_PIX_DSI | AON_CMU_POL_CLK_DSI_IN |
867 SET_BITFIELD(aoncmu->MIPI_CLK, AON_CMU_CFG_DIV_PIX_DSI, 0x4);
868 cmu->QCLK_ENABLE = SYS_QCLK_DSI_DSI | SYS_QCLK_DSI_PIX;
869 hal_sys_timer_delay_us(10);
870 hal_cmu_dsi_reset_set();//QR DSI/PIX CLK bit 4/5; APR APB CLK bit 8
871 hal_sys_timer_delay(US_TO_TICKS(10));
872 hal_cmu_dsi_reset_clear();
873 }
874
hal_cmu_dsi_clock_enable_v2(uint8_t pixel_div)875 void hal_cmu_dsi_clock_enable_v2(uint8_t pixel_div)
876 {
877 hal_cmu_dsp_set_freq(HAL_CMU_FREQ_780M);
878 cmu->DSP_DIV = SET_BITFIELD(cmu->DSP_DIV, CMU_CFG_DIV_APCLK, 0x0);
879 hal_cmu_pll_enable(HAL_CMU_PLL_DSI, HAL_CMU_PLL_USER_DSI);
880 cmu->APCLK_ENABLE = SYS_APCLK_DISPLAY;
881 aoncmu->MIPI_CLK = AON_CMU_EN_CLK_PIX_DSI | AON_CMU_POL_CLK_DSI_IN |
882 SET_BITFIELD(aoncmu->MIPI_CLK, AON_CMU_CFG_DIV_PIX_DSI, pixel_div);
883 cmu->QCLK_ENABLE = SYS_QCLK_DSI_DSI | SYS_QCLK_DSI_PIX;
884 hal_sys_timer_delay_us(10);
885 }
886
hal_cmu_dsi_clock_disable(void)887 void hal_cmu_dsi_clock_disable(void)
888 {
889 aoncmu->MIPI_CLK &= ~(AON_CMU_EN_CLK_PIX_DSI | AON_CMU_POL_CLK_DSI_IN);
890 cmu->QCLK_DISABLE = SYS_QCLK_DSI_DSI | SYS_QCLK_DSI_PIX;
891 cmu->APCLK_DISABLE = SYS_APCLK_DISPLAY;
892 hal_cmu_pll_disable(HAL_CMU_PLL_DSI, HAL_CMU_PLL_USER_DSI);
893 }
894
hal_cmu_dsi_reset_set(void)895 void hal_cmu_dsi_reset_set(void)
896 {
897 cmu->QRESET_SET = SYS_QRST_DSI_DSI | SYS_QRST_DSI_PIX;
898 cmu->APRESET_SET = SYS_APRST_DISPLAY;
899 }
900
hal_cmu_dsi_reset_clear(void)901 void hal_cmu_dsi_reset_clear(void)
902 {
903 cmu->APRESET_CLR = SYS_APRST_DISPLAY;
904 cmu->QRESET_CLR = SYS_QRST_DSI_DSI | SYS_QRST_DSI_PIX;
905 hal_sys_timer_delay_us(10);
906 }
907
hal_cmu_dsi_sleep(void)908 void hal_cmu_dsi_sleep(void)
909 {
910 hal_cmu_dsi_clock_disable();
911 }
912
hal_cmu_dsi_wakeup(void)913 void hal_cmu_dsi_wakeup(void)
914 {
915 hal_cmu_dsi_clock_enable();
916 }
917
hal_cmu_lcdc_clock_enable(void)918 void hal_cmu_lcdc_clock_enable(void)
919 {
920 hal_cmu_lcdc_reset_clear();
921 cmu->XCLK_ENABLE = SYS_XCLK_DSI | SYS_XCLK_DISPLAYX | SYS_XCLK_DISPLAYH;
922 cmu->QCLK_ENABLE = SYS_QCLK_DSI_32K | SYS_QCLK_DSI_PN | SYS_QCLK_DSI_TV;
923
924 hal_cmu_clock_enable(HAL_CMU_MOD_Q_DSI_32K);
925 hal_cmu_clock_enable(HAL_CMU_MOD_Q_DSI_PN);
926 hal_cmu_clock_enable(HAL_CMU_MOD_Q_DSI_TV);
927 hal_cmu_clock_enable(HAL_CMU_MOD_Q_DSI_PIX);
928 hal_cmu_clock_enable(HAL_CMU_MOD_Q_DSI_DSI);
929 hal_cmu_reset_clear(HAL_CMU_MOD_Q_DSI_32K);
930 hal_cmu_reset_clear(HAL_CMU_MOD_Q_DSI_PN);
931 hal_cmu_reset_clear(HAL_CMU_MOD_Q_DSI_TV);
932 hal_cmu_reset_clear(HAL_CMU_MOD_Q_DSI_PIX);
933 hal_cmu_reset_clear(HAL_CMU_MOD_Q_DSI_DSI);
934 }
935
hal_cmu_lcdc_clock_disable(void)936 void hal_cmu_lcdc_clock_disable(void)
937 {
938 cmu->QCLK_DISABLE = SYS_QCLK_DSI_32K | SYS_QCLK_DSI_PN | SYS_QCLK_DSI_TV;
939 cmu->XCLK_DISABLE = SYS_XCLK_DSI | SYS_XCLK_DISPLAYX | SYS_XCLK_DISPLAYH;
940 }
941
hal_cmu_lcdc_reset_set(void)942 void hal_cmu_lcdc_reset_set(void)
943 {
944 cmu->QRESET_SET = SYS_QRST_DSI_32K | SYS_QRST_DSI_PN | SYS_QRST_DSI_TV;
945 cmu->XRESET_SET = SYS_XRST_DSI | SYS_XRST_DISPLAYX | SYS_XRST_DISPLAYH;
946 }
947
hal_cmu_lcdc_reset_clear(void)948 void hal_cmu_lcdc_reset_clear(void)
949 {
950 cmu->XRESET_CLR = SYS_XRST_DSI | SYS_XRST_DISPLAYX | SYS_XRST_DISPLAYH;
951 cmu->QRESET_CLR = SYS_QRST_DSI_32K | SYS_QRST_DSI_PN | SYS_QRST_DSI_TV;
952 hal_sys_timer_delay_us(10);
953 }
954
hal_cmu_lcdc_sleep(void)955 void hal_cmu_lcdc_sleep(void)
956 {
957 hal_cmu_lcdc_clock_disable();
958 }
959
hal_cmu_lcdc_wakeup(void)960 void hal_cmu_lcdc_wakeup(void)
961 {
962 hal_cmu_lcdc_clock_enable();
963 }
hal_cmu_csi_clock_enable(void)964 void hal_cmu_csi_clock_enable(void)
965 {
966 cmu->DSP_DIV = SET_BITFIELD(cmu->DSP_DIV, CMU_CFG_DIV_APCLK, 0x0);
967 aoncmu->MIPI_CLK = AON_CMU_EN_CLK_PIX_CSI | AON_CMU_POL_CLK_CSI_IN |
968 SET_BITFIELD(aoncmu->MIPI_CLK, AON_CMU_CFG_DIV_PIX_CSI, 0x7); //0xa:240M 1lane
969 cmu->APCLK_ENABLE = SYS_APCLK_CSI;
970 cmu->XCLK_ENABLE = SYS_XCLK_CSI;
971 cmu->QCLK_ENABLE = SYS_QCLK_CSI_LANE | SYS_QCLK_CSI_PIX | SYS_QCLK_CSI_LANG;
972
973 hal_cmu_clock_set_mode(HAL_CMU_MOD_Q_CSI_LANE, HAL_CMU_CLK_AUTO);
974 hal_cmu_clock_set_mode(HAL_CMU_MOD_Q_CSI_PIX, HAL_CMU_CLK_AUTO);
975 hal_cmu_clock_set_mode(HAL_CMU_MOD_Q_CSI_LANG, HAL_CMU_CLK_AUTO);
976 }
977
hal_cmu_csi_clock_disable(void)978 void hal_cmu_csi_clock_disable(void)
979 {
980 cmu->XCLK_DISABLE = SYS_XCLK_CSI;
981 cmu->QCLK_ENABLE = SYS_QCLK_CSI_LANE | SYS_QCLK_CSI_PIX | SYS_QCLK_CSI_LANG;
982 cmu->APCLK_DISABLE = SYS_APCLK_CSI;
983 aoncmu->MIPI_CLK &= ~(AON_CMU_EN_CLK_PIX_CSI | AON_CMU_POL_CLK_CSI_IN);
984 }
985
hal_cmu_csi_reset_set(void)986 void hal_cmu_csi_reset_set(void)
987 {
988 cmu->XRESET_SET = SYS_XRST_CSI;
989 cmu->QRESET_SET = SYS_QRST_CSI_LANE | SYS_QRST_CSI_PIX | SYS_QRST_CSI_LANG;
990 cmu->APRESET_SET = SYS_APRST_CSI;
991 }
992
hal_cmu_csi_reset_clear(void)993 void hal_cmu_csi_reset_clear(void)
994 {
995 cmu->APRESET_CLR = SYS_APRST_CSI;
996 cmu->XRESET_CLR = SYS_XRST_CSI;
997 cmu->QRESET_CLR = SYS_QRST_CSI_LANE | SYS_QRST_CSI_PIX | SYS_QRST_CSI_LANG;
998 hal_sys_timer_delay_us(10);
999 }
1000
1001 #ifdef LOW_SYS_FREQ
1002 #ifdef LOW_SYS_FREQ_6P5M
hal_cmu_fast_timer_offline(void)1003 int hal_cmu_fast_timer_offline(void)
1004 {
1005 return (cmu_sys_freq == HAL_CMU_FREQ_6P5M);
1006 }
1007 #endif
1008 #endif
1009
1010 #ifdef CHIP_BEST2003_DSP
1011
1012 int hal_cmu_sys_set_freq(enum HAL_CMU_FREQ_T freq) __attribute__((alias("hal_cmu_dsp_set_freq")));
1013
1014 enum HAL_CMU_FREQ_T hal_cmu_sys_get_freq(void) __attribute__((alias("hal_cmu_dsp_get_freq")));
1015
1016 #else // !CHIP_BEST2003_DSP
1017
hal_cmu_sys_set_freq(enum HAL_CMU_FREQ_T freq)1018 int hal_cmu_sys_set_freq(enum HAL_CMU_FREQ_T freq)
1019 {
1020 uint32_t enable;
1021 uint32_t disable;
1022 int div;
1023 uint32_t lock;
1024
1025 if (freq >= HAL_CMU_FREQ_QTY) {
1026 return 1;
1027 }
1028
1029 #ifdef LOW_SYS_FREQ
1030 cmu_sys_freq = freq;
1031 #endif
1032
1033 div = -1;
1034
1035 switch (freq) {
1036 case HAL_CMU_FREQ_32K:
1037 enable = 0;
1038 disable = CMU_RSTN_DIV_MCU_DISABLE | CMU_BYPASS_DIV_MCU_DISABLE | CMU_SEL_MCU_OSC_4_DISABLE | CMU_SEL_MCU_OSC_2_DISABLE |
1039 CMU_SEL_MCU_OSCX4_DISABLE | CMU_SEL_MCU_SLOW_DISABLE | CMU_SEL_MCU_FAST_DISABLE | CMU_SEL_MCU_PLL_DISABLE;
1040 break;
1041 case HAL_CMU_FREQ_6P5M:
1042 #if defined(LOW_SYS_FREQ) && defined(LOW_SYS_FREQ_6P5M)
1043 enable = CMU_SEL_MCU_OSC_4_ENABLE;
1044 disable = CMU_RSTN_DIV_MCU_DISABLE | CMU_BYPASS_DIV_MCU_DISABLE |
1045 CMU_SEL_MCU_OSCX4_DISABLE | CMU_SEL_MCU_SLOW_DISABLE | CMU_SEL_MCU_FAST_DISABLE | CMU_SEL_MCU_PLL_DISABLE;
1046 break;
1047 #endif
1048 case HAL_CMU_FREQ_13M:
1049 #ifdef LOW_SYS_FREQ
1050 enable = CMU_SEL_MCU_OSC_2_ENABLE | CMU_SEL_MCU_SLOW_ENABLE;
1051 disable = CMU_RSTN_DIV_MCU_DISABLE | CMU_BYPASS_DIV_MCU_DISABLE |
1052 CMU_SEL_MCU_OSCX4_DISABLE | CMU_SEL_MCU_FAST_DISABLE | CMU_SEL_MCU_PLL_DISABLE;
1053 break;
1054 #endif
1055 case HAL_CMU_FREQ_26M:
1056 enable = CMU_SEL_MCU_SLOW_ENABLE;
1057 disable = CMU_RSTN_DIV_MCU_DISABLE | CMU_BYPASS_DIV_MCU_DISABLE | CMU_SEL_MCU_OSC_2_ENABLE |
1058 CMU_SEL_MCU_OSCX4_DISABLE | CMU_SEL_MCU_FAST_DISABLE | CMU_SEL_MCU_PLL_DISABLE;
1059 break;
1060 case HAL_CMU_FREQ_52M:
1061 enable = CMU_SEL_MCU_FAST_ENABLE;
1062 disable = CMU_RSTN_DIV_MCU_DISABLE | CMU_BYPASS_DIV_MCU_DISABLE |
1063 CMU_SEL_MCU_OSCX4_DISABLE | CMU_SEL_MCU_PLL_DISABLE;
1064 break;
1065 case HAL_CMU_FREQ_78M:
1066 case HAL_CMU_FREQ_104M:
1067 #ifdef OSC_26M_X4_AUD2BB
1068 enable = CMU_SEL_MCU_OSCX4_ENABLE | CMU_SEL_MCU_FAST_ENABLE;
1069 disable = CMU_RSTN_DIV_MCU_DISABLE | CMU_BYPASS_DIV_MCU_DISABLE | CMU_SEL_MCU_PLL_DISABLE;
1070 break;
1071 #endif
1072 case HAL_CMU_FREQ_156M:
1073 case HAL_CMU_FREQ_208M:
1074 case HAL_CMU_FREQ_260M:
1075 enable = CMU_RSTN_DIV_MCU_ENABLE | CMU_SEL_MCU_PLL_ENABLE;
1076 disable = CMU_BYPASS_DIV_MCU_DISABLE;
1077 if (0) {
1078 #ifndef OSC_26M_X4_AUD2BB
1079 } else if (freq <= HAL_CMU_FREQ_78M) {
1080 div = 3;
1081 } else if (freq <= HAL_CMU_FREQ_104M) {
1082 div = 2;
1083 #endif
1084 } else if (freq <= HAL_CMU_FREQ_156M) {
1085 div = 1;
1086 } else { // 208M or 260M
1087 div = 0;
1088 }
1089 break;
1090 case HAL_CMU_FREQ_390M:
1091 case HAL_CMU_FREQ_780M:
1092 default:
1093 enable = CMU_BYPASS_DIV_MCU_ENABLE | CMU_SEL_MCU_PLL_ENABLE;
1094 disable = CMU_RSTN_DIV_MCU_DISABLE;
1095 break;
1096 };
1097
1098 if (div >= 0) {
1099 lock = int_lock();
1100 cmu->SYS_DIV = SET_BITFIELD(cmu->SYS_DIV, CMU_CFG_DIV_MCU, div);
1101 int_unlock(lock);
1102 }
1103
1104 if (enable & CMU_SEL_MCU_PLL_ENABLE) {
1105 cmu->SYS_CLK_ENABLE = CMU_RSTN_DIV_MCU_ENABLE;
1106 if (enable & CMU_BYPASS_DIV_MCU_ENABLE) {
1107 cmu->SYS_CLK_ENABLE = CMU_BYPASS_DIV_MCU_ENABLE;
1108 } else {
1109 cmu->SYS_CLK_DISABLE = CMU_BYPASS_DIV_MCU_DISABLE;
1110 }
1111 }
1112 cmu->SYS_CLK_ENABLE = enable;
1113 if (enable & CMU_SEL_MCU_PLL_ENABLE) {
1114 cmu->SYS_CLK_DISABLE = disable;
1115 } else {
1116 cmu->SYS_CLK_DISABLE = disable & ~(CMU_RSTN_DIV_MCU_DISABLE | CMU_BYPASS_DIV_MCU_DISABLE);
1117 cmu->SYS_CLK_DISABLE = CMU_BYPASS_DIV_MCU_DISABLE;
1118 cmu->SYS_CLK_DISABLE = CMU_RSTN_DIV_MCU_DISABLE;
1119 }
1120
1121 return 0;
1122 }
1123
hal_cmu_sys_get_freq(void)1124 enum HAL_CMU_FREQ_T BOOT_TEXT_SRAM_LOC hal_cmu_sys_get_freq(void)
1125 {
1126 uint32_t sys_clk;
1127 uint32_t div;
1128
1129 sys_clk = cmu->SYS_CLK_ENABLE;
1130
1131 if (sys_clk & CMU_SEL_MCU_PLL_ENABLE) {
1132 if (sys_clk & CMU_BYPASS_DIV_MCU_ENABLE) {
1133 // 384M
1134 return HAL_CMU_FREQ_390M;
1135 } else {
1136 div = GET_BITFIELD(cmu->SYS_DIV, CMU_CFG_DIV_MCU);
1137 if (div == 0) {
1138 // 192M
1139 return HAL_CMU_FREQ_208M;
1140 } else if (div == 1) {
1141 // 128M
1142 return HAL_CMU_FREQ_156M;
1143 } else if (div == 2) {
1144 // 96M
1145 return HAL_CMU_FREQ_104M;
1146 } else { // div == 3
1147 // 76.8M
1148 return HAL_CMU_FREQ_78M;
1149 }
1150 }
1151 } else if (sys_clk & CMU_SEL_MCU_FAST_ENABLE) {
1152 if (sys_clk & CMU_SEL_MCU_OSCX4_ENABLE) {
1153 return HAL_CMU_FREQ_104M;
1154 } else {
1155 return HAL_CMU_FREQ_52M;
1156 }
1157 } else if (sys_clk & CMU_SEL_MCU_SLOW_ENABLE) {
1158 return HAL_CMU_FREQ_26M;
1159 } else {
1160 return HAL_CMU_FREQ_32K;
1161 }
1162 }
1163
1164 #endif // !CHIP_BEST2003_DSP
1165
hal_cmu_dsp_set_freq(enum HAL_CMU_FREQ_T freq)1166 int hal_cmu_dsp_set_freq(enum HAL_CMU_FREQ_T freq)
1167 {
1168 uint32_t enable;
1169 uint32_t disable;
1170 int div;
1171 uint32_t lock;
1172
1173 if (freq >= HAL_CMU_FREQ_QTY) {
1174 return 1;
1175 }
1176
1177 #ifdef CHIP_BEST2003_DSP
1178 #ifdef LOW_SYS_FREQ
1179 cmu_sys_freq = freq;
1180 #endif
1181 #endif
1182
1183 div = -1;
1184
1185 switch (freq) {
1186 case HAL_CMU_FREQ_32K:
1187 enable = 0;
1188 disable = CMU_RSTN_DIV_A7_DISABLE | CMU_BYPASS_DIV_A7_DISABLE | CMU_SEL_A7_OSC_4_DISABLE | CMU_SEL_A7_OSC_2_DISABLE |
1189 CMU_SEL_A7_OSCX4_DISABLE | CMU_SEL_A7_SLOW_DISABLE | CMU_SEL_A7_FAST_DISABLE | CMU_SEL_A7_PLL_DISABLE;
1190 break;
1191 case HAL_CMU_FREQ_6P5M:
1192 #if defined(LOW_SYS_FREQ) && defined(LOW_SYS_FREQ_6P5M)
1193 enable = CMU_SEL_A7_OSC_4_ENABLE;
1194 disable = CMU_RSTN_DIV_A7_DISABLE | CMU_BYPASS_DIV_A7_DISABLE |
1195 CMU_SEL_A7_OSCX4_DISABLE | CMU_SEL_A7_SLOW_DISABLE | CMU_SEL_A7_FAST_DISABLE | CMU_SEL_A7_PLL_DISABLE;
1196 break;
1197 #endif
1198 case HAL_CMU_FREQ_13M:
1199 #ifdef LOW_SYS_FREQ
1200 enable = CMU_SEL_A7_OSC_2_ENABLE | CMU_SEL_A7_SLOW_ENABLE;
1201 disable = CMU_RSTN_DIV_A7_DISABLE | CMU_BYPASS_DIV_A7_DISABLE |
1202 CMU_SEL_A7_OSCX4_DISABLE | CMU_SEL_A7_FAST_DISABLE | CMU_SEL_A7_PLL_DISABLE;
1203 break;
1204 #endif
1205 case HAL_CMU_FREQ_26M:
1206 enable = CMU_SEL_A7_SLOW_ENABLE;
1207 disable = CMU_RSTN_DIV_A7_DISABLE | CMU_BYPASS_DIV_A7_DISABLE | CMU_SEL_A7_OSC_2_DISABLE |
1208 CMU_SEL_A7_OSCX4_DISABLE | CMU_SEL_A7_FAST_DISABLE | CMU_SEL_A7_PLL_DISABLE;
1209 break;
1210 case HAL_CMU_FREQ_52M:
1211 enable = CMU_SEL_A7_FAST_ENABLE;
1212 disable = CMU_RSTN_DIV_A7_DISABLE | CMU_BYPASS_DIV_A7_DISABLE |
1213 CMU_SEL_A7_OSCX4_DISABLE | CMU_SEL_A7_PLL_DISABLE;
1214 break;
1215 case HAL_CMU_FREQ_78M:
1216 case HAL_CMU_FREQ_104M:
1217 #ifdef OSC_26M_X4_AUD2BB
1218 enable = CMU_SEL_A7_OSCX4_ENABLE | CMU_SEL_A7_FAST_ENABLE;
1219 disable = CMU_RSTN_DIV_A7_DISABLE | CMU_BYPASS_DIV_A7_DISABLE | CMU_SEL_A7_PLL_DISABLE;
1220 break;
1221 #endif
1222 case HAL_CMU_FREQ_156M:
1223 case HAL_CMU_FREQ_208M:
1224 case HAL_CMU_FREQ_260M:
1225 case HAL_CMU_FREQ_390M:
1226 enable = CMU_RSTN_DIV_A7_ENABLE | CMU_SEL_A7_PLL_ENABLE;
1227 disable = CMU_BYPASS_DIV_A7_DISABLE;
1228 if (0) {
1229 } else if (freq <= HAL_CMU_FREQ_156M) {
1230 div = 3;
1231 } else if (freq <= HAL_CMU_FREQ_208M) {
1232 div = 2;
1233 } else if (freq <= HAL_CMU_FREQ_260M) {
1234 div = 1;
1235 } else { // 390M
1236 div = 0;
1237 }
1238 break;
1239 case HAL_CMU_FREQ_780M:
1240 default:
1241 enable = CMU_BYPASS_DIV_A7_ENABLE | CMU_SEL_A7_PLL_ENABLE;
1242 disable = CMU_RSTN_DIV_A7_DISABLE;
1243 break;
1244 };
1245
1246 if (div >= 0) {
1247 lock = int_lock();
1248 cmu->DSP_DIV = SET_BITFIELD(cmu->DSP_DIV, CMU_CFG_DIV_A7, div);
1249 int_unlock(lock);
1250 }
1251
1252 if (enable & CMU_SEL_A7_PLL_ENABLE) {
1253 cmu->SYS_CLK_ENABLE = CMU_RSTN_DIV_A7_ENABLE;
1254 if (enable & CMU_BYPASS_DIV_A7_ENABLE) {
1255 cmu->SYS_CLK_ENABLE = CMU_BYPASS_DIV_A7_ENABLE;
1256 } else {
1257 cmu->SYS_CLK_DISABLE = CMU_BYPASS_DIV_A7_DISABLE;
1258 }
1259 }
1260 cmu->SYS_CLK_ENABLE = enable;
1261 if (enable & CMU_SEL_A7_PLL_ENABLE) {
1262 cmu->SYS_CLK_DISABLE = disable;
1263 } else {
1264 cmu->SYS_CLK_DISABLE = disable & ~(CMU_RSTN_DIV_A7_DISABLE | CMU_BYPASS_DIV_A7_DISABLE);
1265 cmu->SYS_CLK_DISABLE = CMU_BYPASS_DIV_A7_DISABLE;
1266 cmu->SYS_CLK_DISABLE = CMU_RSTN_DIV_A7_DISABLE;
1267 }
1268
1269 return 0;
1270 }
1271
hal_cmu_dsp_get_freq(void)1272 enum HAL_CMU_FREQ_T BOOT_TEXT_SRAM_LOC hal_cmu_dsp_get_freq(void)
1273 {
1274 uint32_t sys_clk;
1275 uint32_t div;
1276
1277 sys_clk = cmu->SYS_CLK_ENABLE;
1278
1279 if (sys_clk & CMU_SEL_A7_PLL_ENABLE) {
1280 if (sys_clk & CMU_BYPASS_DIV_A7_ENABLE) {
1281 return HAL_CMU_FREQ_780M;
1282 } else {
1283 div = GET_BITFIELD(cmu->DSP_DIV, CMU_CFG_DIV_A7);
1284 if (div == 0) {
1285 return HAL_CMU_FREQ_390M;
1286 } else if (div == 1) {
1287 return HAL_CMU_FREQ_260M;
1288 } else if (div == 2) {
1289 return HAL_CMU_FREQ_208M;
1290 } else { // div == 3
1291 return HAL_CMU_FREQ_156M;
1292 }
1293 }
1294 } else if (sys_clk & CMU_SEL_A7_FAST_ENABLE) {
1295 if (sys_clk & CMU_SEL_A7_OSCX4_ENABLE) {
1296 return HAL_CMU_FREQ_104M;
1297 } else {
1298 return HAL_CMU_FREQ_52M;
1299 }
1300 } else if (sys_clk & CMU_SEL_A7_SLOW_ENABLE) {
1301 return HAL_CMU_FREQ_26M;
1302 } else {
1303 return HAL_CMU_FREQ_32K;
1304 }
1305 }
1306
hal_cmu_flash_select_pll(enum HAL_CMU_PLL_T pll)1307 int BOOT_TEXT_SRAM_LOC hal_cmu_flash_select_pll(enum HAL_CMU_PLL_T pll)
1308 {
1309 return 0;
1310 }
1311
hal_cmu_flash1_select_pll(enum HAL_CMU_PLL_T pll)1312 int BOOT_TEXT_SRAM_LOC hal_cmu_flash1_select_pll(enum HAL_CMU_PLL_T pll)
1313 {
1314 return 0;
1315 }
1316
hal_cmu_mem_select_pll(enum HAL_CMU_PLL_T pll)1317 int hal_cmu_mem_select_pll(enum HAL_CMU_PLL_T pll)
1318 {
1319 return 0;
1320 }
1321
hal_cmu_dsp_select_pll(enum HAL_CMU_PLL_T pll)1322 int hal_cmu_dsp_select_pll(enum HAL_CMU_PLL_T pll)
1323 {
1324 uint32_t lock;
1325 uint32_t set;
1326 uint32_t clr;
1327
1328 if (pll == HAL_CMU_PLL_USB) {
1329 set = AON_CMU_SEL_A7_PLLUSB | AON_CMU_SEL_A7_PLLBB;
1330 clr = 0;
1331 } else if (pll == HAL_CMU_PLL_DSP) {
1332 set = 0;
1333 clr = AON_CMU_SEL_A7_PLLUSB | AON_CMU_SEL_A7_PLLBB;
1334 } else if (pll == HAL_CMU_PLL_BB) {
1335 set = AON_CMU_SEL_A7_PLLBB;
1336 clr = AON_CMU_SEL_A7_PLLUSB;
1337 } else {
1338 // == HAL_CMU_PLL_DDR or == HAL_CMU_PLL_BB_PSRAM or >= HAL_CMU_PLL_QTY
1339 return 1;
1340 }
1341
1342 lock = int_lock();
1343 aoncmu->DSP_PLL_SELECT = (aoncmu->DSP_PLL_SELECT & ~clr) | set;
1344 int_unlock(lock);
1345
1346 return 0;
1347 }
1348
hal_cmu_sys_select_pll(enum HAL_CMU_PLL_T pll)1349 int BOOT_TEXT_FLASH_LOC hal_cmu_sys_select_pll(enum HAL_CMU_PLL_T pll)
1350 {
1351 uint32_t lock;
1352 uint32_t set;
1353 uint32_t clr;
1354
1355 if (pll == HAL_CMU_PLL_USB) {
1356 set = AON_CMU_SEL_MCU_PLLUSB | AON_CMU_SEL_MCU_PLLA7USB;
1357 clr = AON_CMU_SEL_MCU_PLLBB_PS;
1358 } else if (pll == HAL_CMU_PLL_DSP) {
1359 set = AON_CMU_SEL_MCU_PLLA7USB;
1360 clr = AON_CMU_SEL_MCU_PLLBB_PS | AON_CMU_SEL_MCU_PLLUSB;
1361 } else if (pll == HAL_CMU_PLL_BB) {
1362 set = 0;
1363 clr = AON_CMU_SEL_MCU_PLLBB_PS | AON_CMU_SEL_MCU_PLLUSB | AON_CMU_SEL_MCU_PLLA7USB;
1364 } else if (pll == HAL_CMU_PLL_BB_PSRAM) {
1365 set = AON_CMU_SEL_MCU_PLLBB_PS;
1366 clr = AON_CMU_SEL_MCU_PLLUSB | AON_CMU_SEL_MCU_PLLA7USB;
1367 } else {
1368 // == HAL_CMU_PLL_DDR or >= HAL_CMU_PLL_QTY
1369 return 1;
1370 }
1371
1372 lock = int_lock();
1373 aoncmu->FLS_PSR_CLK = (aoncmu->FLS_PSR_CLK & ~clr) | set;
1374 int_unlock(lock);
1375
1376 return 0;
1377 }
1378
hal_cmu_audio_select_pll(enum HAL_CMU_PLL_T pll)1379 int BOOT_TEXT_FLASH_LOC hal_cmu_audio_select_pll(enum HAL_CMU_PLL_T pll)
1380 {
1381 if (pll == HAL_CMU_PLL_BB) {
1382 aoncmu->PCM_I2S_CLK &= ~AON_CMU_SEL_AUD_PLLUSB;
1383 } else {
1384 aoncmu->PCM_I2S_CLK |= AON_CMU_SEL_AUD_PLLUSB;
1385 }
1386
1387 return 0;
1388 }
1389
hal_cmu_get_pll_status(enum HAL_CMU_PLL_T pll)1390 int hal_cmu_get_pll_status(enum HAL_CMU_PLL_T pll)
1391 {
1392 bool en;
1393
1394 if (pll == HAL_CMU_PLL_USB) {
1395 en = !!(aoncmu->TOP_CLK_ENABLE & AON_CMU_EN_CLK_TOP_PLLUSB_ENABLE);
1396 } else if (pll == HAL_CMU_PLL_DDR) {
1397 en = !!(aoncmu->TOP_CLK_ENABLE & AON_CMU_EN_CLK_TOP_PLLDDR_ENABLE);
1398 } else if (pll == HAL_CMU_PLL_DSP) {
1399 en = !!(aoncmu->TOP_CLK_ENABLE & AON_CMU_EN_CLK_TOP_PLLA7_ENABLE);
1400 } else if (pll == HAL_CMU_PLL_BB) {
1401 en = !!(aoncmu->TOP_CLK_ENABLE & AON_CMU_EN_CLK_TOP_PLLBB_ENABLE);
1402 } else if (pll == HAL_CMU_PLL_BB_PSRAM) {
1403 en = !!(aoncmu->TOP_CLK_ENABLE & AON_CMU_EN_CLK_TOP_PLLBB_PS_ENABLE);
1404 } else {
1405 en = false;
1406 }
1407
1408 return en;
1409 }
1410
hal_cmu_pll_enable(enum HAL_CMU_PLL_T pll,enum HAL_CMU_PLL_USER_T user)1411 int BOOT_TEXT_FLASH_LOC hal_cmu_pll_enable(enum HAL_CMU_PLL_T pll, enum HAL_CMU_PLL_USER_T user)
1412 {
1413 uint32_t pu_val;
1414 uint32_t en_val;
1415 uint32_t lock;
1416
1417 if (pll >= HAL_CMU_PLL_QTY) {
1418 return 1;
1419 }
1420 if (user >= HAL_CMU_PLL_USER_QTY && user != HAL_CMU_PLL_USER_ALL) {
1421 return 2;
1422 }
1423
1424 if (pll == HAL_CMU_PLL_USB) {
1425 pu_val = AON_CMU_PU_PLLDSI_ENABLE | AON_CMU_PU_PLLDSI_DIV_PS_ENABLE;
1426 en_val = AON_CMU_EN_CLK_TOP_PLLUSB_ENABLE;
1427 } else if (pll == HAL_CMU_PLL_DDR) {
1428 pu_val = AON_CMU_PU_PLLDDR_ENABLE;
1429 en_val = AON_CMU_EN_CLK_TOP_PLLDDR_ENABLE;
1430 } else if (pll == HAL_CMU_PLL_DSP) {
1431 pu_val = AON_CMU_PU_PLLA7_ENABLE;
1432 en_val = AON_CMU_EN_CLK_TOP_PLLA7_ENABLE;
1433 } else if (pll == HAL_CMU_PLL_BB) {
1434 #ifdef BBPLL_USE_DSI_MCUPLL
1435 pu_val = AON_CMU_PU_PLLDSI_ENABLE | AON_CMU_PU_PLLDSI_DIV_MCU_ENABLE;
1436 #else
1437 pu_val = AON_CMU_PU_PLLBB_ENABLE | AON_CMU_PU_PLLBB_DIV_MCU_ENABLE;
1438 #endif
1439 en_val = AON_CMU_EN_CLK_TOP_PLLBB_ENABLE;
1440 } else if (pll == HAL_CMU_PLL_BB_PSRAM) {
1441 #ifdef BB_PSRAMPLL_USE_DSI_PSRAMPLL
1442 pu_val = AON_CMU_PU_PLLDSI_ENABLE | AON_CMU_PU_PLLDSI_DIV_PS_ENABLE;
1443 #else
1444 pu_val = AON_CMU_PU_PLLBB_ENABLE | AON_CMU_PU_PLLBB_DIV_PS_ENABLE;
1445 #endif
1446 en_val = AON_CMU_EN_CLK_TOP_PLLBB_PS_ENABLE;
1447 } else if (pll == HAL_CMU_PLL_DSI) {
1448 pu_val = AON_CMU_PU_PLLDSI_ENABLE;
1449 en_val = 0;
1450 } else {
1451 pu_val = 0;
1452 en_val = 0;
1453 }
1454
1455 lock = int_lock();
1456
1457 if (pll_user_map[pll] == 0 || user == HAL_CMU_PLL_USER_ALL) {
1458 #ifndef ROM_BUILD
1459 pmu_pll_div_reset_set(pll);
1460 #endif
1461 aoncmu->PLL_ENABLE = pu_val;
1462 #ifndef ROM_BUILD
1463 hal_sys_timer_delay_us(20);
1464 pmu_pll_div_reset_clear(pll);
1465 // Wait at least 10us for clock ready
1466 hal_sys_timer_delay_us(10);
1467 #endif
1468 aoncmu->TOP_CLK_ENABLE = en_val;
1469 }
1470 if (user < HAL_CMU_PLL_USER_QTY) {
1471 pll_user_map[pll] |= (1 << user);
1472 } else if (user == HAL_CMU_PLL_USER_ALL) {
1473 pll_user_map[pll] |= ((1 << user) - 1);
1474 }
1475 int_unlock(lock);
1476
1477 return 0;
1478 }
1479
hal_cmu_pll_disable(enum HAL_CMU_PLL_T pll,enum HAL_CMU_PLL_USER_T user)1480 int BOOT_TEXT_FLASH_LOC hal_cmu_pll_disable(enum HAL_CMU_PLL_T pll, enum HAL_CMU_PLL_USER_T user)
1481 {
1482 uint32_t pu_val;
1483 uint32_t en_val;
1484 uint32_t lock;
1485
1486 if (pll >= HAL_CMU_PLL_QTY) {
1487 return 1;
1488 }
1489 if (user >= HAL_CMU_PLL_USER_QTY && user != HAL_CMU_PLL_USER_ALL) {
1490 return 2;
1491 }
1492
1493 if (pll == HAL_CMU_PLL_USB) {
1494 pu_val = 0;
1495 en_val = AON_CMU_EN_CLK_TOP_PLLUSB_DISABLE;
1496 } else if (pll == HAL_CMU_PLL_DDR) {
1497 pu_val = AON_CMU_PU_PLLDDR_DISABLE;
1498 en_val = AON_CMU_EN_CLK_TOP_PLLDDR_DISABLE;
1499 } else if (pll == HAL_CMU_PLL_DSP) {
1500 pu_val = AON_CMU_PU_PLLA7_DISABLE;
1501 en_val = AON_CMU_EN_CLK_TOP_PLLA7_DISABLE;
1502 } else if (pll == HAL_CMU_PLL_BB) {
1503 #ifdef BBPLL_USE_DSI_MCUPLL
1504 pu_val = AON_CMU_PU_PLLDSI_DIV_MCU_DISABLE;
1505 #else
1506 pu_val = AON_CMU_PU_PLLBB_DIV_MCU_DISABLE;
1507 #endif
1508 en_val = AON_CMU_EN_CLK_TOP_PLLBB_DISABLE;
1509 } else if (pll == HAL_CMU_PLL_BB_PSRAM) {
1510 #ifdef BB_PSRAMPLL_USE_DSI_PSRAMPLL
1511 pu_val = AON_CMU_PU_PLLDSI_DIV_PS_DISABLE;
1512 #else
1513 pu_val = AON_CMU_PU_PLLBB_DIV_PS_DISABLE;
1514 #endif
1515 en_val = AON_CMU_EN_CLK_TOP_PLLBB_PS_DISABLE;
1516 } else if (pll == HAL_CMU_PLL_DSI) {
1517 pu_val = 0;
1518 en_val = 0;
1519 } else {
1520 pu_val = 0;
1521 en_val = 0;
1522 }
1523
1524 lock = int_lock();
1525 if (user < HAL_CMU_PLL_USER_ALL) {
1526 pll_user_map[pll] &= ~(1 << user);
1527 } else if (user == HAL_CMU_PLL_USER_ALL) {
1528 pll_user_map[pll] = 0;
1529 }
1530 if (pll_user_map[pll] == 0 || user == HAL_CMU_PLL_USER_ALL) {
1531 #if defined(BBPLL_USE_DSI_MCUPLL) && defined(BB_PSRAMPLL_USE_DSI_PSRAMPLL)
1532 if (pll_user_map[HAL_CMU_PLL_BB] == 0 && pll_user_map[HAL_CMU_PLL_BB_PSRAM] == 0 &&
1533 pll_user_map[HAL_CMU_PLL_USB] == 0 && pll_user_map[HAL_CMU_PLL_DSI] == 0)
1534 pu_val |= AON_CMU_PU_PLLBB_DISABLE;
1535 #elif defined(BBPLL_USE_DSI_MCUPLL) && !defined(BB_PSRAMPLL_USE_DSI_PSRAMPLL)
1536 if (pll == HAL_CMU_PLL_BB || pll == HAL_CMU_PLL_USB || pll == HAL_CMU_PLL_DSI) {
1537 if (pll_user_map[HAL_CMU_PLL_BB] == 0 && pll_user_map[HAL_CMU_PLL_USB] == 0 &&
1538 pll_user_map[HAL_CMU_PLL_DSI] == 0)
1539 pu_val |= AON_CMU_PU_PLLDSI_DISABLE;
1540 } else if (pll == HAL_CMU_PLL_BB_PSRAM) {
1541 pu_val |= AON_CMU_PU_PLLBB_DISABLE;
1542 }
1543 #elif !defined(BBPLL_USE_DSI_MCUPLL) && defined(BB_PSRAMPLL_USE_DSI_PSRAMPLL)
1544 if (pll == HAL_CMU_PLL_BB_PSRAM || pll == HAL_CMU_PLL_USB || pll == HAL_CMU_PLL_DSI) {
1545 if (pll_user_map[HAL_CMU_PLL_BB_PSRAM] == 0 && pll_user_map[HAL_CMU_PLL_USB] == 0 &&
1546 pll_user_map[HAL_CMU_PLL_DSI] == 0)
1547 pu_val |= AON_CMU_PU_PLLDSI_DISABLE;
1548 } else if (pll == HAL_CMU_PLL_BB) {
1549 pu_val |= AON_CMU_PU_PLLBB_DISABLE;
1550 }
1551 #else
1552 if (pll == HAL_CMU_PLL_USB || pll == HAL_CMU_PLL_DSI) {
1553 if (pll_user_map[HAL_CMU_PLL_USB] == 0 && pll_user_map[HAL_CMU_PLL_DSI] == 0)
1554 pu_val |= AON_CMU_PU_PLLDSI_DISABLE;
1555 } else if (pll == HAL_CMU_PLL_BB || pll == HAL_CMU_PLL_BB_PSRAM) {
1556 if (pll_user_map[HAL_CMU_PLL_BB] == 0 && pll_user_map[HAL_CMU_PLL_BB_PSRAM] == 0)
1557 pu_val |= AON_CMU_PU_PLLBB_DISABLE;
1558 }
1559 #endif
1560 aoncmu->TOP_CLK_DISABLE = en_val;
1561 aoncmu->PLL_DISABLE = pu_val;
1562 }
1563 int_unlock(lock);
1564
1565 return 0;
1566 }
1567
hal_cmu_low_freq_mode_init(void)1568 void BOOT_TEXT_FLASH_LOC hal_cmu_low_freq_mode_init(void)
1569 {
1570 }
1571
hal_cmu_low_freq_mode_enable(enum HAL_CMU_FREQ_T old_freq,enum HAL_CMU_FREQ_T new_freq)1572 void hal_cmu_low_freq_mode_enable(enum HAL_CMU_FREQ_T old_freq, enum HAL_CMU_FREQ_T new_freq)
1573 {
1574 enum HAL_CMU_PLL_T pll;
1575 enum HAL_CMU_FREQ_T switch_freq;
1576
1577 // TODO: Select the PLL used by sys
1578 pll = HAL_CMU_PLL_BB;
1579
1580 #ifdef OSC_26M_X4_AUD2BB
1581 switch_freq = HAL_CMU_FREQ_104M;
1582 #else
1583 switch_freq = HAL_CMU_FREQ_52M;
1584 #endif
1585
1586 if (old_freq > switch_freq && new_freq <= switch_freq) {
1587 hal_cmu_pll_disable(pll, HAL_CMU_PLL_USER_SYS);
1588 }
1589 }
1590
hal_cmu_low_freq_mode_disable(enum HAL_CMU_FREQ_T old_freq,enum HAL_CMU_FREQ_T new_freq)1591 void hal_cmu_low_freq_mode_disable(enum HAL_CMU_FREQ_T old_freq, enum HAL_CMU_FREQ_T new_freq)
1592 {
1593 enum HAL_CMU_PLL_T pll;
1594 enum HAL_CMU_FREQ_T switch_freq;
1595
1596 // TODO: Select the PLL used by sys
1597 pll = HAL_CMU_PLL_BB;
1598
1599 #ifdef OSC_26M_X4_AUD2BB
1600 switch_freq = HAL_CMU_FREQ_104M;
1601 #else
1602 switch_freq = HAL_CMU_FREQ_52M;
1603 #endif
1604
1605 if (old_freq <= switch_freq && new_freq > switch_freq) {
1606 hal_cmu_pll_enable(pll, HAL_CMU_PLL_USER_SYS);
1607 }
1608 }
1609
hal_cmu_rom_enable_pll(void)1610 void hal_cmu_rom_enable_pll(void)
1611 {
1612 hal_cmu_sys_select_pll(HAL_CMU_PLL_BB);
1613 hal_cmu_pll_enable(HAL_CMU_PLL_BB, HAL_CMU_PLL_USER_SYS);
1614
1615 #if defined(PSRAM_ENABLE) && !defined(PSRAM_LOW_SPEED)
1616 hal_cmu_pll_enable(HAL_CMU_PLL_BB_PSRAM, HAL_CMU_PLL_USER_PSRAM);
1617 #endif
1618 }
1619
hal_cmu_sram_init()1620 void BOOT_TEXT_FLASH_LOC hal_cmu_sram_init()
1621 {
1622 uint32_t mcu_ram_size;
1623
1624 #if defined(ARM_CMSE)
1625 mcu_ram_size = RAM5_BASE + RAM5_SIZE - RAM0_BASE;
1626 #elif defined(ARM_CMNS)
1627 mcu_ram_size = RAM_SIZE + RAM_S_SIZE;
1628 #else
1629 mcu_ram_size = RAM_SIZE;
1630 #endif
1631 #if defined(CHIP_HAS_CP) && ((RAMCP_SIZE > 0) || (RAMCPX_SIZE > 0))
1632 mcu_ram_size += (RAMCP_SIZE + RAMCPX_SIZE);
1633 #endif
1634 #ifdef __BT_RAMRUN__
1635 mcu_ram_size += BT_RAMRUN_SIZE;
1636 #endif
1637
1638 switch (mcu_ram_size) {
1639 case RAM1_BASE - RAM0_BASE: //RAM0
1640 cmu->WAKEUP_CLK_CFG = SET_BITFIELD(cmu->WAKEUP_CLK_CFG, CMU_CFG_SRAM_IN_M33, 0x0);
1641 break;
1642 case RAM2_BASE - RAM0_BASE: //RAM0,1
1643 cmu->WAKEUP_CLK_CFG = SET_BITFIELD(cmu->WAKEUP_CLK_CFG, CMU_CFG_SRAM_IN_M33, 0x1);
1644 break;
1645 case RAM3_BASE - RAM0_BASE: //RAM0,1,2
1646 cmu->WAKEUP_CLK_CFG = SET_BITFIELD(cmu->WAKEUP_CLK_CFG, CMU_CFG_SRAM_IN_M33, 0x3);
1647 break;
1648 case RAM4_BASE - RAM0_BASE: //RAM0,1,2,3
1649 cmu->WAKEUP_CLK_CFG = SET_BITFIELD(cmu->WAKEUP_CLK_CFG, CMU_CFG_SRAM_IN_M33, 0x7);
1650 break;
1651 case RAM5_BASE - RAM0_BASE: //RAM0,1,2,3,4
1652 cmu->WAKEUP_CLK_CFG = SET_BITFIELD(cmu->WAKEUP_CLK_CFG, CMU_CFG_SRAM_IN_M33, 0xF);
1653 break;
1654 case (RAM5_BASE + RAM5_SIZE - RAM0_BASE): //RAM0,1,2,3,4,5
1655 default:
1656 cmu->WAKEUP_CLK_CFG = SET_BITFIELD(cmu->WAKEUP_CLK_CFG, CMU_CFG_SRAM_IN_M33, 0x1F);
1657 break;
1658 }
1659 }
1660
hal_cmu_programmer_enable_pll(void)1661 void hal_cmu_programmer_enable_pll(void)
1662 {
1663 hal_cmu_sram_init();
1664 hal_cmu_dma_req_init();
1665
1666 hal_cmu_flash_select_pll(HAL_CMU_PLL_BB);
1667 hal_cmu_sys_select_pll(HAL_CMU_PLL_BB);
1668 hal_cmu_pll_enable(HAL_CMU_PLL_BB, HAL_CMU_PLL_USER_SYS);
1669
1670 #if defined(PSRAM_ENABLE) && !defined(PSRAM_LOW_SPEED)
1671 hal_cmu_pll_enable(HAL_CMU_PLL_BB_PSRAM, HAL_CMU_PLL_USER_PSRAM);
1672 #endif
1673 }
1674
hal_cmu_init_pll_selection(void)1675 void BOOT_TEXT_FLASH_LOC hal_cmu_init_pll_selection(void)
1676 {
1677 enum HAL_CMU_PLL_T sys;
1678
1679 #if !defined(ARM_CMNS)
1680 // Disable the PLL which might be enabled in ROM
1681 hal_cmu_pll_disable(HAL_CMU_PLL_BB, HAL_CMU_PLL_USER_ALL);
1682 #endif
1683
1684 #ifdef BBPLL_USE_DSI_MCUPLL
1685 aoncmu->FLS_PSR_CLK |= AON_CMU_SEL_MCU_PLLDSI;
1686 #endif
1687
1688 #ifdef BB_PSRAMPLL_USE_DSI_PSRAMPLL
1689 aoncmu->FLS_PSR_CLK |= AON_CMU_SEL_PSR_PLLDSI;
1690 #endif
1691
1692 #ifdef SYS_USE_USBPLL
1693 sys = HAL_CMU_PLL_USB;
1694 #elif defined(SYS_USE_BB_PSRAMPLL)
1695 sys = HAL_CMU_PLL_BB_PSRAM;
1696 #elif defined(SYS_USE_DSPPLL)
1697 sys = HAL_CMU_PLL_DSP;
1698 #else
1699 sys = HAL_CMU_PLL_BB;
1700 #endif
1701 hal_cmu_sys_select_pll(sys);
1702
1703 #ifdef AUDIO_USE_BBPLL
1704 hal_cmu_audio_select_pll(HAL_CMU_PLL_BB);
1705 #else
1706 hal_cmu_audio_select_pll(HAL_CMU_PLL_USB);
1707 #endif
1708
1709 #ifndef ULTRA_LOW_POWER
1710 hal_cmu_pll_enable(sys, HAL_CMU_PLL_USER_SYS);
1711 #endif
1712 #if !(defined(FLASH_LOW_SPEED) || defined(OSC_26M_X4_AUD2BB))
1713 hal_cmu_pll_enable(HAL_CMU_PLL_BB, HAL_CMU_PLL_USER_FLASH);
1714 #endif
1715 #if defined(PSRAM_ENABLE) && !defined(PSRAM_LOW_SPEED)
1716 hal_cmu_pll_enable(HAL_CMU_PLL_BB_PSRAM, HAL_CMU_PLL_USER_PSRAM);
1717 #endif
1718
1719 hal_cmu_dsp_timer0_select_slow();
1720 #ifdef TIMER1_BASE
1721 hal_cmu_dsp_timer1_select_fast();
1722 #endif
1723 }
1724
1725 #if defined(__AUDIO_RESAMPLE__) && defined(ANA_26M_X4_ENABLE)
hal_cmu_audio_26m_x4_enable(enum CMU_AUD_26M_X4_USER_T user)1726 void hal_cmu_audio_26m_x4_enable(enum CMU_AUD_26M_X4_USER_T user)
1727 {
1728 uint32_t lock;
1729
1730 if (user >= CMU_AUD_26M_X4_USER_QTY) {
1731 return;
1732 }
1733
1734 lock = int_lock();
1735
1736 if (aud_26m_x4_map == 0) {
1737 aoncmu->PCM_I2S_CLK |= AON_CMU_SEL_AUD_X4;
1738 }
1739 aud_26m_x4_map |= (1 << user);
1740
1741 int_unlock(lock);
1742 }
1743
hal_cmu_audio_26m_x4_disable(enum CMU_AUD_26M_X4_USER_T user)1744 void hal_cmu_audio_26m_x4_disable(enum CMU_AUD_26M_X4_USER_T user)
1745 {
1746 uint32_t lock;
1747
1748 if (user >= CMU_AUD_26M_X4_USER_QTY) {
1749 return;
1750 }
1751
1752 lock = int_lock();
1753
1754 if (aud_26m_x4_map & (1 << user)) {
1755 aud_26m_x4_map &= ~(1 << user);
1756 if (aud_26m_x4_map == 0) {
1757 aoncmu->PCM_I2S_CLK &= ~AON_CMU_SEL_AUD_X4;
1758 }
1759 }
1760
1761 int_unlock(lock);
1762 }
1763 #endif
1764
hal_cmu_codec_iir_enable(uint32_t speed)1765 void hal_cmu_codec_iir_enable(uint32_t speed)
1766 {
1767 uint32_t lock;
1768 uint32_t mask;
1769 uint32_t val;
1770 uint32_t div;
1771 uint32_t cfg_speed = 0;
1772
1773 mask = AON_CMU_SEL_CODECIIR_OSC | AON_CMU_SEL_CODECIIR_OSCX2 | AON_CMU_BYPASS_DIV_CODECIIR;
1774 val = 0;
1775
1776 if (speed <= 26000000) {
1777 val |= AON_CMU_SEL_CODECIIR_OSC | AON_CMU_SEL_CODECIIR_OSCX2;
1778 cfg_speed = 26000000;
1779 } else if (speed <= 52000000) {
1780 val |= AON_CMU_SEL_CODECIIR_OSCX2;
1781 cfg_speed = 52000000;
1782 } else {
1783 #if defined(__AUDIO_RESAMPLE__) && defined(ANA_26M_X4_ENABLE)
1784 if (hal_cmu_get_audio_resample_status()) {
1785 hal_cmu_audio_26m_x4_enable(CMU_AUD_26M_X4_USER_IIR);
1786 val |= AON_CMU_BYPASS_DIV_CODECIIR;
1787 cfg_speed = 104000000;
1788 }
1789 else
1790 #endif
1791 {
1792 // Assume audio stream is one of 48K series
1793 div = HAL_CMU_AUD_PLL_CLOCK / speed;
1794 if (div >= 2) {
1795 hal_cmu_codec_iir_set_div(div);
1796 cfg_speed = HAL_CMU_AUD_PLL_CLOCK / div;
1797 } else {
1798 val |= AON_CMU_BYPASS_DIV_CODECIIR;
1799 cfg_speed = HAL_CMU_AUD_PLL_CLOCK;
1800 }
1801 analog_aud_freq_pll_config(CODEC_FREQ_48K_SERIES, CODEC_PLL_DIV);
1802 analog_aud_pll_open(ANA_AUD_PLL_USER_IIR);
1803 }
1804
1805 //pmu_iir_freq_config(cfg_speed);
1806 }
1807
1808 ASSERT(speed <= cfg_speed, "%s: speed %u should <= cfg_speed %u", __func__, speed, cfg_speed);
1809
1810 lock = int_lock();
1811 aoncmu->CODEC_IIR = (aoncmu->CODEC_IIR & ~mask) | val;
1812 int_unlock(lock);
1813
1814 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_CODECIIR_ENABLE;
1815
1816 aocmu_reg_update_wait();
1817 }
1818
hal_cmu_codec_iir_disable(void)1819 void hal_cmu_codec_iir_disable(void)
1820 {
1821 uint32_t lock;
1822 uint32_t val;
1823 bool high_speed;
1824
1825 aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_CODECIIR_DISABLE;
1826
1827 #if defined(__AUDIO_RESAMPLE__) && defined(ANA_26M_X4_ENABLE)
1828 hal_cmu_audio_26m_x4_disable(CMU_AUD_26M_X4_USER_IIR);
1829 #endif
1830
1831 high_speed = !(aoncmu->CODEC_IIR & AON_CMU_SEL_CODECIIR_OSC);
1832
1833 val = AON_CMU_SEL_CODECIIR_OSC | AON_CMU_SEL_CODECIIR_OSCX2;
1834
1835 lock = int_lock();
1836 aoncmu->CODEC_IIR |= val;
1837 int_unlock(lock);
1838
1839 if (high_speed) {
1840 //pmu_iir_freq_config(0);
1841 }
1842 analog_aud_pll_close(ANA_AUD_PLL_USER_IIR);
1843 }
1844
hal_cmu_codec_iir_set_div(uint32_t div)1845 int hal_cmu_codec_iir_set_div(uint32_t div)
1846 {
1847 uint32_t lock;
1848
1849 if (div < 2) {
1850 return 1;
1851 }
1852
1853 div -= 2;
1854 lock = int_lock();
1855 aoncmu->CODEC_IIR = SET_BITFIELD(aoncmu->CODEC_IIR, AON_CMU_CFG_DIV_CODECIIR, div);
1856 int_unlock(lock);
1857
1858 return 0;
1859 }
1860
hal_cmu_codec_rs_enable(uint32_t speed)1861 void hal_cmu_codec_rs_enable(uint32_t speed)
1862 {
1863 uint32_t lock;
1864 uint32_t mask;
1865 uint32_t val;
1866 uint32_t div;
1867 uint32_t cfg_speed = 0;
1868
1869 mask = AON_CMU_SEL_CODECRS0_OSC | AON_CMU_SEL_CODECRS0_OSCX2 | AON_CMU_BYPASS_DIV_CODECRS0;
1870 mask |= AON_CMU_SEL_CODECRS1_OSC | AON_CMU_SEL_CODECRS1_OSCX2 | AON_CMU_BYPASS_DIV_CODECRS1;
1871 val = 0;
1872
1873 if (speed <= 26000000) {
1874 val |= AON_CMU_SEL_CODECRS0_OSC | AON_CMU_SEL_CODECRS0_OSCX2;
1875 val |= AON_CMU_SEL_CODECRS1_OSC | AON_CMU_SEL_CODECRS1_OSCX2;
1876 cfg_speed = 26000000;
1877 } else if (speed <= 52000000) {
1878 val |= AON_CMU_SEL_CODECRS0_OSCX2;
1879 val |= AON_CMU_SEL_CODECRS1_OSCX2;
1880 cfg_speed = 52000000;
1881 } else {
1882 #if defined(__AUDIO_RESAMPLE__) && defined(ANA_26M_X4_ENABLE)
1883 if (hal_cmu_get_audio_resample_status()) {
1884 hal_cmu_audio_26m_x4_enable(CMU_AUD_26M_X4_USER_RS);
1885 val |= AON_CMU_BYPASS_DIV_CODECRS0;
1886 val |= AON_CMU_BYPASS_DIV_CODECRS1;
1887 cfg_speed = 104000000;
1888 }
1889 else
1890 #endif
1891 {
1892 // Assume audio stream is one of 48K series
1893 div = HAL_CMU_AUD_PLL_CLOCK / speed;
1894 if (div >= 2) {
1895 hal_cmu_codec_rs_set_div(div);
1896 cfg_speed = HAL_CMU_AUD_PLL_CLOCK / div;
1897 } else {
1898 val |= AON_CMU_BYPASS_DIV_CODECRS0;
1899 val |= AON_CMU_BYPASS_DIV_CODECRS1;
1900 cfg_speed = HAL_CMU_AUD_PLL_CLOCK;
1901 }
1902 analog_aud_freq_pll_config(CODEC_FREQ_48K_SERIES, CODEC_PLL_DIV);
1903 analog_aud_pll_open(ANA_AUD_PLL_USER_RS);
1904 }
1905 }
1906
1907 ASSERT(speed <= cfg_speed, "%s: speed %u should <= cfg_speed %u", __func__, speed, cfg_speed);
1908
1909 lock = int_lock();
1910 aoncmu->CODEC_IIR = (aoncmu->CODEC_IIR & ~mask) | val;
1911 int_unlock(lock);
1912
1913 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_CODECRS0_ENABLE | AON_CMU_EN_CLK_CODECRS1_ENABLE;
1914
1915 aocmu_reg_update_wait();
1916 }
1917
hal_cmu_codec_rs_disable(void)1918 void hal_cmu_codec_rs_disable(void)
1919 {
1920 uint32_t lock;
1921 //bool high_speed;
1922
1923 aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_CODECRS0_DISABLE | AON_CMU_EN_CLK_CODECRS1_DISABLE;
1924
1925 #if defined(__AUDIO_RESAMPLE__) && defined(ANA_26M_X4_ENABLE)
1926 hal_cmu_audio_26m_x4_disable(CMU_AUD_26M_X4_USER_RS);
1927 #endif
1928
1929 lock = int_lock();
1930 aoncmu->CODEC_IIR |= AON_CMU_SEL_CODECRS0_OSC | AON_CMU_SEL_CODECRS0_OSCX2 | AON_CMU_SEL_CODECRS1_OSC | AON_CMU_SEL_CODECRS1_OSCX2;
1931 int_unlock(lock);
1932
1933 analog_aud_pll_close(ANA_AUD_PLL_USER_RS);
1934 }
1935
hal_cmu_codec_rs_set_div(uint32_t div)1936 int hal_cmu_codec_rs_set_div(uint32_t div)
1937 {
1938 uint32_t lock;
1939
1940 if (div < 2) {
1941 return 1;
1942 }
1943
1944 div -= 2;
1945 lock = int_lock();
1946 aoncmu->CODEC_IIR = (aoncmu->CODEC_IIR & ~(AON_CMU_CFG_DIV_CODECRS0_MASK | AON_CMU_CFG_DIV_CODECRS1_MASK)) |
1947 AON_CMU_CFG_DIV_CODECRS0(div) | AON_CMU_CFG_DIV_CODECRS1(div);
1948 int_unlock(lock);
1949
1950 return 0;
1951 }
1952
hal_cmu_codec_clock_enable(void)1953 void hal_cmu_codec_clock_enable(void)
1954 {
1955 uint32_t lock;
1956
1957 lock = int_lock();
1958 aoncmu->CODEC_DIV = (aoncmu->CODEC_DIV & ~(AON_CMU_SEL_CODEC_OSC | AON_CMU_SEL_CODECHCLK_OSCX2 | AON_CMU_SEL_CODEC_ANA_2 | AON_CMU_SEL_CODECHCLK_PLL)) |
1959 AON_CMU_SEL_CODEC_OSC_2;
1960 int_unlock(lock);
1961
1962 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_CODECHCLK_ENABLE | AON_CMU_EN_CLK_CODEC_ENABLE;
1963 hal_cmu_clock_enable(HAL_CMU_MOD_H_CODEC);
1964 }
1965
hal_cmu_codec_clock_disable(void)1966 void hal_cmu_codec_clock_disable(void)
1967 {
1968 hal_cmu_clock_disable(HAL_CMU_MOD_H_CODEC);
1969 aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_CODECHCLK_DISABLE | AON_CMU_EN_CLK_CODEC_DISABLE;
1970 }
1971
hal_cmu_codec_vad_clock_enable(int type)1972 void hal_cmu_codec_vad_clock_enable(int type)
1973 {
1974 uint32_t lock;
1975
1976 lock = int_lock();
1977 aoncmu->CODEC_DIV |= (AON_CMU_EN_VAD_IIR | AON_CMU_EN_VAD_RS);
1978 int_unlock(lock);
1979
1980 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_OSC_ENABLE | AON_CMU_EN_CLK_VAD32K_ENABLE;
1981 if (type == AUD_VAD_TYPE_MIX) {
1982 aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_CODEC_DISABLE;
1983 }
1984 }
1985
hal_cmu_codec_vad_clock_disable(int type)1986 void hal_cmu_codec_vad_clock_disable(int type)
1987 {
1988 uint32_t lock;
1989
1990 aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_TOP_OSC_DISABLE | AON_CMU_EN_CLK_VAD32K_DISABLE;
1991 if (type == AUD_VAD_TYPE_MIX) {
1992 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_CODEC_ENABLE;
1993 }
1994
1995 lock = int_lock();
1996 aoncmu->CODEC_DIV &= ~(AON_CMU_EN_VAD_IIR | AON_CMU_EN_VAD_RS);
1997 int_unlock(lock);
1998 }
1999
hal_cmu_codec_reset_set(void)2000 void hal_cmu_codec_reset_set(void)
2001 {
2002 aoncmu->SOFT_RSTN_SET = AON_CMU_SOFT_RSTN_CODEC_SET;
2003 }
2004
hal_cmu_codec_reset_clear(void)2005 void hal_cmu_codec_reset_clear(void)
2006 {
2007 hal_cmu_reset_clear(HAL_CMU_MOD_H_CODEC);
2008 aoncmu->SOFT_RSTN_CLR = AON_CMU_SOFT_RSTN_CODEC_CLR;
2009 aocmu_reg_update_wait();
2010 }
2011
hal_cmu_codec_set_fault_mask(uint32_t msk)2012 void hal_cmu_codec_set_fault_mask(uint32_t msk)
2013 {
2014 uint32_t lock;
2015
2016 lock = int_lock();
2017 // If bit set 1, DAC will be muted when some faults occur
2018 cmu->PERIPH_CLK = SET_BITFIELD(cmu->PERIPH_CLK, CMU_MASK_OBS, msk);
2019 int_unlock(lock);
2020 }
2021
hal_cmu_i2s_clock_out_enable(enum HAL_I2S_ID_T id)2022 void hal_cmu_i2s_clock_out_enable(enum HAL_I2S_ID_T id)
2023 {
2024 uint32_t lock;
2025 uint32_t val;
2026
2027 if (id == HAL_I2S_ID_0) {
2028 val = CMU_EN_CLK_I2S0_OUT;
2029 } else {
2030 val = CMU_EN_CLK_I2S1_OUT;
2031 }
2032
2033 lock = int_lock();
2034 cmu->I2C_CLK |= val;
2035 int_unlock(lock);
2036 }
2037
hal_cmu_i2s_clock_out_disable(enum HAL_I2S_ID_T id)2038 void hal_cmu_i2s_clock_out_disable(enum HAL_I2S_ID_T id)
2039 {
2040 uint32_t lock;
2041 uint32_t val;
2042
2043 if (id == HAL_I2S_ID_0) {
2044 val = CMU_EN_CLK_I2S0_OUT;
2045 } else {
2046 val = CMU_EN_CLK_I2S1_OUT;
2047 }
2048
2049 lock = int_lock();
2050 cmu->I2C_CLK &= ~val;
2051 int_unlock(lock);
2052 }
2053
hal_cmu_i2s_set_slave_mode(enum HAL_I2S_ID_T id)2054 void hal_cmu_i2s_set_slave_mode(enum HAL_I2S_ID_T id)
2055 {
2056 uint32_t lock;
2057 uint32_t val;
2058
2059 if (id == HAL_I2S_ID_0) {
2060 val = CMU_SEL_I2S0_CLKIN;
2061 } else {
2062 val = CMU_SEL_I2S1_CLKIN;
2063 }
2064
2065 lock = int_lock();
2066 cmu->I2C_CLK |= val;
2067 int_unlock(lock);
2068 }
2069
hal_cmu_i2s_set_master_mode(enum HAL_I2S_ID_T id)2070 void hal_cmu_i2s_set_master_mode(enum HAL_I2S_ID_T id)
2071 {
2072 uint32_t lock;
2073 uint32_t val;
2074
2075 if (id == HAL_I2S_ID_0) {
2076 val = CMU_SEL_I2S0_CLKIN;
2077 } else {
2078 val = CMU_SEL_I2S1_CLKIN;
2079 }
2080
2081 lock = int_lock();
2082 cmu->I2C_CLK &= ~val;
2083 int_unlock(lock);
2084 }
2085
hal_cmu_i2s_clock_enable(enum HAL_I2S_ID_T id)2086 void hal_cmu_i2s_clock_enable(enum HAL_I2S_ID_T id)
2087 {
2088 uint32_t lock;
2089 uint32_t val;
2090 volatile uint32_t *reg;
2091
2092 if (id == HAL_I2S_ID_0) {
2093 val = AON_CMU_EN_CLK_PLL_I2S0;
2094 reg = &aoncmu->PCM_I2S_CLK;
2095 } else {
2096 val = AON_CMU_EN_CLK_PLL_I2S1;
2097 reg = &aoncmu->SPDIF_CLK;
2098 }
2099
2100 lock = int_lock();
2101 *reg |= val;
2102 int_unlock(lock);
2103 }
2104
hal_cmu_i2s_clock_disable(enum HAL_I2S_ID_T id)2105 void hal_cmu_i2s_clock_disable(enum HAL_I2S_ID_T id)
2106 {
2107 uint32_t lock;
2108 uint32_t val;
2109 volatile uint32_t *reg;
2110
2111 if (id == HAL_I2S_ID_0) {
2112 val = AON_CMU_EN_CLK_PLL_I2S0;
2113 reg = &aoncmu->PCM_I2S_CLK;
2114 } else {
2115 val = AON_CMU_EN_CLK_PLL_I2S1;
2116 reg = &aoncmu->SPDIF_CLK;
2117 }
2118
2119 lock = int_lock();
2120 *reg &= ~val;
2121 int_unlock(lock);
2122 }
2123
hal_cmu_i2s_set_div(enum HAL_I2S_ID_T id,uint32_t div)2124 int hal_cmu_i2s_set_div(enum HAL_I2S_ID_T id, uint32_t div)
2125 {
2126 uint32_t lock;
2127
2128 if (div < 2) {
2129 return 1;
2130 }
2131
2132 div -= 2;
2133 if ((div & (AON_CMU_CFG_DIV_I2S0_MASK >> AON_CMU_CFG_DIV_I2S0_SHIFT)) != div) {
2134 return 1;
2135 }
2136
2137 lock = int_lock();
2138 if (id == HAL_I2S_ID_0) {
2139 aoncmu->PCM_I2S_CLK = SET_BITFIELD(aoncmu->PCM_I2S_CLK, AON_CMU_CFG_DIV_I2S0, div);
2140 } else {
2141 aoncmu->SPDIF_CLK = SET_BITFIELD(aoncmu->SPDIF_CLK, AON_CMU_CFG_DIV_I2S1, div);
2142 }
2143 int_unlock(lock);
2144
2145 return 0;
2146 }
2147
hal_cmu_pcm_clock_out_enable(void)2148 void hal_cmu_pcm_clock_out_enable(void)
2149 {
2150 uint32_t lock;
2151
2152 lock = int_lock();
2153 cmu->I2C_CLK |= CMU_EN_CLK_PCM_OUT;
2154 int_unlock(lock);
2155 }
2156
hal_cmu_pcm_clock_out_disable(void)2157 void hal_cmu_pcm_clock_out_disable(void)
2158 {
2159 uint32_t lock;
2160
2161 lock = int_lock();
2162 cmu->I2C_CLK &= ~CMU_EN_CLK_PCM_OUT;
2163 int_unlock(lock);
2164 }
2165
hal_cmu_pcm_set_slave_mode(int clk_pol)2166 void hal_cmu_pcm_set_slave_mode(int clk_pol)
2167 {
2168 uint32_t lock;
2169 uint32_t mask;
2170 uint32_t cfg;
2171
2172 mask = CMU_SEL_PCM_CLKIN | CMU_POL_CLK_PCM_IN;
2173
2174 if (clk_pol) {
2175 cfg = CMU_SEL_PCM_CLKIN | CMU_POL_CLK_PCM_IN;
2176 } else {
2177 cfg = CMU_SEL_PCM_CLKIN;
2178 }
2179
2180 lock = int_lock();
2181 cmu->I2C_CLK = (cmu->I2C_CLK & ~mask) | cfg;
2182 int_unlock(lock);
2183 }
2184
hal_cmu_pcm_set_master_mode(void)2185 void hal_cmu_pcm_set_master_mode(void)
2186 {
2187 uint32_t lock;
2188
2189 lock = int_lock();
2190 cmu->I2C_CLK &= ~CMU_SEL_PCM_CLKIN;
2191 int_unlock(lock);
2192 }
2193
hal_cmu_pcm_clock_enable(void)2194 void hal_cmu_pcm_clock_enable(void)
2195 {
2196 uint32_t lock;
2197
2198 lock = int_lock();
2199 aoncmu->PCM_I2S_CLK |= AON_CMU_EN_CLK_PLL_PCM;
2200 int_unlock(lock);
2201 }
2202
hal_cmu_pcm_clock_disable(void)2203 void hal_cmu_pcm_clock_disable(void)
2204 {
2205 uint32_t lock;
2206
2207 lock = int_lock();
2208 aoncmu->PCM_I2S_CLK &= ~AON_CMU_EN_CLK_PLL_PCM;
2209 int_unlock(lock);
2210 }
2211
hal_cmu_pcm_set_div(uint32_t div)2212 int hal_cmu_pcm_set_div(uint32_t div)
2213 {
2214 uint32_t lock;
2215
2216 if (div < 2) {
2217 return 1;
2218 }
2219
2220 div -= 2;
2221 if ((div & (AON_CMU_CFG_DIV_PCM_MASK >> AON_CMU_CFG_DIV_PCM_SHIFT)) != div) {
2222 return 1;
2223 }
2224
2225 lock = int_lock();
2226 aoncmu->PCM_I2S_CLK = SET_BITFIELD(aoncmu->PCM_I2S_CLK, AON_CMU_CFG_DIV_PCM, div);
2227 int_unlock(lock);
2228 return 0;
2229 }
2230
hal_cmu_spdif_clock_enable(enum HAL_SPDIF_ID_T id)2231 int hal_cmu_spdif_clock_enable(enum HAL_SPDIF_ID_T id)
2232 {
2233 uint32_t lock;
2234 uint32_t mask;
2235
2236 if (id >= HAL_SPDIF_ID_QTY) {
2237 return 1;
2238 }
2239
2240 mask = AON_CMU_EN_CLK_PLL_SPDIF0;
2241
2242 lock = int_lock();
2243 aoncmu->SPDIF_CLK |= mask;
2244 int_unlock(lock);
2245 return 0;
2246 }
2247
hal_cmu_spdif_clock_disable(enum HAL_SPDIF_ID_T id)2248 int hal_cmu_spdif_clock_disable(enum HAL_SPDIF_ID_T id)
2249 {
2250 uint32_t lock;
2251 uint32_t mask;
2252
2253 if (id >= HAL_SPDIF_ID_QTY) {
2254 return 1;
2255 }
2256
2257 mask = AON_CMU_EN_CLK_PLL_SPDIF0;
2258
2259 lock = int_lock();
2260 aoncmu->SPDIF_CLK &= ~mask;
2261 int_unlock(lock);
2262
2263 return 0;
2264 }
2265
hal_cmu_spdif_set_div(enum HAL_SPDIF_ID_T id,uint32_t div)2266 int hal_cmu_spdif_set_div(enum HAL_SPDIF_ID_T id, uint32_t div)
2267 {
2268 uint32_t lock;
2269
2270 if (id >= HAL_SPDIF_ID_QTY) {
2271 return 1;
2272 }
2273
2274 if (div < 2) {
2275 return 2;
2276 }
2277
2278 div -= 2;
2279 if ((div & (AON_CMU_CFG_DIV_SPDIF0_MASK >> AON_CMU_CFG_DIV_SPDIF0_SHIFT)) != div) {
2280 return 2;
2281 }
2282
2283 lock = int_lock();
2284 aoncmu->SPDIF_CLK = SET_BITFIELD(aoncmu->SPDIF_CLK, AON_CMU_CFG_DIV_SPDIF0, div);
2285 int_unlock(lock);
2286 return 0;
2287 }
2288
2289 #ifdef CHIP_HAS_USB
hal_cmu_usb_set_device_mode(void)2290 void hal_cmu_usb_set_device_mode(void)
2291 {
2292 uint32_t lock;
2293
2294 lock = int_lock();
2295 cmu->SYS_DIV |= CMU_USB_ID;
2296 int_unlock(lock);
2297 }
2298
hal_cmu_usb_set_host_mode(void)2299 void hal_cmu_usb_set_host_mode(void)
2300 {
2301 uint32_t lock;
2302
2303 lock = int_lock();
2304 cmu->SYS_DIV &= ~CMU_USB_ID;
2305 int_unlock(lock);
2306 }
2307
2308 #ifdef ROM_BUILD
hal_cmu_usb_rom_select_clock_source(int pll_en,unsigned int crystal)2309 enum HAL_CMU_USB_CLOCK_SEL_T hal_cmu_usb_rom_select_clock_source(int pll_en, unsigned int crystal)
2310 {
2311 enum HAL_CMU_USB_CLOCK_SEL_T sel;
2312
2313 if (crystal == 24000000) {
2314 sel = HAL_CMU_USB_CLOCK_SEL_24M_X2;
2315 } else {
2316 sel = HAL_CMU_USB_CLOCK_SEL_PLL;
2317 }
2318
2319 hal_cmu_usb_rom_set_clock_source(sel);
2320
2321 return sel;
2322 }
hal_cmu_usb_rom_set_clock_source(enum HAL_CMU_USB_CLOCK_SEL_T sel)2323 void hal_cmu_usb_rom_set_clock_source(enum HAL_CMU_USB_CLOCK_SEL_T sel)
2324 {
2325 }
2326 #endif
2327
hal_cmu_usb_get_clock_source(void)2328 static uint32_t hal_cmu_usb_get_clock_source(void)
2329 {
2330 uint32_t src;
2331
2332 #ifdef USB_HIGH_SPEED
2333 src = CMU_USB_CLK_SRC_PLL_60M;
2334 #else
2335 #ifndef USB_USE_USBPLL
2336 if (hal_cmu_get_crystal_freq() == 24000000)
2337 src = CMU_USB_CLK_SRC_OSC_24M_X2;
2338 else
2339 #endif
2340 src = CMU_USB_CLK_SRC_PLL_48M;
2341 #endif
2342
2343 return src;
2344 }
2345
hal_cmu_usb_clock_enable(void)2346 void hal_cmu_usb_clock_enable(void)
2347 {
2348 enum HAL_CMU_PLL_T pll;
2349 uint32_t lock;
2350 uint32_t src;
2351 POSSIBLY_UNUSED uint32_t div;
2352
2353 #if !defined(USB_HIGH_SPEED) && defined(USB_USE_USBPLL)
2354 pll = HAL_CMU_PLL_USB;
2355 #else
2356 pll = HAL_CMU_PLL_BB;
2357 #endif
2358 src = hal_cmu_usb_get_clock_source();
2359 if (src != CMU_USB_CLK_SRC_OSC_24M_X2)
2360 hal_cmu_pll_enable(pll, HAL_CMU_PLL_USER_USB);
2361
2362 lock = int_lock();
2363 #ifdef USB_HIGH_SPEED
2364 cmu->SYS_DIV = SET_BITFIELD(cmu->SYS_DIV, CMU_SEL_USB_SRC, 1);
2365 #else
2366 cmu->SYS_DIV = SET_BITFIELD(cmu->SYS_DIV, CMU_SEL_USB_SRC, 0);
2367 if (src == CMU_USB_CLK_SRC_OSC_24M_X2) {
2368 aoncmu->CLK_SELECT |= AON_CMU_SEL_USB_OSCX2;
2369 } else {
2370 #ifdef USB_USE_USBPLL
2371 aoncmu->CLK_SELECT |= AON_CMU_SEL_USB_PLLUSB;
2372 // DSI PSRAMPLL to dig: ?
2373 div = 8;///TODO:
2374 #else // USB usb BBPLL
2375 aoncmu->CLK_SELECT &= ~AON_CMU_SEL_USB_PLLUSB;
2376 // BBPLL to dig: 384M
2377 div = 8;
2378 #endif
2379 aoncmu->CLK_SELECT = SET_BITFIELD(aoncmu->CLK_SELECT, AON_CMU_CFG_DIV_USB, div-2);
2380 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_USB_PLL_ENABLE;
2381 }
2382 #endif /*USB_HIGH_SPEED*/
2383 int_unlock(lock);
2384 hal_cmu_clock_enable(HAL_CMU_MOD_H_USBC);
2385 #ifdef USB_HIGH_SPEED
2386 hal_cmu_clock_enable(HAL_CMU_MOD_H_USBH);
2387 #endif
2388 hal_cmu_clock_enable(HAL_CMU_MOD_O_USB32K);
2389 hal_cmu_clock_enable(HAL_CMU_MOD_O_USB);
2390 hal_cmu_reset_set(HAL_CMU_MOD_O_USB);
2391 hal_cmu_reset_set(HAL_CMU_MOD_O_USB32K);
2392 #ifdef USB_HIGH_SPEED
2393 hal_cmu_reset_set(HAL_CMU_MOD_H_USBH);
2394 #endif
2395 hal_cmu_reset_set(HAL_CMU_MOD_H_USBC);
2396 hal_sys_timer_delay(US_TO_TICKS(60));
2397 hal_cmu_reset_clear(HAL_CMU_MOD_H_USBC);
2398 #ifdef USB_HIGH_SPEED
2399 hal_cmu_reset_clear(HAL_CMU_MOD_H_USBH);
2400 #endif
2401 hal_cmu_reset_clear(HAL_CMU_MOD_O_USB32K);
2402 hal_cmu_reset_clear(HAL_CMU_MOD_O_USB);
2403 }
2404
hal_cmu_usb_clock_disable(void)2405 void hal_cmu_usb_clock_disable(void)
2406 {
2407 enum HAL_CMU_PLL_T pll;
2408
2409 #if !defined(USB_HIGH_SPEED) && defined(USB_USE_USBPLL)
2410 pll = HAL_CMU_PLL_USB;
2411 #else
2412 pll = HAL_CMU_PLL_BB;
2413 #endif
2414
2415 hal_cmu_reset_set(HAL_CMU_MOD_O_USB);
2416 hal_cmu_reset_set(HAL_CMU_MOD_O_USB32K);
2417 #ifdef USB_HIGH_SPEED
2418 hal_cmu_reset_set(HAL_CMU_MOD_H_USBH);
2419 #endif
2420 hal_cmu_reset_set(HAL_CMU_MOD_H_USBC);
2421 hal_cmu_clock_disable(HAL_CMU_MOD_O_USB);
2422 hal_cmu_clock_disable(HAL_CMU_MOD_O_USB32K);
2423 #ifdef USB_HIGH_SPEED
2424 hal_cmu_clock_disable(HAL_CMU_MOD_H_USBH);
2425 #endif
2426 hal_cmu_clock_disable(HAL_CMU_MOD_H_USBC);
2427 #ifndef USB_HIGH_SPEED
2428 aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_USB_PLL_DISABLE;
2429 #endif
2430
2431 if (hal_cmu_usb_get_clock_source() != CMU_USB_CLK_SRC_OSC_24M_X2)
2432 hal_cmu_pll_disable(pll, HAL_CMU_PLL_USER_USB);
2433 }
2434 #endif
2435
hal_cmu_apb_init_div(void)2436 void BOOT_TEXT_FLASH_LOC hal_cmu_apb_init_div(void)
2437 {
2438 // Divider defaults to 2 (div = reg_val + 2)
2439 //cmu->SYS_DIV = SET_BITFIELD(cmu->SYS_DIV, CMU_CFG_DIV_PCLK, 0);
2440 }
2441
hal_cmu_periph_set_div(uint32_t div)2442 int hal_cmu_periph_set_div(uint32_t div)
2443 {
2444 uint32_t lock;
2445 int ret = 0;
2446
2447 if (div == 0 || div > ((AON_CMU_CFG_DIV_PER_MASK >> AON_CMU_CFG_DIV_PER_SHIFT) + 2)) {
2448 ret = 1;
2449 } else {
2450 lock = int_lock();
2451 if (div == 1) {
2452 aoncmu->CLK_SELECT |= AON_CMU_BYPASS_DIV_PER;
2453 } else {
2454 div -= 2;
2455 aoncmu->CLK_SELECT = (aoncmu->CLK_SELECT & ~(AON_CMU_CFG_DIV_PER_MASK | AON_CMU_BYPASS_DIV_PER)) |
2456 AON_CMU_CFG_DIV_PER(div);
2457 }
2458 int_unlock(lock);
2459 }
2460
2461 return ret;
2462 }
2463
2464 #define PERPH_SET_DIV_FUNC(f, F, r) \
2465 int hal_cmu_ ##f## _set_div(uint32_t div) \
2466 { \
2467 uint32_t lock; \
2468 int ret = 0; \
2469 lock = int_lock(); \
2470 if (div < 2 || div > ((CMU_CFG_DIV_ ##F## _MASK >> CMU_CFG_DIV_ ##F## _SHIFT) + 2)) { \
2471 cmu->r &= ~(CMU_SEL_OSCX2_ ##F | CMU_SEL_PLL_ ##F | CMU_EN_PLL_ ##F); \
2472 ret = 1; \
2473 } else { \
2474 div -= 2; \
2475 cmu->r = (cmu->r & ~(CMU_CFG_DIV_ ##F## _MASK)) | CMU_SEL_OSCX2_ ##F | CMU_SEL_PLL_ ##F | \
2476 CMU_CFG_DIV_ ##F(div); \
2477 cmu->r |= CMU_EN_PLL_ ##F; \
2478 } \
2479 int_unlock(lock); \
2480 return ret; \
2481 }
2482
2483 PERPH_SET_DIV_FUNC(uart0, UART0, UART_CLK);
2484 PERPH_SET_DIV_FUNC(uart1, UART1, UART_CLK);
2485 PERPH_SET_DIV_FUNC(uart2, UART2, UART_CLK);
2486 PERPH_SET_DIV_FUNC(uart3, UART3, UART_CLK);
2487 PERPH_SET_DIV_FUNC(spi, SPI0, SYS_DIV);
2488 PERPH_SET_DIV_FUNC(slcd, SPI1, SYS_DIV);
2489 PERPH_SET_DIV_FUNC(sdmmc, SDMMC, PERIPH_CLK);
2490 PERPH_SET_DIV_FUNC(i2c, I2C, I2C_CLK);
2491
2492 #define PERPH_SET_FREQ_FUNC(f, F, r) \
2493 int hal_cmu_ ##f## _set_freq(enum HAL_CMU_PERIPH_FREQ_T freq) \
2494 { \
2495 uint32_t lock; \
2496 int ret = 0; \
2497 lock = int_lock(); \
2498 if (freq == HAL_CMU_PERIPH_FREQ_26M) { \
2499 cmu->r &= ~(CMU_SEL_OSCX2_ ##F | CMU_SEL_PLL_ ##F | CMU_EN_PLL_ ##F); \
2500 } else if (freq == HAL_CMU_PERIPH_FREQ_52M) { \
2501 cmu->r = (cmu->r & ~(CMU_SEL_PLL_ ##F | CMU_EN_PLL_ ##F)) | CMU_SEL_OSCX2_ ##F; \
2502 } else { \
2503 ret = 1; \
2504 } \
2505 int_unlock(lock); \
2506 return ret; \
2507 }
2508
2509 PERPH_SET_FREQ_FUNC(uart0, UART0, UART_CLK);
2510 PERPH_SET_FREQ_FUNC(uart1, UART1, UART_CLK);
2511 PERPH_SET_FREQ_FUNC(uart2, UART2, UART_CLK);
2512 PERPH_SET_FREQ_FUNC(uart3, UART3, UART_CLK);
2513 PERPH_SET_FREQ_FUNC(spi, SPI0, SYS_DIV);
2514 PERPH_SET_FREQ_FUNC(slcd, SPI1, SYS_DIV);
2515 PERPH_SET_FREQ_FUNC(sdmmc, SDMMC, PERIPH_CLK);
2516 PERPH_SET_FREQ_FUNC(i2c, I2C, I2C_CLK);
2517
hal_cmu_ispi_set_freq(enum HAL_CMU_PERIPH_FREQ_T freq)2518 int hal_cmu_ispi_set_freq(enum HAL_CMU_PERIPH_FREQ_T freq)
2519 {
2520 uint32_t lock;
2521 int ret = 0;
2522
2523 lock = int_lock();
2524 if (freq == HAL_CMU_PERIPH_FREQ_26M) {
2525 cmu->SYS_DIV &= ~CMU_SEL_OSCX2_SPI2;
2526 } else if (freq == HAL_CMU_PERIPH_FREQ_52M) {
2527 cmu->SYS_DIV |= CMU_SEL_OSCX2_SPI2;
2528 } else {
2529 ret = 1;
2530 }
2531 int_unlock(lock);
2532
2533 return ret;
2534 }
2535
hal_cmu_sec_eng_clock_enable(void)2536 void hal_cmu_sec_eng_clock_enable(void)
2537 {
2538 hal_cmu_clock_enable(HAL_CMU_MOD_H_SEC_ENG);
2539 hal_cmu_clock_enable(HAL_CMU_MOD_P_SEC_ENG);
2540 hal_cmu_reset_clear(HAL_CMU_MOD_H_SEC_ENG);
2541 hal_cmu_reset_clear(HAL_CMU_MOD_P_SEC_ENG);
2542 }
2543
hal_cmu_sec_eng_clock_disable(void)2544 void hal_cmu_sec_eng_clock_disable(void)
2545 {
2546 hal_cmu_reset_set(HAL_CMU_MOD_H_SEC_ENG);
2547 hal_cmu_reset_set(HAL_CMU_MOD_P_SEC_ENG);
2548 hal_cmu_clock_disable(HAL_CMU_MOD_H_SEC_ENG);
2549 hal_cmu_clock_disable(HAL_CMU_MOD_P_SEC_ENG);
2550 }
2551
hal_cmu_clock_out_enable(enum HAL_CMU_CLOCK_OUT_ID_T id)2552 int hal_cmu_clock_out_enable(enum HAL_CMU_CLOCK_OUT_ID_T id)
2553 {
2554 uint32_t lock;
2555 uint32_t sel;
2556 uint32_t cfg;
2557
2558 enum CMU_CLK_OUT_SEL_T {
2559 CMU_CLK_OUT_SEL_AON = 0,
2560 CMU_CLK_OUT_SEL_CODEC = 1,
2561 CMU_CLK_OUT_SEL_BT = 2,
2562 CMU_CLK_OUT_SEL_MCU = 3,
2563 CMU_CLK_OUT_SEL_WF = 4,
2564
2565 CMU_CLK_OUT_SEL_QTY
2566 };
2567
2568 sel = CMU_CLK_OUT_SEL_QTY;
2569 cfg = 0;
2570
2571 if (id <= HAL_CMU_CLOCK_OUT_AON_SYS) {
2572 sel = CMU_CLK_OUT_SEL_AON;
2573 cfg = id - HAL_CMU_CLOCK_OUT_AON_32K;
2574 } else if (HAL_CMU_CLOCK_OUT_MCU_32K <= id && id <= HAL_CMU_CLOCK_OUT_MCU_I2S1) {
2575 sel = CMU_CLK_OUT_SEL_MCU;
2576 lock = int_lock();
2577 cmu->PERIPH_CLK = SET_BITFIELD(cmu->PERIPH_CLK, CMU_CFG_CLK_OUT, id - HAL_CMU_CLOCK_OUT_MCU_32K);
2578 int_unlock(lock);
2579 } else if (HAL_CMU_CLOCK_OUT_CODEC_ADC_ANA <= id && id <= HAL_CMU_CLOCK_OUT_CODEC_HCLK) {
2580 sel = CMU_CLK_OUT_SEL_CODEC;
2581 hal_codec_select_clock_out(id - HAL_CMU_CLOCK_OUT_CODEC_ADC_ANA);
2582 } else if (HAL_CMU_CLOCK_OUT_BT_NONE <= id && id <= HAL_CMU_CLOCK_OUT_BT_DACD8) {
2583 sel = CMU_CLK_OUT_SEL_BT;
2584 btcmu->CLK_OUT = SET_BITFIELD(btcmu->CLK_OUT, BT_CMU_CFG_CLK_OUT, id - HAL_CMU_CLOCK_OUT_BT_NONE);
2585 } else if (HAL_CMU_CLOCK_OUT_WF_32K <= id && id <= HAL_CMU_CLOCK_OUT_WF_BBDIGFIFO) {
2586 sel = CMU_CLK_OUT_SEL_WF;
2587 wlancmu->CLK_OUT = SET_BITFIELD(wlancmu->CLK_OUT, WLAN_CMU_CFG_CLK_OUT, id - HAL_CMU_CLOCK_OUT_WF_32K);
2588 }
2589
2590 if (sel < CMU_CLK_OUT_SEL_QTY) {
2591 lock = int_lock();
2592 aoncmu->CLK_OUT = (aoncmu->CLK_OUT & ~(AON_CMU_SEL_CLK_OUT_MASK | AON_CMU_CFG_CLK_OUT_MASK)) |
2593 AON_CMU_SEL_CLK_OUT(sel) | AON_CMU_CFG_CLK_OUT(cfg) | AON_CMU_EN_CLK_OUT;
2594 int_unlock(lock);
2595
2596 return 0;
2597 }
2598
2599 return 1;
2600 }
2601
hal_cmu_clock_out_disable(void)2602 void hal_cmu_clock_out_disable(void)
2603 {
2604 uint32_t lock;
2605
2606 lock = int_lock();
2607 aoncmu->CLK_OUT &= ~AON_CMU_EN_CLK_OUT;
2608 int_unlock(lock);
2609 }
2610
hal_cmu_i2s_mclk_enable(enum HAL_CMU_I2S_MCLK_ID_T id)2611 int hal_cmu_i2s_mclk_enable(enum HAL_CMU_I2S_MCLK_ID_T id)
2612 {
2613 uint32_t lock;
2614
2615 lock = int_lock();
2616 aoncmu->CODEC_DIV = SET_BITFIELD(aoncmu->CODEC_DIV, AON_CMU_SEL_I2S_MCLK, id) | AON_CMU_EN_I2S_MCLK;
2617 int_unlock(lock);
2618
2619 return 0;
2620 }
2621
hal_cmu_i2s_mclk_disable(void)2622 void hal_cmu_i2s_mclk_disable(void)
2623 {
2624 uint32_t lock;
2625
2626 lock = int_lock();
2627 aoncmu->CODEC_DIV &= ~AON_CMU_EN_I2S_MCLK;
2628 int_unlock(lock);
2629 }
2630
hal_cmu_pwm_set_freq(enum HAL_PWM_ID_T id,uint32_t freq)2631 int hal_cmu_pwm_set_freq(enum HAL_PWM_ID_T id, uint32_t freq)
2632 {
2633 uint32_t lock;
2634 int clk_32k;
2635 uint32_t div;
2636
2637 if (id >= HAL_PWM_ID_QTY) {
2638 return 1;
2639 }
2640
2641 if (freq == 0) {
2642 clk_32k = 1;
2643 div = 0;
2644 } else {
2645 clk_32k = 0;
2646 div = hal_cmu_get_crystal_freq() / freq;
2647 if (div < 2) {
2648 return -1;
2649 }
2650
2651 div -= 2;
2652 if ((div & (AON_CMU_CFG_DIV_PWM0_MASK >> AON_CMU_CFG_DIV_PWM0_SHIFT)) != div) {
2653 return -2;
2654 }
2655 }
2656
2657 lock = int_lock();
2658 if (id == HAL_PWM_ID_0) {
2659 aoncmu->PWM01_CLK = (aoncmu->PWM01_CLK & ~(AON_CMU_CFG_DIV_PWM0_MASK | AON_CMU_SEL_PWM0_OSC | AON_CMU_EN_CLK_PWM0_OSC)) |
2660 AON_CMU_CFG_DIV_PWM0(div) | (clk_32k ? 0 : (AON_CMU_SEL_PWM0_OSC | AON_CMU_EN_CLK_PWM0_OSC));
2661 } else if (id == HAL_PWM_ID_1) {
2662 aoncmu->PWM01_CLK = (aoncmu->PWM01_CLK & ~(AON_CMU_CFG_DIV_PWM1_MASK | AON_CMU_SEL_PWM1_OSC | AON_CMU_EN_CLK_PWM1_OSC)) |
2663 AON_CMU_CFG_DIV_PWM1(div) | (clk_32k ? 0 : (AON_CMU_SEL_PWM1_OSC | AON_CMU_EN_CLK_PWM1_OSC));
2664 } else if (id == HAL_PWM_ID_2) {
2665 aoncmu->PWM23_CLK = (aoncmu->PWM23_CLK & ~(AON_CMU_CFG_DIV_PWM2_MASK | AON_CMU_SEL_PWM2_OSC | AON_CMU_EN_CLK_PWM2_OSC)) |
2666 AON_CMU_CFG_DIV_PWM2(div) | (clk_32k ? 0 : (AON_CMU_SEL_PWM2_OSC | AON_CMU_EN_CLK_PWM2_OSC));
2667 } else if (id == HAL_PWM_ID_3) {
2668 aoncmu->PWM23_CLK = (aoncmu->PWM23_CLK & ~(AON_CMU_CFG_DIV_PWM3_MASK | AON_CMU_SEL_PWM3_OSC | AON_CMU_EN_CLK_PWM3_OSC)) |
2669 AON_CMU_CFG_DIV_PWM3(div) | (clk_32k ? 0 : (AON_CMU_SEL_PWM3_OSC | AON_CMU_EN_CLK_PWM3_OSC));
2670 } else if (id == HAL_PWM1_ID_0) {
2671 aoncmu->PWM45_CLK = (aoncmu->PWM45_CLK & ~(AON_CMU_CFG_DIV_PWM4_MASK | AON_CMU_SEL_PWM4_OSC | AON_CMU_EN_CLK_PWM4_OSC)) |
2672 AON_CMU_CFG_DIV_PWM4(div) | (clk_32k ? 0 : (AON_CMU_SEL_PWM4_OSC | AON_CMU_EN_CLK_PWM4_OSC));
2673 } else if (id == HAL_PWM1_ID_1) {
2674 aoncmu->PWM45_CLK = (aoncmu->PWM45_CLK & ~(AON_CMU_CFG_DIV_PWM5_MASK | AON_CMU_SEL_PWM5_OSC | AON_CMU_EN_CLK_PWM5_OSC)) |
2675 AON_CMU_CFG_DIV_PWM5(div) | (clk_32k ? 0 : (AON_CMU_SEL_PWM5_OSC | AON_CMU_EN_CLK_PWM5_OSC));
2676 } else if (id == HAL_PWM1_ID_2) {
2677 aoncmu->PWM67_CLK = (aoncmu->PWM67_CLK & ~(AON_CMU_CFG_DIV_PWM6_MASK | AON_CMU_SEL_PWM6_OSC | AON_CMU_EN_CLK_PWM6_OSC)) |
2678 AON_CMU_CFG_DIV_PWM6(div) | (clk_32k ? 0 : (AON_CMU_SEL_PWM6_OSC | AON_CMU_EN_CLK_PWM6_OSC));
2679 } else if (id == HAL_PWM1_ID_3) {
2680 aoncmu->PWM67_CLK = (aoncmu->PWM67_CLK & ~(AON_CMU_CFG_DIV_PWM7_MASK | AON_CMU_SEL_PWM7_OSC | AON_CMU_EN_CLK_PWM7_OSC)) |
2681 AON_CMU_CFG_DIV_PWM7(div) | (clk_32k ? 0 : (AON_CMU_SEL_PWM7_OSC | AON_CMU_EN_CLK_PWM7_OSC));
2682 } else {
2683 ASSERT(0,"PWM id error!");
2684 }
2685 int_unlock(lock);
2686 return 0;
2687 }
2688
hal_cmu_jtag_enable(void)2689 void hal_cmu_jtag_enable(void)
2690 {
2691 uint32_t lock;
2692
2693 lock = int_lock();
2694 cmu->MCU_TIMER &= ~(CMU_SECURE_BOOT_JTAG | CMU_SECURE_BOOT_I2C);
2695 int_unlock(lock);
2696 }
2697
hal_cmu_jtag_disable(void)2698 void hal_cmu_jtag_disable(void)
2699 {
2700 uint32_t lock;
2701
2702 lock = int_lock();
2703 cmu->MCU_TIMER |= (CMU_SECURE_BOOT_JTAG | CMU_SECURE_BOOT_I2C);
2704 int_unlock(lock);
2705 }
2706
hal_cmu_jtag_clock_enable(void)2707 void hal_cmu_jtag_clock_enable(void)
2708 {
2709 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_JTAG_ENABLE;
2710 }
2711
hal_cmu_jtag_clock_disable(void)2712 void hal_cmu_jtag_clock_disable(void)
2713 {
2714 aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_TOP_JTAG_DISABLE;
2715 }
2716
hal_cmu_jtag_set_cp(void)2717 void hal_cmu_jtag_set_cp(void)
2718 {
2719 cmu->PERIPH_CLK |= CMU_JTAG_SEL_CP;
2720 }
2721
hal_cmu_jtag_set_a7(void)2722 void hal_cmu_jtag_set_a7(void)
2723 {
2724 cmu->PERIPH_CLK |= CMU_JTAG_SEL_A7;
2725 }
2726
hal_cmu_rom_clock_init(void)2727 void hal_cmu_rom_clock_init(void)
2728 {
2729 aoncmu->CODEC_DIV = (aoncmu->CODEC_DIV & ~AON_CMU_SEL_AON_OSCX2) | AON_CMU_SEL_AON_OSC;
2730 // Enable PMU fast clock
2731 //aoncmu->CLK_OUT = (aoncmu->CLK_OUT & ~AON_CMU_SEL_DCDC_PLL) | AON_CMU_SEL_DCDC_OSC | AON_CMU_BYPASS_DIV_DCDC | AON_CMU_EN_CLK_DCDC0;
2732
2733 hal_cmu_dma_req_init();
2734
2735 // Debug Select CMU REG F4
2736 cmu->MCU_TIMER = SET_BITFIELD(cmu->MCU_TIMER, CMU_DEBUG_REG_SEL, CMU_DEBUG_REG_SEL_DEBUG);
2737 }
2738
hal_cmu_init_chip_feature(uint16_t feature)2739 void hal_cmu_init_chip_feature(uint16_t feature)
2740 {
2741 aoncmu->CHIP_FEATURE = feature | AON_CMU_EFUSE_LOCK;
2742 }
2743
hal_cmu_osc_x2_enable(void)2744 void BOOT_TEXT_FLASH_LOC hal_cmu_osc_x2_enable(void)
2745 {
2746 // Debug Select CMU REG F4
2747 cmu->MCU_TIMER = SET_BITFIELD(cmu->MCU_TIMER, CMU_DEBUG_REG_SEL, CMU_DEBUG_REG_SEL_DEBUG);
2748 // Power on OSCX2
2749 aoncmu->PLL_ENABLE = AON_CMU_PU_OSCX2_ENABLE;
2750 // Disable DIG OSCX2
2751 aoncmu->CLK_SELECT &= ~AON_CMU_SEL_OSCX2_DIG;
2752 // Enable OSCX2
2753 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_OSCX2_ENABLE | AON_CMU_EN_CLK_MCU_OSCX2_ENABLE;
2754 }
2755
hal_cmu_osc_x4_enable(void)2756 void BOOT_TEXT_FLASH_LOC hal_cmu_osc_x4_enable(void)
2757 {
2758 #ifdef ANA_26M_X4_ENABLE
2759 // Power on OSCX4
2760 aoncmu->PLL_ENABLE = AON_CMU_PU_OSCX4_ENABLE;
2761 // Disable DIG OSCX4
2762 aoncmu->CLK_SELECT &= ~AON_CMU_SEL_OSCX4_DIG;
2763 // Enable OSCX4
2764 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_OSCX4_ENABLE;
2765 #endif
2766 }
2767
2768 struct CMU_DMA_PER_2_REQ_T {
2769 enum HAL_DMA_PERIPH_T periph;
2770 enum CMU_DMA_REQ_T req;
2771 };
2772 const static BOOT_RODATA_FLASH_LOC struct CMU_DMA_PER_2_REQ_T periph_map[] = {
2773 {HAL_DMA_PERIPH_NULL, CMU_DMA_REQ_NULL},
2774 {HAL_AUDMA_CODEC_RX, CMU_DMA_REQ_CODEC_RX},
2775 {HAL_AUDMA_CODEC_TX, CMU_DMA_REQ_CODEC_TX},
2776 {HAL_AUDMA_DSD_RX, CMU_DMA_REQ_DSD_RX},
2777 {HAL_AUDMA_DSD_TX, CMU_DMA_REQ_DSD_TX},
2778 {HAL_GPDMA_IR_RX, CMU_DMA_REQ_IR_RX},
2779 {HAL_GPDMA_IR_TX, CMU_DMA_REQ_IR_TX},
2780 {HAL_GPDMA_FLASH1, CMU_DMA_REQ_FLS1},
2781 {HAL_GPDMA_FLASH0, CMU_DMA_REQ_FLS0},
2782 {HAL_AUDMA_BTDUMP, CMU_DMA_REQ_BTDUMP},
2783 {HAL_GPDMA_SDMMC, CMU_DMA_REQ_SDEMMC},
2784 {HAL_GPDMA_I2C0_RX, CMU_DMA_REQ_I2C0_RX},
2785 {HAL_GPDMA_I2C0_TX, CMU_DMA_REQ_I2C0_TX},
2786 {HAL_GPDMA_I2C1_RX, CMU_DMA_REQ_I2C1_RX},
2787 {HAL_GPDMA_I2C1_TX, CMU_DMA_REQ_I2C1_TX},
2788 {HAL_GPDMA_I2C2_RX, CMU_DMA_REQ_I2C2_RX},
2789 {HAL_GPDMA_I2C2_TX, CMU_DMA_REQ_I2C2_TX},
2790 {HAL_GPDMA_SPI_RX, CMU_DMA_REQ_SPILCD0_RX},
2791 {HAL_GPDMA_SPI_TX, CMU_DMA_REQ_SPILCD0_TX},
2792 {HAL_GPDMA_SPILCD_RX, CMU_DMA_REQ_SPILCD1_RX},
2793 {HAL_GPDMA_SPILCD_TX, CMU_DMA_REQ_SPILCD1_TX},
2794 {HAL_GPDMA_ISPI_RX, CMU_DMA_REQ_SPI_ITN_RX},
2795 {HAL_GPDMA_ISPI_TX, CMU_DMA_REQ_SPI_ITN_TX},
2796 {HAL_GPDMA_UART0_RX, CMU_DMA_REQ_UART0_RX},
2797 {HAL_GPDMA_UART0_TX, CMU_DMA_REQ_UART0_TX},
2798 {HAL_GPDMA_UART1_RX, CMU_DMA_REQ_UART1_RX},
2799 {HAL_GPDMA_UART1_TX, CMU_DMA_REQ_UART1_TX},
2800 {HAL_GPDMA_UART2_RX, CMU_DMA_REQ_UART2_RX},
2801 {HAL_GPDMA_UART2_TX, CMU_DMA_REQ_UART2_TX},
2802 {HAL_GPDMA_UART3_RX, CMU_DMA_REQ_UART3_RX},
2803 {HAL_GPDMA_UART3_TX, CMU_DMA_REQ_UART3_TX},
2804 {HAL_AUDMA_BTPCM_RX, CMU_DMA_REQ_PCM_RX},
2805 {HAL_AUDMA_BTPCM_TX, CMU_DMA_REQ_PCM_TX},
2806 {HAL_AUDMA_I2S0_RX, CMU_DMA_REQ_I2S0_RX},
2807 {HAL_AUDMA_I2S0_TX, CMU_DMA_REQ_I2S0_TX},
2808 {HAL_AUDMA_I2S1_RX, CMU_DMA_REQ_I2S1_RX},
2809 {HAL_AUDMA_I2S1_TX, CMU_DMA_REQ_I2S1_TX},
2810 {HAL_AUDMA_SPDIF0_RX, CMU_DMA_REQ_SPDIF0_RX},
2811 {HAL_AUDMA_SPDIF0_TX, CMU_DMA_REQ_SPDIF0_TX},
2812 };
2813
hal_dma_periph_2_idx(enum HAL_DMA_PERIPH_T periph)2814 enum CMU_DMA_REQ_T BOOT_TEXT_FLASH_LOC hal_dma_periph_2_idx(enum HAL_DMA_PERIPH_T periph)
2815 {
2816 uint32_t i;
2817 for (i=0; i<ARRAY_SIZE(periph_map); ++i)
2818 if (periph_map[i].periph == periph)
2819 return periph_map[i].req;
2820 return CMU_DMA_REQ_NULL;
2821 }
2822
hal_cmu_dma_req_init(void)2823 void BOOT_TEXT_FLASH_LOC hal_cmu_dma_req_init(void)
2824 {
2825 // DMA channel config
2826 cmu->ADMA_CH0_4_REQ =
2827 CMU_ADMA_CH0_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[0])) |
2828 CMU_ADMA_CH1_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[1])) |
2829 CMU_ADMA_CH2_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[2])) |
2830 CMU_ADMA_CH3_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[3])) |
2831 CMU_ADMA_CH4_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[4]));
2832 cmu->ADMA_CH5_9_REQ =
2833 CMU_ADMA_CH5_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[5])) |
2834 CMU_ADMA_CH6_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[6])) |
2835 CMU_ADMA_CH7_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[7])) |
2836 CMU_ADMA_CH8_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[8])) |
2837 CMU_ADMA_CH9_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[9]));
2838 cmu->ADMA_CH10_14_REQ =
2839 CMU_ADMA_CH10_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[10])) |
2840 CMU_ADMA_CH11_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[11])) |
2841 CMU_ADMA_CH12_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[12])) |
2842 CMU_ADMA_CH13_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[13])) |
2843 CMU_ADMA_CH14_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[14]));
2844 cmu->ADMA_CH15_REQ =
2845 CMU_ADMA_CH15_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[15]));
2846
2847 cmu->GDMA_CH0_4_REQ =
2848 CMU_GDMA_CH0_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[0])) |
2849 CMU_GDMA_CH1_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[1])) |
2850 CMU_GDMA_CH2_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[2])) |
2851 CMU_GDMA_CH3_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[3])) |
2852 CMU_GDMA_CH4_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[4]));
2853 cmu->GDMA_CH5_9_REQ =
2854 CMU_GDMA_CH5_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[5])) |
2855 CMU_GDMA_CH6_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[6])) |
2856 CMU_GDMA_CH7_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[7])) |
2857 CMU_GDMA_CH8_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[8])) |
2858 CMU_GDMA_CH9_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[9]));
2859 cmu->GDMA_CH10_14_REQ =
2860 CMU_GDMA_CH10_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[10])) |
2861 CMU_GDMA_CH11_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[11])) |
2862 CMU_GDMA_CH12_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[12])) |
2863 CMU_GDMA_CH13_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[13])) |
2864 CMU_GDMA_CH14_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[14]));
2865 cmu->GDMA_CH15_REQ =
2866 CMU_GDMA_CH15_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[15]));
2867 }
2868
hal_cmu_module_init_state(void)2869 void BOOT_TEXT_FLASH_LOC hal_cmu_module_init_state(void)
2870 {
2871 aoncmu->CLK_OUT = AON_CMU_EN_CLK_DCDC0 | AON_CMU_CFG_DIV_DCDC(1);
2872 aoncmu->CODEC_DIV = (aoncmu->CODEC_DIV & ~AON_CMU_SEL_AON_OSCX2) | AON_CMU_SEL_AON_OSC;
2873 // Slow down PMU fast clock
2874 //aoncmu->CLK_OUT = (aoncmu->CLK_OUT & ~(AON_CMU_BYPASS_DIV_DCDC | AON_CMU_CFG_DIV_DCDC_MASK)) | AON_CMU_CFG_DIV_DCDC(2);
2875
2876 hal_cmu_sram_init();
2877
2878 hal_cmu_dma_req_init();
2879
2880 #ifndef SIMU
2881 cmu->ORESET_SET = SYS_ORST_USB | SYS_ORST_USB32K | SYS_ORST_PSRAM1G | SYS_ORST_PSRAM200 | SYS_ORST_SDMMC |
2882 SYS_ORST_WDT | SYS_ORST_TIMER2 | SYS_ORST_I2C0 | SYS_ORST_I2C1 | SYS_ORST_I2C2 | SYS_ORST_SPI | SYS_ORST_SLCD | SYS_ORST_SPI_PHY |
2883 #ifndef ARM_CMNS
2884 SYS_ORST_UART0 |
2885 #endif
2886 SYS_ORST_UART1 | SYS_ORST_UART2 | SYS_ORST_UART3 | SYS_ORST_PCM | SYS_ORST_I2S0 | SYS_ORST_I2S1 |
2887 SYS_ORST_SPDIF0 | SYS_ORST_A7 | SYS_ORST_TSF | SYS_ORST_WDT_AP | SYS_ORST_TIMER0_AP | SYS_ORST_TIMER1_AP | SYS_ORST_FLASH1;
2888 cmu->PRESET_SET = SYS_PRST_WDT | SYS_PRST_TIMER2 | SYS_PRST_I2C0 | SYS_PRST_I2C1 | SYS_PRST_I2C2 | SYS_PRST_IR |
2889 SYS_PRST_SPI | SYS_PRST_SLCD | SYS_PRST_SPI_PHY |
2890 #ifndef ARM_CMNS
2891 SYS_PRST_UART0 |
2892 #endif
2893 SYS_PRST_UART1 | SYS_PRST_UART2 | SYS_PRST_UART3 |
2894 SYS_PRST_PCM | SYS_PRST_I2S0 | SYS_PRST_I2S1 | SYS_PRST_SPDIF0 | SYS_PRST_TQWF | SYS_PRST_TQA7;
2895 cmu->HRESET_SET = SYS_HRST_CORE1 | SYS_HRST_BCM | SYS_HRST_USBC | SYS_HRST_USBH | SYS_HRST_CODEC |
2896 SYS_HRST_AX2H_A7 | SYS_HRST_PSRAM1G | SYS_HRST_PSRAM200 | SYS_HRST_BT_DUMP | SYS_HRST_WF_DUMP | SYS_HRST_SDMMC |
2897 SYS_HRST_CHECKSUM | SYS_HRST_CRC | SYS_HRST_FLASH1;
2898 cmu->XRESET_SET = SYS_XRST_DMA | SYS_XRST_NIC | SYS_XRST_IMEMLO | SYS_XRST_IMEMHI | SYS_XRST_PSRAM1G | SYS_XRST_PER |
2899 SYS_XRST_PDBG | SYS_XRST_CORE0 | SYS_XRST_CORE1 | SYS_XRST_CORE2 | SYS_XRST_CORE3 | SYS_XRST_DBG | SYS_XRST_SCU |
2900 SYS_XRST_DISPLAYX | SYS_XRST_DISPLAYH | SYS_XRST_CSI | SYS_XRST_DSI | SYS_XRST_PSRAM1GMX | SYS_XRST_GPV_MAIN | SYS_XRST_GPV_PSRAM1G;
2901 cmu->APRESET_SET = SYS_APRST_BOOTREG | SYS_APRST_WDT| SYS_APRST_TIMER0 | SYS_APRST_TIMER1 | SYS_APRST_TQ | SYS_APRST_DAP |
2902 SYS_APRST_DISPLAY | SYS_APRST_CSI;
2903 cmu->QRESET_SET = SYS_QRST_DSI_32K | SYS_QRST_DSI_PN | SYS_QRST_DSI_TV | SYS_QRST_DSI_PIX |
2904 SYS_QRST_DSI_DSI | SYS_QRST_CSI_LANE | SYS_QRST_CSI_PIX | SYS_QRST_CSI_LANG | SYS_QRST_IR;
2905
2906 cmu->OCLK_DISABLE = SYS_OCLK_USB | SYS_OCLK_USB32K | SYS_OCLK_PSRAM1G | SYS_OCLK_PSRAM200 | SYS_OCLK_SDMMC |
2907 SYS_OCLK_WDT | SYS_OCLK_TIMER2 | SYS_OCLK_I2C0 | SYS_OCLK_I2C1 | SYS_OCLK_I2C2 | SYS_OCLK_SPI | SYS_OCLK_SLCD | SYS_OCLK_SPI_PHY |
2908 #ifndef ARM_CMNS
2909 SYS_OCLK_UART0 |
2910 #endif
2911 SYS_OCLK_UART1 | SYS_OCLK_UART2 | SYS_OCLK_UART3 | SYS_OCLK_PCM | SYS_OCLK_I2S0 | SYS_OCLK_I2S1 |
2912 SYS_OCLK_SPDIF0 | SYS_OCLK_A7 | SYS_OCLK_TSF | SYS_OCLK_WDT_AP | SYS_OCLK_TIMER0_AP | SYS_OCLK_TIMER1_AP | SYS_OCLK_FLASH1;
2913 cmu->PCLK_DISABLE = SYS_PCLK_WDT | SYS_PCLK_TIMER2 | SYS_PCLK_I2C0 | SYS_PCLK_I2C1 | SYS_PCLK_I2C2 | SYS_PCLK_IR |
2914 SYS_PCLK_SPI | SYS_PCLK_SLCD | SYS_PCLK_SPI_PHY |
2915 #ifndef ARM_CMNS
2916 SYS_PCLK_UART0 |
2917 #endif
2918 SYS_PCLK_UART1 | SYS_PCLK_UART2 | SYS_PCLK_UART3 |
2919 SYS_PCLK_PCM | SYS_PCLK_I2S0 | SYS_PCLK_I2S1 | SYS_PCLK_SPDIF0 | SYS_PCLK_TQWF | SYS_PCLK_TQA7;
2920 cmu->HCLK_DISABLE = SYS_HCLK_CORE1 | SYS_HCLK_BCM | SYS_HCLK_USBC | SYS_HCLK_USBH | SYS_HCLK_CODEC |
2921 SYS_HCLK_AX2H_A7 | SYS_HCLK_PSRAM1G | SYS_HCLK_PSRAM200 | SYS_HCLK_BT_DUMP | SYS_HCLK_WF_DUMP | SYS_HCLK_SDMMC |
2922 SYS_HCLK_CHECKSUM | SYS_HCLK_CRC | SYS_HCLK_FLASH1;
2923 cmu->XCLK_DISABLE = SYS_XCLK_DMA | SYS_XCLK_NIC | SYS_XCLK_IMEMLO | SYS_XCLK_IMEMHI | SYS_XCLK_PSRAM1G | SYS_XCLK_PER |
2924 SYS_XCLK_PDBG | SYS_XCLK_CORE0 | SYS_XCLK_CORE1 | SYS_XCLK_CORE2 | SYS_XCLK_CORE3 | SYS_XCLK_DBG | SYS_XCLK_SCU |
2925 SYS_XCLK_DISPLAYX | SYS_XCLK_DISPLAYH | SYS_XCLK_CSI | SYS_XCLK_DSI | SYS_XCLK_PSRAM1GMX | SYS_XCLK_GPV_MAIN | SYS_XCLK_GPV_PSRAM1G;;
2926 cmu->APCLK_DISABLE = SYS_APCLK_BOOTREG | SYS_APCLK_WDT| SYS_APCLK_TIMER0 | SYS_APCLK_TIMER1 | SYS_APCLK_TQ | SYS_APCLK_DAP |
2927 SYS_APCLK_DISPLAY | SYS_APCLK_CSI;
2928 cmu->QCLK_DISABLE = SYS_QCLK_DSI_32K | SYS_QCLK_DSI_PN | SYS_QCLK_DSI_TV | SYS_QCLK_DSI_PIX |
2929 SYS_QCLK_DSI_DSI | SYS_QCLK_CSI_LANE | SYS_QCLK_CSI_PIX | SYS_QCLK_CSI_LANG | SYS_QCLK_IR;
2930
2931 aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_CODEC_DISABLE | AON_CMU_EN_CLK_CODECIIR_DISABLE | AON_CMU_EN_CLK_CODECRS0_DISABLE |
2932 AON_CMU_EN_CLK_CODECRS1_DISABLE | AON_CMU_EN_CLK_CODECHCLK_DISABLE | AON_CMU_EN_CLK_VAD32K_DISABLE |
2933 AON_CMU_EN_CLK_BT_DISABLE | AON_CMU_EN_CLK_WF_DISABLE;
2934
2935 aoncmu->RESET_SET = AON_CMU_ARESETN_SET(AON_ARST_PWM | AON_ARST_PWM1) |
2936 AON_CMU_ORESETN_SET(AON_ORST_PWM0 | AON_ORST_PWM1 | AON_ORST_PWM2 | AON_ORST_PWM3 |
2937 AON_ORST_PWM4 | AON_ORST_PWM5 | AON_ORST_PWM6 | AON_ORST_PWM7 | AON_ORST_BTAON);
2938
2939 aoncmu->SOFT_RSTN_SET = AON_CMU_SOFT_RSTN_CODEC_SET |
2940 AON_CMU_SOFT_RSTN_A7_SET | AON_CMU_SOFT_RSTN_A7CPU_SET |
2941 AON_CMU_SOFT_RSTN_WF_SET | AON_CMU_SOFT_RSTN_WFCPU_SET |
2942 AON_CMU_SOFT_RSTN_BT_SET | AON_CMU_SOFT_RSTN_BTCPU_SET;
2943
2944 aoncmu->MOD_CLK_DISABLE = AON_CMU_MANUAL_ACLK_DISABLE(AON_ACLK_PWM) |
2945 AON_CMU_MANUAL_OCLK_DISABLE(AON_OCLK_PWM0 | AON_OCLK_PWM1 | AON_OCLK_PWM2 | AON_OCLK_PWM3 | AON_OCLK_BTAON);
2946
2947 aoncmu->MOD_CLK_MODE &= ~AON_CMU_MODE_ACLK(AON_ACLK_CMU | AON_ACLK_GPIO_INT | AON_ACLK_WDT | AON_ACLK_PWM |
2948 AON_ACLK_TIMER | AON_ACLK_IOMUX);
2949 cmu->PCLK_MODE &= ~(SYS_PCLK_CMU | SYS_PCLK_WDT | SYS_PCLK_TIMER0 | SYS_PCLK_TIMER1 | SYS_PCLK_TIMER2);
2950
2951 aoncmu->MIPI_CLK &= ~(AON_CMU_EN_CLK_PIX_DSI | AON_CMU_EN_CLK_PIX_CSI | AON_CMU_POL_CLK_DSI_IN |
2952 AON_CMU_POL_CLK_CSI_IN);
2953
2954 //cmu->HCLK_MODE = 0;
2955 //cmu->PCLK_MODE = SYS_PCLK_UART0 | SYS_PCLK_UART1 | SYS_PCLK_UART2;
2956 //cmu->OCLK_MODE = 0;
2957 #endif
2958 hal_psc_init();
2959 }
2960
hal_cmu_ema_init(void)2961 void BOOT_TEXT_FLASH_LOC hal_cmu_ema_init(void)
2962 {
2963 // Never change EMA
2964 }
2965
hal_cmu_lpu_wait_26m_ready(void)2966 void hal_cmu_lpu_wait_26m_ready(void)
2967 {
2968 while ((cmu->WAKEUP_CLK_CFG & (CMU_LPU_AUTO_SWITCH26 | CMU_LPU_STATUS_26M)) ==
2969 CMU_LPU_AUTO_SWITCH26);
2970 }
2971
hal_cmu_lpu_busy(void)2972 int hal_cmu_lpu_busy(void)
2973 {
2974 if ((cmu->WAKEUP_CLK_CFG & (CMU_LPU_AUTO_SWITCH26 | CMU_LPU_STATUS_26M)) ==
2975 CMU_LPU_AUTO_SWITCH26) {
2976 return 1;
2977 }
2978 if ((cmu->WAKEUP_CLK_CFG & (CMU_LPU_AUTO_SWITCHPLL | CMU_LPU_STATUS_PLL)) ==
2979 CMU_LPU_AUTO_SWITCHPLL) {
2980 return 1;
2981 }
2982 return 0;
2983 }
2984
hal_cmu_lpu_init(enum HAL_CMU_LPU_CLK_CFG_T cfg)2985 int BOOT_TEXT_FLASH_LOC hal_cmu_lpu_init(enum HAL_CMU_LPU_CLK_CFG_T cfg)
2986 {
2987 uint32_t lpu_clk;
2988 uint32_t timer_26m;
2989 uint32_t timer_pll;
2990
2991 timer_26m = LPU_TIMER_US(TICKS_TO_US(HAL_CMU_26M_READY_TIMEOUT));
2992 timer_pll = LPU_TIMER_US(TICKS_TO_US(HAL_CMU_PLL_LOCKED_TIMEOUT));
2993
2994 if (cfg >= HAL_CMU_LPU_CLK_QTY) {
2995 return 1;
2996 }
2997 if ((timer_26m & (CMU_TIMER_WT26_MASK >> CMU_TIMER_WT26_SHIFT)) != timer_26m) {
2998 return 2;
2999 }
3000 if ((timer_pll & (CMU_TIMER_WTPLL_MASK >> CMU_TIMER_WTPLL_SHIFT)) != timer_pll) {
3001 return 3;
3002 }
3003 if (hal_cmu_lpu_busy()) {
3004 return -1;
3005 }
3006 lpu_clk = cmu->WAKEUP_CLK_CFG;
3007 lpu_clk &= ~(CMU_LPU_EN_MCU | CMU_LPU_EN_A7 | CMU_LPU_AUTO_SWITCHPLL | CMU_LPU_AUTO_SWITCH26);
3008
3009 if (cfg == HAL_CMU_LPU_CLK_26M) {
3010 lpu_clk |= CMU_LPU_EN_MCU | CMU_LPU_EN_A7 | CMU_LPU_AUTO_SWITCH26;
3011 } else if (cfg == HAL_CMU_LPU_CLK_PLL) {
3012 lpu_clk |= CMU_LPU_EN_MCU | CMU_LPU_EN_A7 | CMU_LPU_AUTO_SWITCHPLL | CMU_LPU_AUTO_SWITCH26;
3013 } else {
3014 }
3015
3016 if (lpu_clk & CMU_LPU_AUTO_SWITCH26) {
3017 // Disable RAM wakeup early
3018 cmu->MCU_TIMER &= ~CMU_RAM_RETN_UP_EARLY;
3019 // MCU/ROM/RAM auto clock gating (which depends on RAM gating signal)
3020 cmu->HCLK_MODE &= ~(SYS_HCLK_CORE0 | SYS_HCLK_ROM0 | SYS_HCLK_RAM0 | SYS_HCLK_RAM1 |
3021 SYS_HCLK_RAM2 | SYS_HCLK_RAM3 | SYS_HCLK_RAM4 | SYS_HCLK_RAM5);
3022 // AON_CMU enable auto switch 26M (AON_CMU must have selected 26M and disabled 52M/32K already)
3023 aoncmu->CODEC_DIV |= AON_CMU_LPU_AUTO_SWITCH26;
3024 } else {
3025 // AON_CMU disable auto switch 26M
3026 aoncmu->CODEC_DIV &= ~AON_CMU_LPU_AUTO_SWITCH26;
3027 }
3028
3029 lpu_clk |= CMU_TIMER_WT26(timer_26m);
3030 if (timer_pll) {
3031 lpu_clk |= CMU_TIMER_WTPLL(timer_pll);
3032 hal_sys_timer_delay(US_TO_TICKS(60));
3033 cmu->WAKEUP_CLK_CFG = lpu_clk;
3034 } else {
3035 lpu_clk |= CMU_TIMER_WTPLL(0);
3036 cmu->WAKEUP_CLK_CFG = lpu_clk;
3037 }
3038
3039 #ifndef ARM_CMNS
3040 hal_sec_init(); //need metal_id
3041 #endif
3042
3043 if (hal_get_chip_metal_id() >= HAL_CHIP_METAL_ID_4) {
3044 cmu->CMU_REMAP = CMU_REMAP(0xF); //psram cache and flash cache
3045 } else {
3046 cmu->CMU_REMAP = CMU_REMAP(0xC); //psram cache
3047 }
3048
3049 return 0;
3050 }
3051
cpu_sleep(uint32_t wakeup_cfg)3052 __STATIC_FORCEINLINE void cpu_sleep(uint32_t wakeup_cfg)
3053 {
3054 __DSB();
3055
3056 if (wakeup_cfg & (CMU_LPU_AUTO_SWITCHPLL | CMU_LPU_AUTO_SWITCH26)) {
3057 // 1) Avoid race condition between LPU state machine entry and IRQ wakeup:
3058 // Wait 4 (at least 2) cycles of 32K clock, or 3248 cycles of 26M clock.
3059 // 2) Avoid race condition between CPU clock gating and RAM access when waiting:
3060 // No consecutive RAM access is allowed.
3061 // This is related to instruction width/alignment, pipeline state, branch prediction state, etc.
3062 // Unfortunately, it is too hard to control all of these, especially on M33.
3063 __WFI();
3064 } else {
3065 __WFI();
3066 }
3067 }
3068
hal_cmu_lpu_sleep(enum HAL_CMU_LPU_SLEEP_MODE_T mode)3069 int SRAM_TEXT_LOC hal_cmu_lpu_sleep(enum HAL_CMU_LPU_SLEEP_MODE_T mode)
3070 {
3071 uint32_t start;
3072 uint32_t timeout;
3073 uint32_t saved_pll_cfg;
3074 uint32_t saved_clk_cfg;
3075 uint32_t saved_codec_div;
3076 uint32_t saved_top_clk;
3077 uint32_t wakeup_cfg;
3078 uint32_t saved_hclk;
3079 uint32_t saved_oclk;
3080
3081 saved_codec_div = aoncmu->CODEC_DIV;
3082 saved_top_clk = aoncmu->TOP_CLK_ENABLE;
3083 saved_pll_cfg = aoncmu->PLL_ENABLE;
3084 saved_clk_cfg = cmu->SYS_CLK_ENABLE;
3085 saved_hclk = cmu->HCLK_ENABLE;
3086 saved_oclk = cmu->OCLK_ENABLE;
3087
3088 // Switch VAD clock to AON and disable codec HCLK
3089 aoncmu->CODEC_DIV |= AON_CMU_SEL_CODECHCLK_MCU;
3090 if (mode == HAL_CMU_LPU_SLEEP_MODE_CHIP) {
3091 aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_CODECHCLK_DISABLE;
3092 } else {
3093 // Avoid auto-gating OSC and OSCX2
3094 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_OSCX2_ENABLE | AON_CMU_EN_CLK_TOP_OSC_ENABLE;
3095 }
3096
3097 if (mode == HAL_CMU_LPU_SLEEP_MODE_CHIP) {
3098 wakeup_cfg = cmu->WAKEUP_CLK_CFG;
3099 } else {
3100 wakeup_cfg = 0;
3101 }
3102
3103 // Disable memory/flash freq
3104 cmu->OCLK_DISABLE = SYS_OCLK_PSRAM1G | SYS_OCLK_PSRAM200 | SYS_OCLK_FLASH;
3105 cmu->HCLK_DISABLE = SYS_HCLK_PSRAM1G | SYS_HCLK_PSRAM200 | SYS_HCLK_FLASH;
3106
3107 #ifndef ROM_BUILD
3108 // Reset pll div if pll is enabled
3109 if (saved_pll_cfg & AON_CMU_PU_PLLUSB_ENABLE) {
3110 pmu_pll_div_reset_set(HAL_CMU_PLL_USB);
3111 }
3112 if (saved_pll_cfg & AON_CMU_PU_PLLDDR_ENABLE) {
3113 pmu_pll_div_reset_set(HAL_CMU_PLL_DDR);
3114 }
3115 if (saved_pll_cfg & AON_CMU_PU_PLLA7_ENABLE) {
3116 pmu_pll_div_reset_set(HAL_CMU_PLL_DSP);
3117 }
3118 if (saved_pll_cfg & AON_CMU_PU_PLLBB_DIV_MCU_ENABLE) {
3119 pmu_pll_div_reset_set(HAL_CMU_PLL_BB);
3120 }
3121 if (saved_pll_cfg & AON_CMU_PU_PLLBB_DIV_PS_ENABLE) {
3122 pmu_pll_div_reset_set(HAL_CMU_PLL_BB_PSRAM);
3123 }
3124 #endif
3125
3126 // Setup wakeup mask
3127 #ifdef __ARM_ARCH_ISA_ARM
3128 cmu->WAKEUP_MASK0 = GICDistributor->ISENABLER[0];
3129 cmu->WAKEUP_MASK1 = GICDistributor->ISENABLER[1];
3130 cmu->WAKEUP_MASK2 = GICDistributor->ISENABLER[2];
3131 #else
3132 cmu->WAKEUP_MASK0 = NVIC->ISER[0];
3133 cmu->WAKEUP_MASK1 = NVIC->ISER[1];
3134 cmu->WAKEUP_MASK2 = NVIC->ISER[2];
3135 #endif
3136
3137 // Switch system freq to 26M
3138 cmu->SYS_CLK_ENABLE = CMU_SEL_MCU_SLOW_ENABLE;
3139 cmu->SYS_CLK_DISABLE = CMU_SEL_MCU_OSC_4_DISABLE | CMU_SEL_MCU_OSC_2_DISABLE |
3140 CMU_SEL_MCU_OSCX4_DISABLE | CMU_SEL_MCU_FAST_DISABLE | CMU_SEL_MCU_PLL_DISABLE;
3141 cmu->SYS_CLK_DISABLE = CMU_RSTN_DIV_MCU_DISABLE;
3142 // Shutdown PLLs
3143 if (saved_pll_cfg & AON_CMU_PU_PLLUSB_ENABLE) {
3144 aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_TOP_PLLUSB_DISABLE;
3145 aoncmu->PLL_DISABLE = AON_CMU_PU_PLLUSB_DISABLE;
3146 }
3147 if (saved_pll_cfg & AON_CMU_PU_PLLDDR_ENABLE) {
3148 aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_TOP_PLLDDR_DISABLE;
3149 aoncmu->PLL_DISABLE = AON_CMU_PU_PLLDDR_DISABLE;
3150 }
3151 if (saved_pll_cfg & AON_CMU_PU_PLLA7_ENABLE) {
3152 aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_TOP_PLLA7_DISABLE;
3153 aoncmu->PLL_DISABLE = AON_CMU_PU_PLLA7_DISABLE;
3154 }
3155 if (saved_pll_cfg & AON_CMU_PU_PLLBB_DIV_MCU_ENABLE) {
3156 aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_TOP_PLLBB_DISABLE;
3157 aoncmu->PLL_DISABLE = AON_CMU_PU_PLLBB_DIV_MCU_DISABLE;
3158 }
3159 if (saved_pll_cfg & AON_CMU_PU_PLLBB_DIV_PS_ENABLE) {
3160 aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_TOP_PLLBB_PS_DISABLE;
3161 aoncmu->PLL_DISABLE = AON_CMU_PU_PLLBB_DIV_PS_DISABLE;
3162 }
3163 if (saved_pll_cfg & AON_CMU_PU_PLLBB_ENABLE) {
3164 aoncmu->PLL_DISABLE = AON_CMU_PU_PLLBB_DISABLE;
3165 }
3166 if (saved_pll_cfg & AON_CMU_PU_OSCX4_ENABLE) {
3167 aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_TOP_OSCX4_DISABLE;
3168 aoncmu->PLL_DISABLE = AON_CMU_PU_OSCX4_DISABLE;
3169 }
3170
3171 if (wakeup_cfg & CMU_LPU_AUTO_SWITCHPLL) {
3172 // Do nothing
3173 // Hardware will switch system freq to 32K and shutdown PLLs automatically
3174 } else {
3175 if (wakeup_cfg & CMU_LPU_AUTO_SWITCH26) {
3176 // Do nothing
3177 // Hardware will switch system freq to 32K automatically
3178 } else {
3179 // Manually switch AON_CMU clock to 32K
3180 aoncmu->CODEC_DIV &= ~(AON_CMU_SEL_AON_OSC | AON_CMU_SEL_AON_OSCX2);
3181 // Switch system freq to 32K
3182 cmu->SYS_CLK_DISABLE = CMU_SEL_MCU_SLOW_DISABLE;
3183 }
3184 }
3185
3186 if (wakeup_cfg & CMU_LPU_AUTO_SWITCH26) {
3187 // Enable auto memory retention
3188 cmu->SLEEP = (cmu->SLEEP & ~CMU_MANUAL_RAM_RETN) |
3189 CMU_DEEPSLEEP_EN | CMU_DEEPSLEEP_ROMRAM_EN | CMU_DEEPSLEEP_START;
3190 } else {
3191 // Disable auto memory retention
3192 cmu->SLEEP = (cmu->SLEEP & ~CMU_DEEPSLEEP_ROMRAM_EN) |
3193 CMU_DEEPSLEEP_EN | CMU_MANUAL_RAM_RETN | CMU_DEEPSLEEP_START;
3194 }
3195
3196 #ifndef __ARM_ARCH_ISA_ARM
3197 if (mode == HAL_CMU_LPU_SLEEP_MODE_CHIP) {
3198 SCB->SCR = SCB_SCR_SLEEPDEEP_Msk;
3199 } else {
3200 SCB->SCR = 0;
3201 }
3202 #endif
3203
3204 cpu_sleep(wakeup_cfg);
3205
3206 if (wakeup_cfg & CMU_LPU_AUTO_SWITCHPLL) {
3207 start = hal_sys_timer_get();
3208 timeout = HAL_CMU_26M_READY_TIMEOUT + HAL_CMU_PLL_LOCKED_TIMEOUT + HAL_CMU_LPU_EXTRA_TIMEOUT;
3209 while ((cmu->WAKEUP_CLK_CFG & CMU_LPU_STATUS_PLL) == 0 &&
3210 (hal_sys_timer_get() - start) < timeout);
3211 // Hardware will switch system to PLL divider and enable PLLs automatically
3212 } else {
3213 // Wait for 26M ready
3214 if (wakeup_cfg & CMU_LPU_AUTO_SWITCH26) {
3215 start = hal_sys_timer_get();
3216 timeout = HAL_CMU_26M_READY_TIMEOUT + HAL_CMU_LPU_EXTRA_TIMEOUT;
3217 while ((cmu->WAKEUP_CLK_CFG & CMU_LPU_STATUS_26M) == 0 &&
3218 (hal_sys_timer_get() - start) < timeout);
3219 // Hardware will switch system freq to 26M automatically
3220 } else {
3221 if (mode == HAL_CMU_LPU_SLEEP_MODE_CHIP) {
3222 timeout = HAL_CMU_26M_READY_TIMEOUT;
3223 hal_sys_timer_delay(timeout);
3224 }
3225 // Switch system freq to 26M
3226 cmu->SYS_CLK_ENABLE = CMU_SEL_MCU_SLOW_ENABLE;
3227 // Restore AON_CMU clock
3228 aoncmu->CODEC_DIV = saved_codec_div;
3229 }
3230 }
3231
3232 // System freq is 26M now and will be restored later
3233 // Restore PLLs
3234 if (saved_pll_cfg & AON_CMU_PU_PLLUSB_ENABLE) {
3235 aoncmu->PLL_ENABLE = AON_CMU_PU_PLLUSB_ENABLE;
3236 }
3237 if (saved_pll_cfg & AON_CMU_PU_PLLDDR_ENABLE) {
3238 aoncmu->PLL_ENABLE = AON_CMU_PU_PLLDDR_ENABLE;
3239 }
3240 if (saved_pll_cfg & AON_CMU_PU_PLLA7_ENABLE) {
3241 aoncmu->PLL_ENABLE = AON_CMU_PU_PLLA7_ENABLE;
3242 }
3243 if (saved_pll_cfg & AON_CMU_PU_PLLBB_DIV_MCU_ENABLE) {
3244 aoncmu->PLL_ENABLE = AON_CMU_PU_PLLBB_ENABLE | AON_CMU_PU_PLLBB_DIV_MCU_ENABLE;
3245 }
3246 if (saved_pll_cfg & AON_CMU_PU_PLLBB_DIV_PS_ENABLE) {
3247 aoncmu->PLL_ENABLE = AON_CMU_PU_PLLBB_ENABLE | AON_CMU_PU_PLLBB_DIV_PS_ENABLE;
3248 }
3249 if (saved_pll_cfg & AON_CMU_PU_OSCX4_ENABLE) {
3250 aoncmu->PLL_ENABLE = AON_CMU_PU_OSCX4_ENABLE;
3251 }
3252 #ifndef ROM_BUILD
3253 hal_sys_timer_delay_us(20);
3254 // Clear pll div reset if pll is enabled
3255 if (saved_pll_cfg & AON_CMU_PU_PLLUSB_ENABLE) {
3256 pmu_pll_div_reset_clear(HAL_CMU_PLL_USB);
3257 }
3258 if (saved_pll_cfg & AON_CMU_PU_PLLDDR_ENABLE) {
3259 pmu_pll_div_reset_clear(HAL_CMU_PLL_DDR);
3260 }
3261 if (saved_pll_cfg & AON_CMU_PU_PLLA7_ENABLE) {
3262 pmu_pll_div_reset_clear(HAL_CMU_PLL_DSP);
3263 }
3264 if (saved_pll_cfg & AON_CMU_PU_PLLBB_DIV_MCU_ENABLE) {
3265 pmu_pll_div_reset_clear(HAL_CMU_PLL_BB);
3266 }
3267 if (saved_pll_cfg & AON_CMU_PU_PLLBB_DIV_PS_ENABLE) {
3268 pmu_pll_div_reset_clear(HAL_CMU_PLL_BB_PSRAM);
3269 }
3270 hal_sys_timer_delay_us(10);
3271 #endif
3272 if (saved_pll_cfg & AON_CMU_PU_PLLUSB_ENABLE) {
3273 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_PLLUSB_ENABLE;
3274 }
3275 if (saved_pll_cfg & AON_CMU_PU_PLLDDR_ENABLE) {
3276 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_PLLDDR_ENABLE;
3277 }
3278 if (saved_pll_cfg & AON_CMU_PU_PLLA7_ENABLE) {
3279 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_PLLA7_ENABLE;
3280 }
3281 if (saved_pll_cfg & AON_CMU_PU_PLLBB_DIV_MCU_ENABLE) {
3282 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_PLLBB_ENABLE;
3283 }
3284 if (saved_pll_cfg & AON_CMU_PU_PLLBB_DIV_PS_ENABLE) {
3285 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_PLLBB_PS_ENABLE;
3286 }
3287 if (saved_pll_cfg & AON_CMU_PU_OSCX4_ENABLE) {
3288 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_OSCX4_ENABLE;
3289 }
3290 // Restore system freq
3291 cmu->SYS_CLK_ENABLE = saved_clk_cfg & CMU_RSTN_DIV_MCU_ENABLE;
3292 cmu->SYS_CLK_ENABLE = saved_clk_cfg;
3293 // The original system freq are at least 26M
3294 //cmu->SYS_CLK_DISABLE = ~saved_clk_cfg;
3295
3296 // Switch VAD clock to MCU and enable codec HCLK if it is on before entering sleep
3297 aoncmu->CODEC_DIV &= ~AON_CMU_SEL_CODECHCLK_MCU;
3298 if (mode == HAL_CMU_LPU_SLEEP_MODE_CHIP) {
3299 aoncmu->TOP_CLK_ENABLE = saved_top_clk & AON_CMU_EN_CLK_CODECHCLK_ENABLE;
3300 } else {
3301 // Restore the original top clock settings
3302 aoncmu->TOP_CLK_DISABLE = ~saved_top_clk;
3303 }
3304
3305 if (saved_oclk & (SYS_OCLK_PSRAM1G | SYS_OCLK_PSRAM200 | SYS_OCLK_FLASH)) {
3306 // Enable memory/flash clock
3307 cmu->HCLK_ENABLE = saved_hclk;
3308 cmu->OCLK_ENABLE = saved_oclk;
3309 // Wait until memory/flash clock ready
3310 hal_sys_timer_delay_us(2);
3311 }
3312
3313 return 0;
3314 }
3315
hal_cmu_get_bootmode_addr(void)3316 volatile uint32_t *hal_cmu_get_bootmode_addr(void)
3317 {
3318 return &aoncmu->BOOTMODE;
3319 }
3320
hal_cmu_bt_clock_enable(void)3321 void hal_cmu_bt_clock_enable(void)
3322 {
3323 aoncmu->MOD_CLK_ENABLE = AON_CMU_MANUAL_OCLK_ENABLE(AON_OCLK_BTAON);
3324 aocmu_reg_update_wait();
3325 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_BT_ENABLE;
3326 aocmu_reg_update_wait();
3327 }
3328
hal_cmu_bt_clock_disable(void)3329 void hal_cmu_bt_clock_disable(void)
3330 {
3331 aoncmu->MOD_CLK_DISABLE = AON_CMU_MANUAL_OCLK_DISABLE(AON_OCLK_BTAON);
3332 aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_BT_DISABLE;
3333 }
3334
hal_cmu_bt_reset_set(void)3335 void hal_cmu_bt_reset_set(void)
3336 {
3337 aoncmu->RESET_SET = AON_CMU_ORESETN_SET(AON_ORST_BTAON);
3338 aoncmu->SOFT_RSTN_SET = AON_CMU_SOFT_RSTN_BT_SET | AON_CMU_SOFT_RSTN_BTCPU_SET;
3339 }
3340
hal_cmu_bt_reset_clear(void)3341 void hal_cmu_bt_reset_clear(void)
3342 {
3343 aoncmu->RESET_CLR = AON_CMU_ORESETN_CLR(AON_ORST_BTAON);
3344 aocmu_reg_update_wait();
3345 aoncmu->SOFT_RSTN_CLR = AON_CMU_SOFT_RSTN_BT_CLR | AON_CMU_SOFT_RSTN_BTCPU_CLR;
3346 aocmu_reg_update_wait();
3347 }
3348
hal_cmu_bt_module_init(void)3349 void hal_cmu_bt_module_init(void)
3350 {
3351 //btcmu->CLK_MODE = 0;
3352 }
3353
hal_cmu_wifi_clock_enable(void)3354 void hal_cmu_wifi_clock_enable(void)
3355 {
3356 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_WF_ENABLE;
3357 aocmu_reg_update_wait();
3358 }
3359
hal_cmu_wifi_clock_disable(void)3360 void hal_cmu_wifi_clock_disable(void)
3361 {
3362 aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_WF_DISABLE;
3363 }
3364
hal_cmu_wifi_reset_set(void)3365 void hal_cmu_wifi_reset_set(void)
3366 {
3367 aoncmu->SOFT_RSTN_SET = AON_CMU_SOFT_RSTN_WF_SET | AON_CMU_SOFT_RSTN_WFCPU_SET;
3368 }
3369
hal_cmu_wifi_reset_clear(void)3370 void hal_cmu_wifi_reset_clear(void)
3371 {
3372 aoncmu->SOFT_RSTN_CLR = AON_CMU_SOFT_RSTN_WF_CLR | AON_CMU_SOFT_RSTN_WFCPU_CLR;
3373 aocmu_reg_update_wait();
3374 }
3375
hal_cmu_wlan_set_sleep_allow(uint32_t auto_mode)3376 void BOOT_TEXT_FLASH_LOC hal_cmu_wlan_set_sleep_allow(uint32_t auto_mode)
3377 {
3378 if (auto_mode) { //controlled by wifi sleep signal
3379 aoncmu->RESERVED_0E8 = aoncmu->RESERVED_0E8 & (~((1<<4)|(1<<6)));
3380 } else { //force allow cmu sleep
3381 aoncmu->RESERVED_0E8 = (aoncmu->RESERVED_0E8 & (~((1<<5)|(1<<7)))) | ((1<<4)|(1<<6));
3382 }
3383 }
3384
GPV_init(void)3385 static void GPV_init(void)
3386 {
3387 #ifdef GPV_MAIN_BASE
3388 volatile uint32_t *gpv_ctrl_psram = (volatile uint32_t *)(GPV_MAIN_BASE+0x6000);
3389 volatile uint32_t *gpv_ctrl_x2h = (volatile uint32_t *)(GPV_MAIN_BASE+0x7000);
3390 gpv_ctrl_psram[17] |= 0x2; //0x50306044
3391 gpv_ctrl_x2h[17] |= 0x2; //0x50307044
3392 #endif
3393 }
3394
hal_cmu_dsp_clock_enable(void)3395 void hal_cmu_dsp_clock_enable(void)
3396 {
3397 enum HAL_CMU_PLL_T dsp;
3398 #ifdef DSP_ENABLE
3399 hal_psc_a7_enable();
3400 #endif
3401 // DSP AXI clock divider defaults to 4 (div = reg_val + 2)
3402 cmu->DSP_DIV = SET_BITFIELD(cmu->DSP_DIV, CMU_CFG_DIV_XCLK, 2);
3403 cmu->XCLK_ENABLE = SYS_XCLK_DMA | SYS_XCLK_NIC | SYS_XCLK_IMEMLO | SYS_XCLK_IMEMHI | SYS_XCLK_PER |
3404 SYS_XCLK_PDBG | SYS_XCLK_CORE0 | SYS_XCLK_CORE1 | SYS_XCLK_CORE2 | SYS_XCLK_CORE3 | SYS_XCLK_DBG | SYS_XCLK_SCU |
3405 SYS_XCLK_GPV_MAIN;
3406 cmu->APCLK_ENABLE = SYS_APCLK_BOOTREG | SYS_APCLK_WDT| SYS_APCLK_TIMER0 | SYS_APCLK_TIMER1 | SYS_APCLK_TQ | SYS_APCLK_DAP;
3407 cmu->HCLK_ENABLE = SYS_HCLK_AX2H_A7;
3408
3409 cmu->DSP_CFG0 |= CMU_CA7_DBGEN_MASK | CMU_CA7_SPIDEN_MASK | CMU_CA7_NIDEN_MASK | CMU_CA7_SPNIDEN_MASK;
3410
3411 cmu->PERIPH_CLK |= CMU_A7_ALLIRQ_MASK;
3412 cmu->DSP_CFG0 |= CMU_A7TOM33_IRQS_MASK(8);
3413
3414 #ifdef DSP_USE_BBPLL
3415 dsp = HAL_CMU_PLL_BB;
3416 #elif defined(DSP_USE_USBPLL)
3417 dsp = HAL_CMU_PLL_USB;
3418 #else
3419 dsp = HAL_CMU_PLL_DSP;
3420 #endif
3421 hal_cmu_dsp_select_pll(dsp);
3422 hal_cmu_pll_enable(dsp, HAL_CMU_PLL_USER_DSP);
3423
3424 hal_cmu_dsp_set_freq(HAL_CMU_FREQ_780M);
3425
3426 #ifdef DSP_ENABLE
3427 hal_cmu_clock_enable(HAL_CMU_MOD_O_A7);
3428 hal_cmu_clock_enable(HAL_CMU_MOD_O_WDT_AP);
3429 hal_cmu_clock_enable(HAL_CMU_MOD_O_TIMER0_AP);
3430 hal_cmu_clock_enable(HAL_CMU_MOD_O_TIMER1_AP);
3431 #ifndef ARM_CMNS
3432 ///TODO: add cmse interface if trustzone is enabled
3433 GPV_init();
3434 #endif
3435 #endif
3436 }
3437
hal_cmu_dsp_clock_disable(void)3438 void hal_cmu_dsp_clock_disable(void)
3439 {
3440 enum HAL_CMU_PLL_T dsp;
3441
3442 hal_cmu_clock_disable(HAL_CMU_MOD_O_A7);
3443
3444 #ifdef DSP_USE_BBPLL
3445 dsp = HAL_CMU_PLL_BB;
3446 #elif defined(DSP_USE_USBPLL)
3447 dsp = HAL_CMU_PLL_USB;
3448 #else
3449 dsp = HAL_CMU_PLL_DSP;
3450 #endif
3451 hal_cmu_pll_disable(dsp, HAL_CMU_PLL_USER_DSP);
3452
3453 cmu->XCLK_DISABLE = SYS_XCLK_DMA | SYS_XCLK_NIC | SYS_XCLK_IMEMLO | SYS_XCLK_IMEMHI | SYS_XCLK_PER |
3454 SYS_XCLK_PDBG | SYS_XCLK_CORE0 | SYS_XCLK_CORE1 | SYS_XCLK_CORE2 | SYS_XCLK_CORE3 | SYS_XCLK_DBG | SYS_XCLK_SCU |
3455 SYS_XCLK_GPV_MAIN;
3456 cmu->APCLK_DISABLE = SYS_APCLK_BOOTREG | SYS_APCLK_WDT| SYS_APCLK_TIMER0 | SYS_APCLK_TIMER1 | SYS_APCLK_TQ | SYS_APCLK_DAP;
3457 cmu->OCLK_DISABLE = SYS_OCLK_WDT_AP | SYS_OCLK_TIMER0_AP | SYS_OCLK_TIMER1_AP;
3458 cmu->HCLK_DISABLE = SYS_HCLK_AX2H_A7;
3459
3460 hal_psc_a7_disable();
3461 }
3462
hal_cmu_dsp_reset_set(void)3463 void hal_cmu_dsp_reset_set(void)
3464 {
3465 aoncmu->SOFT_RSTN_SET = AON_CMU_SOFT_RSTN_A7_SET | AON_CMU_SOFT_RSTN_A7CPU_SET;
3466 cmu->ORESET_SET = SYS_ORST_WDT_AP | SYS_ORST_TIMER0_AP | SYS_ORST_TIMER1_AP;
3467 cmu->XRESET_SET = SYS_XRST_DMA | SYS_XRST_NIC | SYS_XRST_IMEMLO | SYS_XRST_IMEMHI | SYS_XRST_PER |
3468 SYS_XRST_PDBG | SYS_XRST_CORE0 | SYS_XRST_CORE1 | SYS_XRST_CORE2 | SYS_XRST_CORE3 | SYS_XRST_DBG | SYS_XRST_SCU |
3469 SYS_XRST_GPV_MAIN;
3470 cmu->APRESET_SET = SYS_APRST_BOOTREG | SYS_APRST_WDT | SYS_APRST_TIMER0 | SYS_APRST_TIMER1 | SYS_APRST_TQ | SYS_APRST_DAP;
3471 cmu->HRESET_SET = SYS_HRST_AX2H_A7;
3472 }
3473
hal_cmu_dsp_reset_clear(void)3474 void hal_cmu_dsp_reset_clear(void)
3475 {
3476 cmu->APRESET_CLR = SYS_APCLK_BOOTREG | SYS_APCLK_WDT| SYS_APCLK_TIMER0 | SYS_APCLK_TIMER1 | SYS_APCLK_TQ | SYS_APCLK_DAP;
3477 cmu->XRESET_CLR = SYS_XRST_DMA | SYS_XRST_NIC | SYS_XRST_IMEMLO | SYS_XRST_IMEMHI | SYS_XRST_PER |
3478 SYS_XRST_PDBG | SYS_XRST_CORE0 | SYS_XRST_CORE1 | SYS_XRST_CORE2 | SYS_XRST_CORE3 | SYS_XRST_DBG | SYS_XRST_SCU |
3479 SYS_XRST_GPV_MAIN;
3480 cmu->ORESET_CLR = SYS_ORST_WDT_AP | SYS_ORST_TIMER0_AP | SYS_ORST_TIMER1_AP;
3481 cmu->HRESET_CLR = SYS_HRST_AX2H_A7;
3482 aoncmu->SOFT_RSTN_CLR = AON_CMU_SOFT_RSTN_A7_CLR;
3483 aocmu_reg_update_wait();
3484 }
3485
hal_cmu_dsp_reset_hold(void)3486 void hal_cmu_dsp_reset_hold(void)
3487 {
3488 aoncmu->SOFT_RSTN_SET = AON_CMU_SOFT_RSTN_A7_SET | AON_CMU_SOFT_RSTN_A7CPU_SET;
3489 cmu->HRESET_SET = SYS_HRST_AX2H_A7 | SYS_HRST_PSRAM1G;
3490 cmu->ORESET_SET = SYS_ORST_PSRAM1G;
3491 cmu->ORESET_SET = SYS_ORST_WDT_AP | SYS_ORST_TIMER1_AP;
3492 }
3493
hal_cmu_dsp_reset_release(void)3494 void hal_cmu_dsp_reset_release(void)
3495 {
3496 cmu->ORESET_CLR = SYS_ORST_WDT_AP | SYS_ORST_TIMER1_AP;
3497 cmu->ORESET_CLR = SYS_ORST_PSRAM1G;
3498 cmu->HRESET_CLR = SYS_HRST_AX2H_A7 | SYS_HRST_PSRAM1G;
3499 aoncmu->SOFT_RSTN_CLR = AON_CMU_SOFT_RSTN_A7_CLR;
3500 aocmu_reg_update_wait();
3501 }
3502
hal_cmu_dsp_init_boot_reg(uint32_t entry)3503 void hal_cmu_dsp_init_boot_reg(uint32_t entry)
3504 {
3505 int i;
3506 volatile uint32_t *boot = (volatile uint32_t *)DSP_BOOT_REG;
3507
3508 // Unlock
3509 boot[32] = 0xCAFE0001;
3510 __DMB();
3511
3512 for (i = 0; i < 8; i++) {
3513 // ldr pc, [pc, #24]
3514 boot[0 + i] = 0xE59FF018;
3515 // Init_Handler
3516 boot[8 + i] = 0x00000040;
3517 }
3518 // b 40
3519 boot[16] = 0xEAFFFFFE;
3520
3521 // Update reset handler
3522 boot[8] = entry;
3523
3524 // Lock
3525 __DMB();
3526 boot[32] = 0xCAFE0000;
3527 __DMB();
3528 }
3529
hal_cmu_dsp_start_cpu(void)3530 void hal_cmu_dsp_start_cpu(void)
3531 {
3532 hal_cmu_dsp_set_freq(HAL_CMU_FREQ_156M);//div 5
3533 aoncmu->SOFT_RSTN_CLR = AON_CMU_SOFT_RSTN_A7CPU_CLR;
3534 }
3535
hal_cmu_dsp_stop_cpu(void)3536 void hal_cmu_dsp_stop_cpu(void)
3537 {
3538 uint32_t lock;
3539 lock = int_lock();
3540 #ifdef PSRAMUHS_ENABLE
3541 hal_psramuhs_hold();
3542 #endif
3543 hal_cmu_dsp_reset_hold();
3544 //hal_cmu_dsp_clock_disable();
3545
3546 #ifdef PSRAMUHS_ENABLE
3547 //hal_cmu_dsp_clock_enable();
3548 hal_cmu_dsp_reset_release();
3549 hal_psramuhs_release();
3550 #endif
3551 int_unlock(lock);
3552 }
3553
hal_cmu_get_aon_chip_id(void)3554 uint32_t hal_cmu_get_aon_chip_id(void)
3555 {
3556 return aoncmu->CHIP_ID;
3557 }
3558
hal_cmu_get_aon_revision_id(void)3559 uint32_t hal_cmu_get_aon_revision_id(void)
3560 {
3561 return GET_BITFIELD(aoncmu->CHIP_ID, AON_CMU_REVISION_ID);
3562 }
3563
hal_cmu_cp_enable(uint32_t sp,uint32_t entry)3564 void hal_cmu_cp_enable(uint32_t sp, uint32_t entry)
3565 {
3566 struct CP_STARTUP_CFG_T * cp_cfg;
3567 uint32_t cfg_addr;
3568
3569 // Use (sp - 128) as the default vector. The Address must aligned to 128-byte boundary.
3570 cfg_addr = (sp - (1 << 7)) & ~((1 << 7) - 1);
3571
3572 cmu->CP_VTOR = cfg_addr;
3573 cp_cfg = (struct CP_STARTUP_CFG_T *)cfg_addr;
3574
3575 cp_cfg->stack = sp;
3576 cp_cfg->reset_hdlr = (uint32_t)system_cp_reset_handler;
3577 cp_entry = entry;
3578
3579 hal_cmu_clock_enable(HAL_CMU_MOD_H_CP);
3580 hal_cmu_reset_clear(HAL_CMU_MOD_H_CP);
3581 }
3582
hal_cmu_cp_disable(void)3583 void hal_cmu_cp_disable(void)
3584 {
3585 hal_cmu_reset_set(HAL_CMU_MOD_H_CP);
3586 hal_cmu_clock_disable(HAL_CMU_MOD_H_CP);
3587 }
3588
hal_cmu_cp_get_entry_addr(void)3589 uint32_t hal_cmu_cp_get_entry_addr(void)
3590 {
3591 return cp_entry;
3592 }
3593
hal_cmu_cp_boot(uint32_t entry)3594 void hal_cmu_cp_boot(uint32_t entry)
3595 {
3596 cmu->CP_VTOR = entry;
3597
3598 hal_cmu_clock_enable(HAL_CMU_MOD_H_CACHE1);
3599 hal_cmu_reset_clear(HAL_CMU_MOD_H_CACHE1);
3600
3601 hal_cmu_clock_enable(HAL_CMU_MOD_H_CP);
3602 hal_cmu_reset_clear(HAL_CMU_MOD_H_CP);
3603 }
3604
hal_cmu_jtag_sel(enum HAL_CMU_JTAG_SEL_T sel)3605 void hal_cmu_jtag_sel(enum HAL_CMU_JTAG_SEL_T sel)
3606 {
3607 uint32_t lock;
3608
3609 lock = int_lock();
3610 cmu->PERIPH_CLK &= ~CMU_JTAG_SEL_MASK;
3611 switch (sel) {
3612 case HAL_CMU_JTAG_SEL_CP:
3613 cmu->PERIPH_CLK |= CMU_JTAG_SEL_CP;
3614 break;
3615 case HAL_CMU_JTAG_SEL_A7:
3616 cmu->PERIPH_CLK |= CMU_JTAG_SEL_A7;
3617 break;
3618 default:
3619 break;
3620 }
3621 int_unlock(lock);
3622 }
3623
hal_cmu_dsp_setup(void)3624 void hal_cmu_dsp_setup(void)
3625 {
3626 hal_sys_timer_open();
3627
3628 hal_sysfreq_req(HAL_SYSFREQ_USER_INIT, HAL_CMU_FREQ_390M);
3629
3630 }
3631
hal_cmu_flash0_dual_die()3632 void hal_cmu_flash0_dual_die()
3633 {
3634 cmu->MCU_TIMER &= ~CMU_FLS1_IO_SEL;
3635 }
3636
hal_cmu_flash1_enable()3637 void hal_cmu_flash1_enable()
3638 {
3639 //aoncmu->FLASH_IOCFG |= AON_CMU_PU_FLASH1_IO;
3640 aoncmu->FLASH_IOCFG = SET_BITFIELD(aoncmu->FLASH_IOCFG, AON_CMU_FLASH1_IODRV, 0x7) | AON_CMU_PU_FLASH1_IO;
3641 }
3642
hal_cmu_set_flash0_x8_mode(uint32_t en)3643 void hal_cmu_set_flash0_x8_mode(uint32_t en)
3644 {
3645 if (en)
3646 cmu->MCU_TIMER |= CMU_FLS0_X8_SEL;
3647 else
3648 cmu->MCU_TIMER &= ~CMU_FLS0_X8_SEL;
3649 }
3650
hal_cmu_set_flash0_size(enum HAL_FLASH0_SIZE_CFG cfg)3651 void hal_cmu_set_flash0_size(enum HAL_FLASH0_SIZE_CFG cfg)
3652 {
3653 *(volatile uint32_t *)(ICACHE_CTRL_BASE + 0x44) = cfg;
3654 }
3655
hal_cmu_get_osc_ready_cycle_cnt(void)3656 uint32_t hal_cmu_get_osc_ready_cycle_cnt(void)
3657 {
3658 uint32_t cnt=10;
3659
3660
3661
3662 return cnt;
3663 }
3664
hal_cmu_get_osc_switch_overhead(void)3665 uint32_t hal_cmu_get_osc_switch_overhead(void)
3666 {
3667 return 6;
3668 }
3669
hal_cmu_bt_sys_set_freq(enum HAL_CMU_FREQ_T freq)3670 void hal_cmu_bt_sys_set_freq(enum HAL_CMU_FREQ_T freq)
3671 {
3672
3673 }
3674
hal_cmu_bt_sys_clock_force_on(void)3675 void hal_cmu_bt_sys_clock_force_on(void)
3676 {
3677 uint32_t lock;
3678
3679 lock = int_lock();
3680 hal_psc_dslp_force_on_bt_enable();
3681 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_BT_CLK_SYS_ENABLE;
3682 int_unlock(lock);
3683 aocmu_reg_update_wait();
3684 }
3685
hal_cmu_bt_sys_clock_auto(void)3686 void hal_cmu_bt_sys_clock_auto(void)
3687 {
3688 uint32_t lock;
3689
3690 lock = int_lock();
3691 aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_BT_CLK_SYS_DISABLE;
3692 hal_psc_dslp_force_on_bt_disable();
3693 int_unlock(lock);
3694 }
3695
3696 #ifdef REUSE_WIFI_CALI_RESULT
3697 extern void save_wifi_cali_result();
3698 #endif
3699
hal_cmu_shutdown_hook(void)3700 void hal_cmu_shutdown_hook(void)
3701 {
3702 int_lock();
3703 hal_cmu_codec_clock_disable();
3704 hal_cmu_codec_rs_disable();
3705
3706 hal_cmu_dsp_reset_set();
3707 hal_cmu_dsp_clock_disable();
3708
3709 #ifdef REUSE_WIFI_CALI_RESULT
3710 save_wifi_cali_result();
3711 #endif
3712
3713 hal_cmu_wifi_reset_set();
3714 hal_cmu_wifi_clock_disable();
3715 hal_cmu_cp_disable();
3716 hal_cmu_bt_reset_set();
3717 hal_cmu_bt_clock_disable();
3718
3719 // hal_norflash_deinit();
3720
3721 hal_cmu_mem_set_freq(HAL_CMU_FREQ_26M);
3722 hal_cmu_sys_set_freq(HAL_CMU_FREQ_26M);
3723
3724 // psramuhsphy_sleep();
3725 // hal_psram_phy_sleep();
3726 // hal_cmu_pll_disable(HAL_CMU_PLL_BB, HAL_CMU_PLL_USER_ALL);
3727 // hal_cmu_pll_disable(HAL_CMU_PLL_BB_PSRAM, HAL_CMU_PLL_USER_ALL);
3728 // hal_cmu_pll_disable(HAL_CMU_PLL_DDR, HAL_CMU_PLL_USER_ALL);
3729 // hal_cmu_pll_disable(HAL_CMU_PLL_DSP, HAL_CMU_PLL_USER_ALL);
3730 // hal_cmu_pll_disable(HAL_CMU_PLL_USB, HAL_CMU_PLL_USER_ALL);
3731 }
3732
hal_cmu_sys_reboot(void)3733 void hal_cmu_sys_reboot(void)
3734 {
3735 #if defined(FLASH_SUSPEND) && defined(FLASH_API_GUARD_THREAD)
3736 norflash_api_flush_all();
3737 #endif
3738 hal_cmu_shutdown_hook();
3739 hal_cmu_reset_set(HAL_CMU_MOD_GLOBAL);
3740 }
3741