1 /*
2 * Copyright (C) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
17 */
18
19 #include "hdmi_hal_scdc.h"
20 #include "drv_hdmi_intf.h"
21 #include "hdmi_osal.h"
22 #include "hdmi_product_define.h"
23 #include "hdmi_hal_phy.h"
24 #include "hdmi_hal_ddc.h"
25 #include "hdmi_hal_machine.h"
26 #include "hdmi_hal_intf.h"
27 #include "hdmi_reg_tx.h"
28
29 #define SCDC_HDMI20_VERSION 1
30 #define SCDC_UPDATE_TIME_INTERVAL 150
31 #define READ_SRC_VERSION_COUNT 2
32
33 typedef struct {
34 hi_bool src_scramble;
35 hi_bool sink_scramble;
36 hi_bool tmds_clk_ratio40x;
37 } scdc_scramble;
38
39 static scdc_infomation g_scdc_info[HDMI_DEVICE_ID_BUTT] = {{{0}, {0}}};
40
scdc_info_ptr_get(hdmi_device_id hdmi_id)41 static scdc_infomation *scdc_info_ptr_get(hdmi_device_id hdmi_id)
42 {
43 if (hdmi_id < HDMI_DEVICE_ID_BUTT) {
44 return &g_scdc_info[hdmi_id];
45 }
46 return HI_NULL;
47 }
48
scdc_scramble_set(hdmi_device_id hdmi_id,const scdc_scramble * scramble)49 static hi_s32 scdc_scramble_set(hdmi_device_id hdmi_id, const scdc_scramble *scramble)
50 {
51 hi_s32 ret;
52 scdc_tmds_config ddc_config_byte = {0};
53 ddc_cfg ddc_src_cfg = {0};
54
55 hdmi_if_null_warn_return(scramble, HI_FAILURE);
56
57 /* source scramble */
58 hdmi_reg_enc_scr_on_set(scramble->src_scramble);
59 /* sink scramble */
60 ddc_config_byte.u8.screambling_enable = scramble->sink_scramble ? HI_TRUE : HI_FALSE;
61 ddc_config_byte.u8.tmds_bit_clock_ratio = scramble->tmds_clk_ratio40x ? HI_TRUE : HI_FALSE;
62 hal_hdmi_ddc_default_cfg_get(hdmi_id, &ddc_src_cfg);
63 ddc_src_cfg.func_type = DDC_FUNC_TYPE_SCDC;
64 ddc_src_cfg.issue_mode = DDC_MODE_WRITE_MUTIL_ACK;
65 ddc_src_cfg.offset = SCDC_OFFSET_TMDS_CONFIG;
66 ddc_src_cfg.data = &ddc_config_byte.byte;
67 ddc_src_cfg.data_size = 1;
68 ret = hal_hdmi_ddc_issue(hdmi_id, &ddc_src_cfg);
69
70 return (ret == ddc_src_cfg.data_size) ? HI_SUCCESS : HI_FAILURE;
71 }
72
scdc_scramble_get(hdmi_device_id hdmi_id,scdc_scramble * scramble)73 static hi_s32 scdc_scramble_get(hdmi_device_id hdmi_id, scdc_scramble *scramble)
74 {
75 hi_s32 ret;
76 scdc_scrambler_status ddc_sramble_byte = {0};
77 scdc_tmds_config ddc_config_byte = {0};
78 ddc_cfg ddc_sink_cfg = {0};
79 scdc_infomation *scdc_info = HI_NULL;
80
81 scdc_info = scdc_info_ptr_get(hdmi_id);
82
83 hdmi_if_null_warn_return(scdc_info, HI_FAILURE);
84 /* source scrambled */
85 scramble->src_scramble = hdmi_reg_enc_scr_on_get() ? HI_TRUE : HI_FALSE;
86 hal_hdmi_ddc_default_cfg_get(hdmi_id, &ddc_sink_cfg);
87 /* sink scrambled status */
88 ddc_sink_cfg.func_type = DDC_FUNC_TYPE_SCDC;
89 ddc_sink_cfg.issue_mode = DDC_MODE_READ_MUTIL_NO_ACK;
90 ddc_sink_cfg.data_size = 1;
91 ddc_sink_cfg.offset = SCDC_OFFSET_SCRAMBLER_STATUS;
92 ddc_sramble_byte.byte = 0;
93 ddc_sink_cfg.data = &ddc_sramble_byte.byte;
94 ret = hal_hdmi_ddc_issue(hdmi_id, &ddc_sink_cfg);
95 scramble->sink_scramble = ddc_sramble_byte.u8.screambling_status ? HI_TRUE : HI_FALSE;
96 scdc_info->status.reg_update[scdc_info->status.reg_update_ptr].scramble_status.byte = ddc_sramble_byte.byte;
97
98 /* sink tmds bit clock ratio & scramble cfg */
99 ddc_sramble_byte.byte = 0;
100 ddc_sink_cfg.data = &ddc_config_byte.byte;
101 ddc_sink_cfg.offset = SCDC_OFFSET_TMDS_CONFIG;
102 ret = hal_hdmi_ddc_issue(hdmi_id, &ddc_sink_cfg);
103 scramble->tmds_clk_ratio40x = ddc_config_byte.u8.tmds_bit_clock_ratio ? HI_TRUE : HI_FALSE;
104 scdc_info->status.reg_static.tmds_config0.byte = ddc_config_byte.byte;
105
106 return (ret == ddc_sink_cfg.data_size) ? HI_SUCCESS : HI_FAILURE;
107 }
108
scdc_mach_poll_callback(hi_void * data)109 hi_void scdc_mach_poll_callback(hi_void *data)
110 {
111 scdc_infomation *scdc_info = (scdc_infomation *)data;
112 hdmi_if_null_warn_return_void(scdc_info);
113 hdmi_if_false_warn_return_void(scdc_info->status.init);
114
115 return;
116 }
117
hal_hdmi_scdc_init(hdmi_device_id hdmi_id)118 hi_s32 hal_hdmi_scdc_init(hdmi_device_id hdmi_id)
119 {
120 hi_s32 ret = HI_SUCCESS;
121 scdc_infomation *scdc_info = scdc_info_ptr_get(hdmi_id);
122 hdmi_mach_ctrl mach_ctrl = {0};
123
124 hdmi_if_null_warn_return(scdc_info, HI_FAILURE);
125
126 if (!scdc_info->status.init) {
127 mach_ctrl.data = scdc_info;
128 mach_ctrl.interval = SCDC_DEFAULT_POLL_INTERVAL;
129 mach_ctrl.callback = scdc_mach_poll_callback;
130 mach_ctrl.name = "SCDC";
131 (hi_void)memset_s(scdc_info, sizeof(scdc_infomation), 0, sizeof(scdc_infomation));
132 scdc_info->status.init = HI_TRUE;
133 scdc_info->status.hdmi_id = hdmi_id;
134 scdc_info->status.mach_interval = mach_ctrl.interval;
135 ret = hal_hdmi_mach_register(&mach_ctrl, &scdc_info->status.mach_id);
136 }
137
138 return ret;
139 }
140
hal_hdmi_scdc_deinit(hdmi_device_id hdmi_id)141 hi_s32 hal_hdmi_scdc_deinit(hdmi_device_id hdmi_id)
142 {
143 hi_s32 ret;
144 scdc_infomation *scdc_info = scdc_info_ptr_get(hdmi_id);
145
146 hdmi_if_null_warn_return(scdc_info, HI_FAILURE);
147 hdmi_if_false_warn_return(scdc_info->status.init, HI_FAILURE);
148 ret = hal_hdmi_mach_unregister(scdc_info->status.mach_id);
149 (hi_void)memset_s(scdc_info, sizeof(scdc_infomation), 0, sizeof(scdc_infomation));
150 scdc_info->status.init = HI_FALSE;
151 return ret;
152 }
153
hal_hdmi_scdc_reset(hdmi_device_id hdmi_id)154 hi_s32 hal_hdmi_scdc_reset(hdmi_device_id hdmi_id)
155 {
156 hi_s32 init_back;
157 hi_u32 mach_id_back;
158 scdc_scramble scramble = {0};
159 scdc_infomation *scdc_info = scdc_info_ptr_get(hdmi_id);
160
161 hdmi_if_null_warn_return(scdc_info, HI_FAILURE);
162 hdmi_if_false_warn_return(scdc_info->status.init, HI_FAILURE);
163
164 hal_hdmi_mach_stop(scdc_info->status.mach_id);
165 init_back = scdc_info->status.init;
166 mach_id_back = scdc_info->status.mach_id;
167 (hi_void)memset_s(scdc_info, sizeof(scdc_infomation), 0, sizeof(scdc_infomation));
168 scdc_info->status.init = init_back;
169 scdc_info->status.mach_id = mach_id_back;
170 scdc_info->status.hdmi_id = hdmi_id;
171 scramble.src_scramble = HI_FALSE;
172 scramble.sink_scramble = HI_FALSE;
173 scramble.tmds_clk_ratio40x = HI_FALSE;
174 scdc_scramble_set(hdmi_id, &scramble);
175
176 return HI_SUCCESS;
177 }
178
scdc_attr_param_check(scdc_attr * attr)179 static hi_void scdc_attr_param_check(scdc_attr *attr)
180 {
181 if ((attr->scramble_interval < SCDC_DEFAULT_SCRAMBLE_INTERVAL) ||
182 (attr->scramble_interval > SCDC_DEFAULT_SCRAMBLE_TIMEOUT)) {
183 attr->scramble_interval = SCDC_DEFAULT_SCRAMBLE_INTERVAL;
184 }
185 if (attr->scramble_timeout < SCDC_DEFAULT_SCRAMBLE_TIMEOUT) {
186 attr->scramble_timeout = SCDC_DEFAULT_SCRAMBLE_TIMEOUT;
187 }
188 if (attr->scramble_timeout > SCDC_MAX_SCRAMBLE_TIMEOUT) {
189 attr->scramble_timeout = SCDC_MAX_SCRAMBLE_TIMEOUT;
190 }
191 }
192
scdc_pre_scramble(hdmi_device_id hdmi_id,scdc_infomation * scdc_info)193 static hi_void scdc_pre_scramble(hdmi_device_id hdmi_id, scdc_infomation *scdc_info)
194 {
195 ddc_cfg cfg = {0};
196 hi_u8 ddc_byte = 0;
197
198 /* read sink version */
199 hal_hdmi_ddc_default_cfg_get(hdmi_id, &cfg);
200 cfg.data_size = 1;
201 cfg.data = &ddc_byte;
202 cfg.func_type = DDC_FUNC_TYPE_SCDC;
203 cfg.offset = SCDC_OFFSET_SINK_VERSION;
204 cfg.issue_mode = DDC_MODE_READ_MUTIL_NO_ACK;
205 hal_hdmi_ddc_issue(hdmi_id, &cfg);
206
207 scdc_info->status.reg_static.sink_version = ddc_byte;
208 if (ddc_byte != SCDC_HDMI20_VERSION) {
209 scdc_info->status.err_cnt.sink_un_read_cnt++;
210 hdmi_warn("scdc sink version is not %u\n", SCDC_HDMI20_VERSION);
211 }
212 /* RR_Enable disable */
213 scdc_info->attr.sink_read_quest = HI_FALSE;
214 scdc_info->status.reg_static.config0.byte = 0;
215 scdc_info->status.reg_static.config0.u8.rr_enable = HI_FALSE;
216 cfg.offset = SCDC_OFFSET_CONFIG_0;
217 cfg.issue_mode = DDC_MODE_WRITE_MUTIL_ACK;
218 cfg.data = &scdc_info->status.reg_static.config0.byte;
219 hal_hdmi_ddc_issue(hdmi_id, &cfg);
220
221 scdc_info->status.reg_static.rr_test_cfg.byte = 0;
222 cfg.offset = SCDC_OFFSET_TEST_CONFIG_0;
223 cfg.issue_mode = DDC_MODE_WRITE_MUTIL_ACK;
224 cfg.data = &scdc_info->status.reg_static.rr_test_cfg.byte;
225 hal_hdmi_ddc_issue(hdmi_id, &cfg);
226
227 return;
228 }
229
scdc_err_record(scdc_infomation * info,scdc_error_type err)230 static hi_void scdc_err_record(scdc_infomation *info, scdc_error_type err)
231 {
232 errno_t ret;
233 scdc_error_record *err_cord = HI_NULL;
234
235 if (info->status.err_record_ptr >= SCDC_MAX_ERROR_RECORD_NUM) {
236 hdmi_err("scdc err record failed, invalid index!\n");
237 return;
238 }
239 err_cord = &info->status.err_record[info->status.err_record_ptr];
240 err_cord->err_type = err;
241 err_cord->time_stamp = hal_hdmi_mach_ms_get();
242 ret = memcpy_s(&err_cord->err_attr, sizeof(err_cord->err_attr), &info->attr, sizeof(scdc_attr));
243 hdmi_unequal_eok_return_void(ret);
244 switch (err_cord->err_type) {
245 case SCDC_ERROR_SINK_UNREAD:
246 info->status.err_cnt.sink_un_read_cnt++;
247 break;
248 case SCDC_ERROR_SCRAMBLE:
249 info->status.err_cnt.sramble_fail_cnt++;
250 break;
251 case SCDC_ERROR_OE_DISABLE:
252 info->status.err_cnt.oe_disable_fail_cnt++;
253 break;
254 case SCDC_ERROR_OE_ENABLE:
255 info->status.err_cnt.oe_enable_fail_cnt++;
256 break;
257 default:
258 break;
259 }
260 info->status.err_record_ptr = (info->status.err_record_ptr + 1) % SCDC_MAX_ERROR_RECORD_NUM;
261
262 return;
263 }
264
scdc_oe_set(hi_bool oe_en,hi_u32 timeout,scdc_infomation * info)265 static hi_void scdc_oe_set(hi_bool oe_en, hi_u32 timeout, scdc_infomation *info)
266 {
267 hi_bool oe_enable = HI_FALSE;
268
269 #ifndef HDMI_FPGA_SUPPORT
270 hal_hdmi_phy_oe_set(oe_en);
271 osal_msleep(timeout);
272 hal_hdmi_phy_oe_get(&oe_enable);
273 #endif
274
275 if (oe_enable != oe_en) {
276 if (oe_en == HI_TRUE) {
277 if (info->status.err_cnt.oe_enable_fail_cnt < SCDC_ERROR_MAX_NUM_OE_ENABLE) {
278 scdc_err_record(info, SCDC_ERROR_OE_ENABLE);
279 }
280 } else {
281 if (info->status.err_cnt.oe_disable_fail_cnt < SCDC_ERROR_MAX_NUM_OE_DISABLE) {
282 scdc_err_record(info, SCDC_ERROR_OE_DISABLE);
283 }
284 }
285 hdmi_err("scdc oe oe_enable=%u fail, expected %u\n", oe_enable, oe_en);
286 }
287
288 return;
289 }
290
hal_hdmi_scdc_attr_set(hdmi_device_id hdmi_id,scdc_attr * attr)291 hi_s32 hal_hdmi_scdc_attr_set(hdmi_device_id hdmi_id, scdc_attr *attr)
292 {
293 hi_s32 ret;
294 hi_u32 scdc_timestart, scdc_time_cur, timeout;
295 scdc_scramble scramble = {0};
296 scdc_infomation *scdc_info = scdc_info_ptr_get(hdmi_id);
297
298 hdmi_if_null_warn_return(attr, HI_FAILURE);
299 hdmi_if_null_warn_return(scdc_info, HI_FAILURE);
300 hdmi_if_false_warn_return(scdc_info->status.init, HI_FAILURE);
301 scdc_attr_param_check(attr);
302
303 ret = memcpy_s(&scdc_info->attr, sizeof(scdc_info->attr), attr, sizeof(scdc_attr));
304 hdmi_unequal_eok_return(ret, HI_ERR_HDMI_INVALID_PARA);
305 scdc_pre_scramble(hdmi_id, scdc_info);
306 osal_msleep(SCDC_DEFAULT_SCRAMBLE_INTERVAL);
307 /* scrameble cfg */
308 timeout = scdc_info->attr.scramble_interval;
309 scdc_timestart = hdmi_osal_get_time_in_ms();
310
311 do {
312 /* oe disable */
313 scdc_oe_set(HI_FALSE, SCDC_OE_DISABLE_WAIT_TIME, scdc_info);
314 /* sink & source scramble config */
315 scramble.src_scramble = scdc_info->attr.src_scramble;
316 scramble.sink_scramble = scdc_info->attr.sink_scramble;
317 scramble.tmds_clk_ratio40x = scdc_info->attr.tmds_clk_ratio40x;
318 scdc_scramble_set(hdmi_id, &scramble);
319 /* oe enable */
320 #ifndef HDMI_FPGA_SUPPORT
321 osal_msleep(timeout);
322 #endif
323 scdc_oe_set(HI_TRUE, timeout, scdc_info);
324 /* poll status */
325 scdc_scramble_get(hdmi_id, &scramble);
326 osal_msleep(SCDC_GET_SCRAMBLE_STATUS_TIME);
327 /* compatibility try again */
328 ret = HI_SUCCESS;
329 if ((scramble.tmds_clk_ratio40x != scdc_info->attr.tmds_clk_ratio40x)) {
330 scdc_err_record(scdc_info, SCDC_ERROR_SCRAMBLE);
331 ret = HI_FAILURE;
332 }
333 timeout += scdc_info->attr.scramble_interval;
334 scdc_time_cur = hdmi_osal_get_time_in_ms();
335 } while ((ret != HI_SUCCESS) && (timeout <= scdc_info->attr.scramble_timeout) &&
336 ((scdc_time_cur - scdc_timestart) < SCDC_WHILE_SCRAMBLE_TIMEOUT));
337
338 hdmi_info("\ndelay_interval=%u, timeout=%u, src_scarmble=%u, sink_scramble=%u, tmds_clk_ratio40x=%u\n",
339 timeout, (scdc_time_cur - scdc_timestart), scramble.src_scramble,
340 scramble.sink_scramble, scramble.tmds_clk_ratio40x);
341
342 if (ret != HI_SUCCESS) {
343 hdmi_err("scdc scramble %s fail!\n", scdc_info->attr.sink_scramble ? "ON" : "OFF");
344 } else {
345 hdmi_info("scdc scramble %s success!\n", scdc_info->attr.sink_scramble ? "ON" : "OFF");
346 }
347
348 if ((ret != HI_SUCCESS) || scdc_info->attr.sink_scramble == HI_FALSE) {
349 ret += hal_hdmi_mach_stop(scdc_info->status.mach_id);
350 scdc_info->status.mach_enable = HI_FALSE;
351 }
352
353 return (ret != HI_SUCCESS) ? HI_FAILURE : HI_SUCCESS;
354 }
355
hal_hdmi_scdc_attr_get(hdmi_device_id hdmi_id,scdc_attr * attr)356 hi_s32 hal_hdmi_scdc_attr_get(hdmi_device_id hdmi_id, scdc_attr *attr)
357 {
358 errno_t ret;
359 scdc_scramble scramble = {0};
360 scdc_infomation *scdc_info = scdc_info_ptr_get(hdmi_id);
361
362 hdmi_if_null_warn_return(attr, HI_FAILURE);
363 hdmi_if_null_warn_return(scdc_info, HI_FAILURE);
364 hdmi_if_false_warn_return(scdc_info->status.init, HI_FAILURE);
365
366 scdc_scramble_get(hdmi_id, &scramble);
367 scdc_info->attr.sink_scramble = scramble.sink_scramble;
368 scdc_info->attr.src_scramble = scramble.src_scramble;
369 scdc_info->attr.tmds_clk_ratio40x = scramble.tmds_clk_ratio40x;
370 ret = memcpy_s(attr, sizeof(scdc_attr), &scdc_info->attr, sizeof(scdc_attr));
371 hdmi_unequal_eok_return(ret, HI_ERR_HDMI_INVALID_PARA);
372
373 return HI_SUCCESS;
374 }
375
376 /* real sw */
hal_hdmi_scdc_all_status_get(hdmi_device_id hdmi_id,scdc_status * status)377 hi_s32 hal_hdmi_scdc_all_status_get(hdmi_device_id hdmi_id, scdc_status *status)
378 {
379 errno_t ret;
380 scdc_infomation *scdc_info = scdc_info_ptr_get(hdmi_id);
381
382 hdmi_if_null_warn_return(status, HI_FAILURE);
383 hdmi_if_null_warn_return(scdc_info, HI_FAILURE);
384 hdmi_if_false_warn_return(scdc_info->status.init, HI_FAILURE);
385
386 ret = memcpy_s(status, sizeof(scdc_status), &scdc_info->status, sizeof(scdc_status));
387 hdmi_unequal_eok_return(ret, HI_ERR_HDMI_INVALID_PARA);
388
389 return HI_SUCCESS;
390 }
391
hal_hdmi_scdc_support_get(hdmi_device_id hdmi_id,hi_bool * support)392 hi_s32 hal_hdmi_scdc_support_get(hdmi_device_id hdmi_id, hi_bool *support)
393 {
394 hi_s32 ret;
395 hi_u8 ddc_byte = 0;
396 hi_u32 re_read_cnt = 0;
397 ddc_cfg tmp = {0};
398 scdc_infomation *scdc_info = scdc_info_ptr_get(hdmi_id);
399
400 hdmi_if_null_warn_return(support, HI_FAILURE);
401 hdmi_if_null_warn_return(scdc_info, HI_FAILURE);
402 hdmi_if_false_warn_return(scdc_info->status.init, HI_FAILURE);
403
404 hal_hdmi_ddc_default_cfg_get(hdmi_id, &tmp);
405 tmp.data_size = 1;
406 tmp.data = &ddc_byte;
407 tmp.func_type = DDC_FUNC_TYPE_SCDC;
408 tmp.offset = SCDC_OFFSET_SRC_VERSION;
409
410 do {
411 /* write source version */
412 tmp.issue_mode = DDC_MODE_WRITE_MUTIL_ACK;
413 ddc_byte = SCDC_HDMI20_VERSION;
414 ret = hal_hdmi_ddc_issue(hdmi_id, &tmp);
415
416 /* read source version */
417 tmp.issue_mode = DDC_MODE_READ_SINGLE_NO_ACK;
418 ddc_byte = 0;
419 ret = hal_hdmi_ddc_issue(hdmi_id, &tmp);
420 re_read_cnt++;
421 } while ((ret != tmp.data_size) && (re_read_cnt < READ_SRC_VERSION_COUNT));
422
423 if (ret == tmp.data_size) {
424 scdc_info->status.reg_static.src_version = SCDC_HDMI20_VERSION;
425 *support = HI_TRUE;
426 } else {
427 scdc_info->status.reg_static.src_version = 0;
428 *support = HI_FALSE;
429 }
430
431 return HI_SUCCESS;
432 }
433
hal_hdmi_scdc_scramble_force(hdmi_device_id hdmi_id,hi_bool enable)434 hi_s32 hal_hdmi_scdc_scramble_force(hdmi_device_id hdmi_id, hi_bool enable)
435 {
436 scdc_scramble scramble = {0};
437 scdc_infomation *scdc_info = scdc_info_ptr_get(hdmi_id);
438
439 hdmi_if_null_warn_return(scdc_info, HI_FAILURE);
440 hdmi_if_false_warn_return(scdc_info->status.init, HI_FAILURE);
441
442 if (enable) {
443 scramble.sink_scramble = HI_TRUE;
444 scramble.tmds_clk_ratio40x = HI_TRUE;
445 scramble.src_scramble = HI_TRUE;
446 scdc_info->attr.sink_scramble = HI_TRUE;
447 scdc_info->attr.src_scramble = HI_TRUE;
448 scdc_info->attr.tmds_clk_ratio40x = HI_TRUE;
449 } else {
450 scramble.sink_scramble = HI_FALSE;
451 scramble.tmds_clk_ratio40x = HI_FALSE;
452 scramble.src_scramble = HI_FALSE;
453 scdc_info->attr.sink_scramble = HI_FALSE;
454 scdc_info->attr.src_scramble = HI_FALSE;
455 scdc_info->attr.tmds_clk_ratio40x = HI_FALSE;
456 }
457
458 return scdc_scramble_set(hdmi_id, &scramble);
459 }
460
hal_hdmi_scdc_mach_enable(hdmi_device_id hdmi_id,hi_bool enable)461 hi_s32 hal_hdmi_scdc_mach_enable(hdmi_device_id hdmi_id, hi_bool enable)
462 {
463 hi_s32 ret;
464 scdc_infomation *scdc_info = scdc_info_ptr_get(hdmi_id);
465
466 hdmi_if_null_warn_return(scdc_info, HI_FAILURE);
467 hdmi_if_false_warn_return(scdc_info->status.init, HI_FAILURE);
468
469 if (enable) {
470 ret = hal_hdmi_mach_start(scdc_info->status.mach_id);
471 } else {
472 ret = hal_hdmi_mach_stop(scdc_info->status.mach_id);
473 }
474
475 return ret;
476 }
477
478