1 /*
2 * Copyright (c) 2021 Bestechnic (Shanghai) Co., Ltd. All rights reserved.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15 #include "plat_addr_map.h"
16 #include CHIP_SPECIFIC_HDR(reg_iomux)
17 #include "hal_iomux.h"
18 #include "hal_chipid.h"
19 #include "hal_gpio.h"
20 #include "hal_location.h"
21 #include "hal_timer.h"
22 #include "hal_trace.h"
23 #include "hal_uart.h"
24 #include "pmu.h"
25 #include "hal_chipid.h"
26
27 #define UART_HALF_DUPLEX
28
29 #ifdef I2S0_VOLTAGE_VMEM
30 #define I2S0_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_MEM
31 #else
32 #define I2S0_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_VIO
33 #endif
34
35 #ifdef I2S1_VOLTAGE_VMEM
36 #define I2S1_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_MEM
37 #else
38 #define I2S1_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_VIO
39 #endif
40
41 #ifdef SPDIF0_VOLTAGE_VMEM
42 #define SPDIF0_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_MEM
43 #else
44 #define SPDIF0_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_VIO
45 #endif
46
47 #ifdef DIGMIC_VOLTAGE_VMEM
48 #define DIGMIC_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_MEM
49 #else
50 #define DIGMIC_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_VIO
51 #endif
52
53 #ifdef SPI_VOLTAGE_VMEM
54 #define SPI_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_MEM
55 #else
56 #define SPI_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_VIO
57 #endif
58
59 #ifdef SPILCD_VOLTAGE_VMEM
60 #define SPILCD_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_MEM
61 #else
62 #define SPILCD_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_VIO
63 #endif
64
65 #ifdef I2C0_VOLTAGE_VMEM
66 #define I2C0_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_MEM
67 #else
68 #define I2C0_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_VIO
69 #endif
70
71 #ifdef I2C1_VOLTAGE_VMEM
72 #define I2C1_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_MEM
73 #else
74 #define I2C1_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_VIO
75 #endif
76
77 #ifdef I2C2_VOLTAGE_VMEM
78 #define I2C2_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_MEM
79 #else
80 #define I2C2_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_VIO
81 #endif
82
83 #ifdef CLKOUT_VOLTAGE_VMEM
84 #define CLKOUT_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_MEM
85 #else
86 #define CLKOUT_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_VIO
87 #endif
88
89 #ifdef PWM0_VOLTAGE_VMEM
90 #define PWM0_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_MEM
91 #else
92 #define PWM0_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_VIO
93 #endif
94
95 #ifdef PWM1_VOLTAGE_VMEM
96 #define PWM1_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_MEM
97 #else
98 #define PWM1_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_VIO
99 #endif
100
101 #ifdef PWM2_VOLTAGE_VMEM
102 #define PWM2_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_MEM
103 #else
104 #define PWM2_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_VIO
105 #endif
106
107 #ifdef PWM3_VOLTAGE_VMEM
108 #define PWM3_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_MEM
109 #else
110 #define PWM3_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_VIO
111 #endif
112
113 #ifdef PWM4_VOLTAGE_VMEM
114 #define PWM4_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_MEM
115 #else
116 #define PWM4_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_VIO
117 #endif
118
119 #ifdef PWM5_VOLTAGE_VMEM
120 #define PWM5_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_MEM
121 #else
122 #define PWM5_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_VIO
123 #endif
124
125 #ifdef PWM6_VOLTAGE_VMEM
126 #define PWM6_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_MEM
127 #else
128 #define PWM6_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_VIO
129 #endif
130
131 #ifdef PWM7_VOLTAGE_VMEM
132 #define PWM7_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_MEM
133 #else
134 #define PWM7_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_VIO
135 #endif
136
137 #ifdef IR_VOLTAGE_VMEM
138 #define IR_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_MEM
139 #else
140 #define IR_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_VIO
141 #endif
142
143 #ifdef SDMMC_VOLTAGE_VMEM
144 #define SDMMC_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_MEM
145 #else
146 #define SDMMC_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_VIO
147 #endif
148
149 #ifndef I2S0_I_IOMUX_INDEX
150 //00, 13, 37
151 #define I2S0_I_IOMUX_INDEX 00
152 #endif
153 #ifndef I2S0_I1_IOMUX_INDEX
154 //12, 36
155 //#define I2S0_I1_IOMUX_INDEX 12
156 #endif
157 #ifndef I2S0_I2_IOMUX_INDEX
158 //11, 35
159 //#define I2S0_I2_IOMUX_INDEX 11
160 #endif
161 #ifndef I2S0_I3_IOMUX_INDEX
162 //10, 35
163 //#define I2S0_I3_IOMUX_INDEX 10
164 #endif
165
166 #ifndef I2S0_O_IOMUX_INDEX
167 //01, 07
168 #define I2S0_O_IOMUX_INDEX 01
169 #endif
170 #ifndef I2S0_O1_IOMUX_INDEX
171 //06
172 #define I2S0_O1_IOMUX_INDEX 06
173 #endif
174 #ifndef I2S0_O2_IOMUX_INDEX
175 //05
176 #define I2S0_O2_IOMUX_INDEX 05
177 #endif
178 #ifndef I2S0_O3_IOMUX_INDEX
179 //04
180 #define I2S0_O3_IOMUX_INDEX 04
181 #endif
182
183 #ifndef I2S1_I_IOMUX_INDEX
184 //20, 33
185 #define I2S1_I_IOMUX_INDEX 20
186 #endif
187 #ifndef I2S1_I1_IOMUX_INDEX
188 //32
189 //#define I2S1_I1_IOMUX_INDEX 32
190 #endif
191 #ifndef I2S1_I2_IOMUX_INDEX
192 //31
193 //#define I2S1_I2_IOMUX_INDEX 31
194 #endif
195 #ifndef I2S1_I3_IOMUX_INDEX
196 //30
197 //#define I2S1_I3_IOMUX_INDEX 30
198 #endif
199
200 #ifndef I2S1_O_IOMUX_INDEX
201 //21, 27
202 #define I2S1_O_IOMUX_INDEX 21
203 #endif
204 #ifndef I2S1_O1_IOMUX_INDEX
205 //26
206 #define I2S1_O1_IOMUX_INDEX 26
207 #endif
208 #ifndef I2S1_O2_IOMUX_INDEX
209 //25
210 #define I2S1_O2_IOMUX_INDEX 25
211 #endif
212 #ifndef I2S1_O3_IOMUX_INDEX
213 //24
214 #define I2S1_O3_IOMUX_INDEX 24
215 #endif
216
217 #ifndef I2S_MCLK_IOMUX_INDEX
218 //04, 13, 15, 20, 22, 27, 34
219 #define I2S_MCLK_IOMUX_INDEX 04
220 #endif
221
222 #ifndef SPDIF0_I_IOMUX_INDEX
223 //02, 10, 20, 26, 37, 24
224 #define SPDIF0_I_IOMUX_INDEX 02
225 #endif
226
227 #ifndef SPDIF0_O_IOMUX_INDEX
228 //03, 11, 21, 27, 37, 07
229 #define SPDIF0_O_IOMUX_INDEX 03
230 #endif
231
232 #ifndef DIG_MIC_CK_IOMUX_PIN
233 //HAL_IOMUX_PIN_P0_0, HAL_IOMUX_PIN_P0_4, HAL_IOMUX_PIN_P3_3, HAL_IOMUX_PIN_P3_4
234 #define DIG_MIC_CK_IOMUX_PIN 0
235 #endif
236
237 #ifndef DIG_MIC_D0_IOMUX_PIN
238 //HAL_IOMUX_PIN_P0_1, HAL_IOMUX_PIN_P0_5, HAL_IOMUX_PIN_P3_0, HAL_IOMUX_PIN_P3_5
239 #define DIG_MIC_D0_IOMUX_PIN 1
240 #endif
241
242 #ifndef DIG_MIC_D1_IOMUX_PIN
243 //HAL_IOMUX_PIN_P0_2, HAL_IOMUX_PIN_P0_6, HAL_IOMUX_PIN_P3_1, HAL_IOMUX_PIN_P3_6
244 #define DIG_MIC_D1_IOMUX_PIN 2
245 #endif
246
247 #ifndef DIG_MIC_D2_IOMUX_PIN
248 //HAL_IOMUX_PIN_P0_3, HAL_IOMUX_PIN_P0_7, HAL_IOMUX_PIN_P3_2, HAL_IOMUX_PIN_P3_7
249 #define DIG_MIC_D2_IOMUX_PIN 3
250 #endif
251
252 #ifndef SPI_IOMUX_INDEX
253 //04(05,06,07), 24(25,26,27), 30(31,32,33)
254 #define SPI_IOMUX_INDEX 04
255 #endif
256
257 #ifndef SPI_IOMUX_CS1_INDEX
258 //10, 35
259 //#define SPI_IOMUX_CS1_INDEX 10
260 #endif
261 #ifndef SPI_IOMUX_CS2_INDEX
262 //11, 37
263 //#define SPI_IOMUX_CS2_INDEX 11
264 #endif
265 #ifndef SPI_IOMUX_CS3_INDEX
266 //12, 25
267 //#define SPI_IOMUX_CS3_INDEX 12
268 #endif
269
270 #ifndef SPI_IOMUX_DI1_INDEX
271 //13, 34
272 //#define SPI_IOMUX_DI1_INDEX 13
273 #endif
274 #ifndef SPI_IOMUX_DI2_INDEX
275 //14, 36
276 //#define SPI_IOMUX_DI2_INDEX 14
277 #endif
278 #ifndef SPI_IOMUX_DI3_INDEX
279 //15, 24
280 //#define SPI_IOMUX_DI3_INDEX 15
281 #endif
282
283 #ifndef SPILCD_IOMUX_INDEX
284 //00(01,02,03), 10(11,14,15), 20(21,22,23), 34(35,36,37)
285 #define SPILCD_IOMUX_INDEX 0
286 #endif
287
288 #ifndef SPILCD_IOMUX_CS1_INDEX
289 //05, 12, 27
290 //#define SPILCD_IOMUX_CS1_INDEX 05
291 #endif
292 #ifndef SPILCD_IOMUX_CS2_INDEX
293 //06, 31
294 //#define SPILCD_IOMUX_CS2_INDEX 06
295 #endif
296 #ifndef SPILCD_IOMUX_CS3_INDEX
297 //07, 32
298 //#define SPILCD_IOMUX_CS3_INDEX 07
299 #endif
300
301 #ifndef SPILCD_IOMUX_DI1_INDEX
302 //02, 26
303 //#define SPILCD_IOMUX_DI1_INDEX 02
304 #endif
305 #ifndef SPILCD_IOMUX_DI2_INDEX
306 //03, 30
307 //#define SPILCD_IOMUX_DI2_INDEX 03
308 #endif
309 #ifndef SPILCD_IOMUX_DI3_INDEX
310 //04, 33
311 //#define SPILCD_IOMUX_DI3_INDEX 04
312 #endif
313
314 #ifndef I2C0_IOMUX_INDEX
315 //00(01), 04(05), 16(17), 20(21), 26(27), 34(35)
316 #define I2C0_IOMUX_INDEX 4
317 #endif
318
319 #ifndef I2C1_IOMUX_INDEX
320 //02(03), 06(07), 14(15), 22(23), 30(31)
321 #define I2C1_IOMUX_INDEX 22
322 #endif
323
324 #ifndef I2C2_IOMUX_INDEX
325 //10(11), 12(13), 24(25), 32(33), 36(37)
326 #define I2C2_IOMUX_INDEX 10
327 #endif
328
329 #ifndef CLKOUT_IOMUX_INDEX
330 //04, 13, 15, 20, 21, 22, 23, 27, 34
331 #define CLKOUT_IOMUX_INDEX 20
332 #endif
333
334 #ifndef WIFI_UART_IOMUX_INDEX
335 //00(nothing), 20, 21, 30
336 #define WIFI_UART_IOMUX_INDEX 00
337 #endif
338
339 #ifndef UART1_IOMUX_INDEX
340 //02, 10, 20, 30, 32
341 #define UART1_IOMUX_INDEX 20
342 #endif
343
344 #ifndef UART2_IOMUX_INDEX
345 //00, 12, 14, 22, 36
346 #define UART2_IOMUX_INDEX 22
347 #endif
348
349 #ifndef UART3_IOMUX_INDEX
350 //04, 06, 24, 26, 34
351 #define UART3_IOMUX_INDEX 04
352 #endif
353
354 #ifndef PWM0_IOMUX_INDEX
355 //00, 10, 20, 30
356 #define PWM0_IOMUX_INDEX 00
357 #endif
358
359 #ifndef PWM1_IOMUX_INDEX
360 //01, 11, 21, 31
361 #define PWM1_IOMUX_INDEX 01
362 #endif
363
364 #ifndef PWM2_IOMUX_INDEX
365 //02, 12, 22, 32
366 #define PWM2_IOMUX_INDEX 02
367 #endif
368
369 #ifndef PWM3_IOMUX_INDEX
370 //03, 13, 23, 33
371 #define PWM3_IOMUX_INDEX 03
372 #endif
373
374 #ifndef PWM4_IOMUX_INDEX
375 //04, 14, 24, 34
376 #define PWM4_IOMUX_INDEX 04
377 #endif
378
379 #ifndef PWM5_IOMUX_INDEX
380 //05, 15, 25, 35
381 #define PWM5_IOMUX_INDEX 05
382 #endif
383
384 #ifndef PWM6_IOMUX_INDEX
385 //06, 16, 26, 36
386 #define PWM6_IOMUX_INDEX 06
387 #endif
388
389 #ifndef PWM7_IOMUX_INDEX
390 //07, 17, 27, 37
391 #define PWM7_IOMUX_INDEX 07
392 #endif
393
394 #ifndef IR_RX_IOMUX_INDEX
395 //00, 02, 06, 10, 12, 14, 22, 26, 31, 33, 36
396 #define IR_RX_IOMUX_INDEX 00
397 #endif
398
399 #ifndef IR_TX_IOMUX_INDEX
400 //01, 03, 07, 11, 13, 15, 21, 27, 32, 34, 37
401 #define IR_TX_IOMUX_INDEX 01
402 #endif
403
404 #define IOMUX_FUNC_VAL_GPIO 15
405
406 #define IOMUX_ALT_FUNC_NUM 11
407
408 // Other func values: 2 -> uart rtx/ctx, 12 -> btdm, 13 -> wf_fem, 14 -> tport, 15 -> gpio
409 static const uint8_t index_to_func_val[IOMUX_ALT_FUNC_NUM] = {
410 0, 1, 3, 4,
411 5, 6, 7, 8,
412 9, 10, 11
413 };
414
415 static const enum HAL_IOMUX_FUNCTION_T pin_func_map[HAL_IOMUX_PIN_NUM][IOMUX_ALT_FUNC_NUM] = {
416 // P0_0
417 { HAL_IOMUX_FUNC_PWM0, HAL_IOMUX_FUNC_UART2_RX, HAL_IOMUX_FUNC_I2C_M0_SCL, HAL_IOMUX_FUNC_SPILCD_DI0,
418 HAL_IOMUX_FUNC_SPILCD_DCN, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE,
419 HAL_IOMUX_FUNC_IR_RX, HAL_IOMUX_FUNC_PDM0_CK, HAL_IOMUX_FUNC_I2S0_SDI0, },
420 // P0_1
421 { HAL_IOMUX_FUNC_PWM1, HAL_IOMUX_FUNC_UART2_TX, HAL_IOMUX_FUNC_I2C_M0_SDA, HAL_IOMUX_FUNC_SPILCD_DIO,
422 HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE,
423 HAL_IOMUX_FUNC_IR_TX, HAL_IOMUX_FUNC_PDM0_D, HAL_IOMUX_FUNC_I2S0_SDO0, },
424 // P0_2
425 { HAL_IOMUX_FUNC_PWM2, HAL_IOMUX_FUNC_UART1_RX, HAL_IOMUX_FUNC_I2C_M1_SCL, HAL_IOMUX_FUNC_SPILCD_CS0,
426 HAL_IOMUX_FUNC_SPILCD_DI1, HAL_IOMUX_FUNC_SPDIF0_DI, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_DISPLAY_BL_EN,
427 HAL_IOMUX_FUNC_IR_RX, HAL_IOMUX_FUNC_PDM1_D, HAL_IOMUX_FUNC_I2S0_WS, },
428 // P0_3
429 { HAL_IOMUX_FUNC_PWM3, HAL_IOMUX_FUNC_UART1_TX, HAL_IOMUX_FUNC_I2C_M1_SDA, HAL_IOMUX_FUNC_SPILCD_CLK,
430 HAL_IOMUX_FUNC_SPILCD_DI2, HAL_IOMUX_FUNC_SPDIF0_DO, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_DISPLAY_BL_PWM,
431 HAL_IOMUX_FUNC_IR_TX, HAL_IOMUX_FUNC_PDM2_D, HAL_IOMUX_FUNC_I2S0_SCK, },
432 // P0_4
433 { HAL_IOMUX_FUNC_PWM4, HAL_IOMUX_FUNC_UART3_RX, HAL_IOMUX_FUNC_I2C_M0_SCL, HAL_IOMUX_FUNC_SPI_DI0,
434 HAL_IOMUX_FUNC_SPILCD_DI3, HAL_IOMUX_FUNC_I2S_MCLK, HAL_IOMUX_FUNC_CLK_OUT, HAL_IOMUX_FUNC_SPI_DCN,
435 HAL_IOMUX_FUNC_SDMMC_DATA7, HAL_IOMUX_FUNC_PDM1_CK, HAL_IOMUX_FUNC_I2S0_SDO3, },
436 // P0_5
437 { HAL_IOMUX_FUNC_PWM5, HAL_IOMUX_FUNC_UART3_TX, HAL_IOMUX_FUNC_I2C_M0_SDA, HAL_IOMUX_FUNC_SPI_CLK,
438 HAL_IOMUX_FUNC_SPILCD_CS1, HAL_IOMUX_FUNC_DISPLAY_SPI_CLK, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_DISPLAY_TE,
439 HAL_IOMUX_FUNC_SDMMC_DATA6, HAL_IOMUX_FUNC_PDM0_D, HAL_IOMUX_FUNC_I2S0_SDO2, },
440 // P0_6
441 { HAL_IOMUX_FUNC_PWM6, HAL_IOMUX_FUNC_UART3_RX, HAL_IOMUX_FUNC_I2C_M1_SCL, HAL_IOMUX_FUNC_SPI_CS0,
442 HAL_IOMUX_FUNC_SPILCD_CS2, HAL_IOMUX_FUNC_DISPLAY_SPI_CS, HAL_IOMUX_FUNC_WF_WAKE_HOST, HAL_IOMUX_FUNC_IR_RX,
443 HAL_IOMUX_FUNC_SDMMC_DATA5, HAL_IOMUX_FUNC_PDM1_D, HAL_IOMUX_FUNC_I2S0_SDO1, },
444 // P0_7
445 { HAL_IOMUX_FUNC_PWM7, HAL_IOMUX_FUNC_UART3_TX, HAL_IOMUX_FUNC_I2C_M1_SDA, HAL_IOMUX_FUNC_SPI_DIO,
446 HAL_IOMUX_FUNC_SPILCD_CS3, HAL_IOMUX_FUNC_DISPLAY_SPI_DIO, HAL_IOMUX_FUNC_SPDIF0_DO, HAL_IOMUX_FUNC_IR_TX,
447 HAL_IOMUX_FUNC_SDMMC_DATA4, HAL_IOMUX_FUNC_PDM2_D, HAL_IOMUX_FUNC_I2S0_SDO0, },
448 // P1_0
449 { HAL_IOMUX_FUNC_PWM0, HAL_IOMUX_FUNC_UART1_RX, HAL_IOMUX_FUNC_I2C_M2_SCL, HAL_IOMUX_FUNC_SPILCD_CLK,
450 HAL_IOMUX_FUNC_SPI_CS1, HAL_IOMUX_FUNC_DISPLAY_SPI_DO1_DCN, HAL_IOMUX_FUNC_IR_RX, HAL_IOMUX_FUNC_WF_SDIO_CLK,
451 HAL_IOMUX_FUNC_SDMMC_DATA2, HAL_IOMUX_FUNC_SPDIF0_DI, HAL_IOMUX_FUNC_I2S0_SDI3, },
452 // P1_1
453 { HAL_IOMUX_FUNC_PWM1, HAL_IOMUX_FUNC_UART1_TX, HAL_IOMUX_FUNC_I2C_M2_SDA, HAL_IOMUX_FUNC_SPILCD_CS0,
454 HAL_IOMUX_FUNC_SPI_CS2, HAL_IOMUX_FUNC_DISPLAY_SPI_DO2, HAL_IOMUX_FUNC_IR_TX, HAL_IOMUX_FUNC_WF_SDIO_CMD,
455 HAL_IOMUX_FUNC_SDMMC_DATA3, HAL_IOMUX_FUNC_SPDIF0_DO, HAL_IOMUX_FUNC_I2S0_SDI2, },
456 // P1_2
457 { HAL_IOMUX_FUNC_PWM2, HAL_IOMUX_FUNC_UART2_RX, HAL_IOMUX_FUNC_I2C_M2_SCL, HAL_IOMUX_FUNC_SPILCD_CS1,
458 HAL_IOMUX_FUNC_SPI_CS3, HAL_IOMUX_FUNC_DISPLAY_SPI_DO3, HAL_IOMUX_FUNC_CLK_32K_IN, HAL_IOMUX_FUNC_WF_SDIO_DATA0,
459 HAL_IOMUX_FUNC_SDMMC_CMD, HAL_IOMUX_FUNC_IR_RX, HAL_IOMUX_FUNC_I2S0_SDI1, },
460 // P1_3
461 { HAL_IOMUX_FUNC_PWM3, HAL_IOMUX_FUNC_UART2_TX, HAL_IOMUX_FUNC_I2C_M2_SDA, HAL_IOMUX_FUNC_SPILCD_DCN,
462 HAL_IOMUX_FUNC_SPI_DI1, HAL_IOMUX_FUNC_I2S_MCLK, HAL_IOMUX_FUNC_CLK_OUT, HAL_IOMUX_FUNC_WF_SDIO_DATA1,
463 HAL_IOMUX_FUNC_SDMMC_CLK, HAL_IOMUX_FUNC_IR_TX, HAL_IOMUX_FUNC_I2S0_SDI0, },
464 // P1_4
465 { HAL_IOMUX_FUNC_PWM4, HAL_IOMUX_FUNC_UART2_RX, HAL_IOMUX_FUNC_I2C_M1_SCL, HAL_IOMUX_FUNC_SPILCD_DI0,
466 HAL_IOMUX_FUNC_SPI_DI2, HAL_IOMUX_FUNC_DISPLAY_SPI_DI, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_WF_SDIO_DATA2,
467 HAL_IOMUX_FUNC_SDMMC_DATA0, HAL_IOMUX_FUNC_IR_RX, HAL_IOMUX_FUNC_DISPLAY_TE, },
468 // P1_5
469 { HAL_IOMUX_FUNC_PWM5, HAL_IOMUX_FUNC_UART2_TX, HAL_IOMUX_FUNC_I2C_M1_SDA, HAL_IOMUX_FUNC_SPILCD_DIO,
470 HAL_IOMUX_FUNC_SPI_DI3, HAL_IOMUX_FUNC_I2S_MCLK, HAL_IOMUX_FUNC_CLK_OUT, HAL_IOMUX_FUNC_WF_SDIO_DATA3,
471 HAL_IOMUX_FUNC_SDMMC_DATA1, HAL_IOMUX_FUNC_IR_TX, HAL_IOMUX_FUNC_DISPLAY_TE, },
472 // P1_6
473 { HAL_IOMUX_FUNC_PWM6, HAL_IOMUX_FUNC_UART0_RX, HAL_IOMUX_FUNC_I2C_M0_SCL, HAL_IOMUX_FUNC_NONE,
474 HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_WF_WAKE_HOST,
475 HAL_IOMUX_FUNC_BT_UART_RX, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE, },
476 // P1_7
477 { HAL_IOMUX_FUNC_PWM7, HAL_IOMUX_FUNC_UART0_TX, HAL_IOMUX_FUNC_I2C_M0_SDA, HAL_IOMUX_FUNC_NONE,
478 HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE,
479 HAL_IOMUX_FUNC_BT_UART_TX, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE, },
480 // P2_0
481 { HAL_IOMUX_FUNC_PWM0, HAL_IOMUX_FUNC_UART1_RX, HAL_IOMUX_FUNC_I2C_M0_SCL, HAL_IOMUX_FUNC_SPILCD_DI0,
482 HAL_IOMUX_FUNC_SPILCD_DCN, HAL_IOMUX_FUNC_I2S_MCLK, HAL_IOMUX_FUNC_CLK_OUT, HAL_IOMUX_FUNC_WF_UART_RX,
483 HAL_IOMUX_FUNC_BT_UART_RX, HAL_IOMUX_FUNC_SPDIF0_DI, HAL_IOMUX_FUNC_I2S1_SDI0, },
484 // P2_1
485 { HAL_IOMUX_FUNC_PWM1, HAL_IOMUX_FUNC_UART1_TX, HAL_IOMUX_FUNC_I2C_M0_SDA, HAL_IOMUX_FUNC_SPILCD_DIO,
486 HAL_IOMUX_FUNC_IR_TX, HAL_IOMUX_FUNC_DISPLAY_TE, HAL_IOMUX_FUNC_CLK_OUT, HAL_IOMUX_FUNC_WF_UART_TX,
487 HAL_IOMUX_FUNC_BT_UART_TX, HAL_IOMUX_FUNC_SPDIF0_DO, HAL_IOMUX_FUNC_I2S1_SDO0, },
488 // P2_2
489 { HAL_IOMUX_FUNC_PWM2, HAL_IOMUX_FUNC_UART2_RX, HAL_IOMUX_FUNC_I2C_M1_SCL, HAL_IOMUX_FUNC_SPILCD_CS0,
490 HAL_IOMUX_FUNC_DISPLAY_BL_EN, HAL_IOMUX_FUNC_I2S_MCLK, HAL_IOMUX_FUNC_CLK_OUT, HAL_IOMUX_FUNC_WF_UART_CTS,
491 HAL_IOMUX_FUNC_BT_UART_CTS, HAL_IOMUX_FUNC_IR_RX, HAL_IOMUX_FUNC_I2S1_WS, },
492 // P2_3
493 { HAL_IOMUX_FUNC_PWM3, HAL_IOMUX_FUNC_UART2_TX, HAL_IOMUX_FUNC_I2C_M1_SDA, HAL_IOMUX_FUNC_SPILCD_CLK,
494 HAL_IOMUX_FUNC_SPI_DCN, HAL_IOMUX_FUNC_DISPLAY_BL_PWM, HAL_IOMUX_FUNC_PCM_DI, HAL_IOMUX_FUNC_WF_UART_RTS,
495 HAL_IOMUX_FUNC_BT_UART_RTS, HAL_IOMUX_FUNC_CLK_OUT, HAL_IOMUX_FUNC_I2S1_SCK, },
496 // P2_4
497 { HAL_IOMUX_FUNC_PWM4, HAL_IOMUX_FUNC_UART3_RX, HAL_IOMUX_FUNC_I2C_M2_SCL, HAL_IOMUX_FUNC_SPI_DI0,
498 HAL_IOMUX_FUNC_SPI_DI3, HAL_IOMUX_FUNC_SPI_DCN, HAL_IOMUX_FUNC_PCM_DO, HAL_IOMUX_FUNC_SPDIF0_DI,
499 HAL_IOMUX_FUNC_WF_SDIO_CLK, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_I2S1_SDO3, },
500 // P2_5
501 { HAL_IOMUX_FUNC_PWM5, HAL_IOMUX_FUNC_UART3_TX, HAL_IOMUX_FUNC_I2C_M2_SDA, HAL_IOMUX_FUNC_SPI_DIO,
502 HAL_IOMUX_FUNC_SPI_CS3, HAL_IOMUX_FUNC_DISPLAY_TE, HAL_IOMUX_FUNC_PCM_FSYNC, HAL_IOMUX_FUNC_NONE,
503 HAL_IOMUX_FUNC_WF_SDIO_CMD, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_I2S1_SDO2, },
504 // P2_6
505 { HAL_IOMUX_FUNC_PWM6, HAL_IOMUX_FUNC_UART3_RX, HAL_IOMUX_FUNC_I2C_M0_SCL, HAL_IOMUX_FUNC_SPI_CS0,
506 HAL_IOMUX_FUNC_SPILCD_DI1, HAL_IOMUX_FUNC_CLK_32K_IN, HAL_IOMUX_FUNC_PCM_CLK, HAL_IOMUX_FUNC_IR_RX,
507 HAL_IOMUX_FUNC_WF_SDIO_DATA0, HAL_IOMUX_FUNC_SPDIF0_DI, HAL_IOMUX_FUNC_I2S1_SDO1, },
508 // P2_7
509 { HAL_IOMUX_FUNC_PWM7, HAL_IOMUX_FUNC_UART3_TX, HAL_IOMUX_FUNC_I2C_M0_SDA, HAL_IOMUX_FUNC_SPI_CLK,
510 HAL_IOMUX_FUNC_SPILCD_CS1, HAL_IOMUX_FUNC_I2S_MCLK, HAL_IOMUX_FUNC_CLK_OUT, HAL_IOMUX_FUNC_IR_TX,
511 HAL_IOMUX_FUNC_WF_SDIO_DATA1, HAL_IOMUX_FUNC_SPDIF0_DO, HAL_IOMUX_FUNC_I2S1_SDO0, },
512 // P3_0
513 { HAL_IOMUX_FUNC_PWM0, HAL_IOMUX_FUNC_UART1_RX, HAL_IOMUX_FUNC_I2C_M1_SCL, HAL_IOMUX_FUNC_SPI_DI0,
514 HAL_IOMUX_FUNC_SPILCD_DI2, HAL_IOMUX_FUNC_SPI_DCN, HAL_IOMUX_FUNC_WF_UART_RX, HAL_IOMUX_FUNC_SPILCD_CS1,
515 HAL_IOMUX_FUNC_WF_SDIO_DATA2, HAL_IOMUX_FUNC_PDM0_D, HAL_IOMUX_FUNC_I2S1_SDI3, },
516 // P3_1
517 { HAL_IOMUX_FUNC_PWM1, HAL_IOMUX_FUNC_UART1_TX, HAL_IOMUX_FUNC_I2C_M1_SDA, HAL_IOMUX_FUNC_SPI_DIO,
518 HAL_IOMUX_FUNC_WF_SDIO_DATA0, HAL_IOMUX_FUNC_DISPLAY_SPI_DI, HAL_IOMUX_FUNC_WF_UART_TX, HAL_IOMUX_FUNC_IR_RX,
519 HAL_IOMUX_FUNC_WF_SDIO_DATA3, HAL_IOMUX_FUNC_PDM1_D, HAL_IOMUX_FUNC_I2S1_SDI2, },
520 // P3_2
521 { HAL_IOMUX_FUNC_PWM2, HAL_IOMUX_FUNC_UART1_RX, HAL_IOMUX_FUNC_I2C_M2_SCL, HAL_IOMUX_FUNC_SPI_CS0,
522 HAL_IOMUX_FUNC_SPILCD_CS3, HAL_IOMUX_FUNC_DISPLAY_SPI_DO3, HAL_IOMUX_FUNC_WF_UART_CTS, HAL_IOMUX_FUNC_IR_TX,
523 HAL_IOMUX_FUNC_WF_WAKE_HOST, HAL_IOMUX_FUNC_PDM2_D, HAL_IOMUX_FUNC_I2S1_SDI1, },
524 // P3_3
525 { HAL_IOMUX_FUNC_PWM3, HAL_IOMUX_FUNC_UART1_TX, HAL_IOMUX_FUNC_I2C_M2_SDA, HAL_IOMUX_FUNC_SPI_CLK,
526 HAL_IOMUX_FUNC_SPILCD_DI3, HAL_IOMUX_FUNC_DISPLAY_SPI_DO2, HAL_IOMUX_FUNC_WF_UART_RTS, HAL_IOMUX_FUNC_SPILCD_DCN,
527 HAL_IOMUX_FUNC_IR_RX, HAL_IOMUX_FUNC_PDM2_CK, HAL_IOMUX_FUNC_I2S1_SDI0, },
528 // P3_4
529 { HAL_IOMUX_FUNC_PWM4, HAL_IOMUX_FUNC_UART3_RX, HAL_IOMUX_FUNC_I2C_M0_SCL, HAL_IOMUX_FUNC_SPILCD_DI0,
530 HAL_IOMUX_FUNC_SPI_DI1, HAL_IOMUX_FUNC_DISPLAY_SPI_DO1_DCN, HAL_IOMUX_FUNC_CLK_OUT, HAL_IOMUX_FUNC_SPILCD_DCN,
531 HAL_IOMUX_FUNC_IR_TX, HAL_IOMUX_FUNC_PDM0_CK, HAL_IOMUX_FUNC_I2S0_SDI3, },
532 // P3_5
533 { HAL_IOMUX_FUNC_PWM5, HAL_IOMUX_FUNC_UART3_TX, HAL_IOMUX_FUNC_I2C_M0_SDA, HAL_IOMUX_FUNC_SPILCD_DIO,
534 HAL_IOMUX_FUNC_SPI_CS1, HAL_IOMUX_FUNC_DISPLAY_SPI_DIO, HAL_IOMUX_FUNC_CLK_32K_IN, HAL_IOMUX_FUNC_NONE,
535 HAL_IOMUX_FUNC_DISPLAY_TE, HAL_IOMUX_FUNC_PDM0_D, HAL_IOMUX_FUNC_I2S0_SDI2, },
536 // P3_6
537 { HAL_IOMUX_FUNC_PWM6, HAL_IOMUX_FUNC_UART2_RX, HAL_IOMUX_FUNC_I2C_M2_SCL, HAL_IOMUX_FUNC_SPILCD_CS0,
538 HAL_IOMUX_FUNC_SPI_DI2, HAL_IOMUX_FUNC_DISPLAY_SPI_CS, HAL_IOMUX_FUNC_CLK_REQ_OUT, HAL_IOMUX_FUNC_SPDIF0_DI,
539 HAL_IOMUX_FUNC_IR_RX, HAL_IOMUX_FUNC_PDM1_D, HAL_IOMUX_FUNC_I2S0_SDI1, },
540 // P3_7
541 { HAL_IOMUX_FUNC_PWM7, HAL_IOMUX_FUNC_UART2_TX, HAL_IOMUX_FUNC_I2C_M2_SDA, HAL_IOMUX_FUNC_SPILCD_CLK,
542 HAL_IOMUX_FUNC_SPI_CS2, HAL_IOMUX_FUNC_DISPLAY_SPI_CLK, HAL_IOMUX_FUNC_CLK_REQ_IN, HAL_IOMUX_FUNC_SPDIF0_DO,
543 HAL_IOMUX_FUNC_IR_TX, HAL_IOMUX_FUNC_PDM2_D, HAL_IOMUX_FUNC_I2S0_SDI0, },
544 };
545
546 static struct IOMUX_T * const iomux = (struct IOMUX_T *)IOMUX_BASE;
547
548 #ifdef ANC_PROD_TEST
549 #define OPT_TYPE
550 #else
551 #define OPT_TYPE const
552 #endif
553
554 static OPT_TYPE enum HAL_IOMUX_PIN_T digmic_ck_pin = DIG_MIC_CK_IOMUX_PIN;
555
556 static OPT_TYPE enum HAL_IOMUX_PIN_T digmic_d0_pin = DIG_MIC_D0_IOMUX_PIN;
557 static OPT_TYPE enum HAL_IOMUX_PIN_T digmic_d1_pin = DIG_MIC_D1_IOMUX_PIN;
558 static OPT_TYPE enum HAL_IOMUX_PIN_T digmic_d2_pin = DIG_MIC_D2_IOMUX_PIN;
559
hal_iomux_set_default_config(void)560 void hal_iomux_set_default_config(void)
561 {
562 uint32_t i;
563 // Set all unused GPIOs to pull-down by default
564 for (i = 0; i < 8; i++) {
565 if (((iomux->REG_004 & (0xF << (i * 4))) >> (i * 4)) == 0xF) {
566 iomux->REG_02C &= ~(1 << i);
567 iomux->REG_030 |= (1 << i);
568 }
569 }
570 for (i = 0; i < 6; i++) {
571 if (((iomux->REG_008 & (0xF << (i * 4))) >> (i * 4)) == 0xF) {
572 iomux->REG_02C &= ~(1 << (i + 8));
573 iomux->REG_030 |= (1 << (i + 8));
574 }
575 }
576 for (i = 0; i < 8; i++) {
577 if (((iomux->REG_00C & (0xF << (i * 4))) >> (i * 4)) == 0xF) {
578 iomux->REG_02C &= ~(1 << (i + 16));
579 iomux->REG_030 |= (1 << (i + 16));
580 }
581 }
582 for (i = 0; i < 8; i++) {
583 if (((iomux->REG_010 & (0xF << (i * 4))) >> (i * 4)) == 0xF) {
584 iomux->REG_02C &= ~(1 << (i + 24));
585 iomux->REG_030 |= (1 << (i + 24));
586 }
587 }
588 }
589
hal_iomux_check(const struct HAL_IOMUX_PIN_FUNCTION_MAP * map,uint32_t count)590 uint32_t hal_iomux_check(const struct HAL_IOMUX_PIN_FUNCTION_MAP *map, uint32_t count)
591 {
592 uint32_t i;
593 for (i = 0; i < count; ++i) {
594 }
595 return 0;
596 }
597
hal_iomux_init(const struct HAL_IOMUX_PIN_FUNCTION_MAP * map,uint32_t count)598 uint32_t hal_iomux_init(const struct HAL_IOMUX_PIN_FUNCTION_MAP *map, uint32_t count)
599 {
600 uint32_t i;
601 uint32_t ret;
602
603 if (map == NULL)
604 return 1;
605
606 for (i = 0; i < count; ++i) {
607 ret = hal_iomux_set_function(map[i].pin, map[i].function, HAL_IOMUX_OP_CLEAN_OTHER_FUNC_BIT);
608 if (ret) {
609 return (i << 8) + 1;
610 }
611 ret = hal_iomux_set_io_voltage_domains(map[i].pin, map[i].volt);
612 if (ret) {
613 return (i << 8) + 2;
614 }
615 ret = hal_iomux_set_io_pull_select(map[i].pin, map[i].pull_sel);
616 if (ret) {
617 return (i << 8) + 3;
618 }
619 }
620
621 return 0;
622 }
623
hal_iomux_set_function(enum HAL_IOMUX_PIN_T pin,enum HAL_IOMUX_FUNCTION_T func,enum HAL_IOMUX_OP_TYPE_T type)624 uint32_t hal_iomux_set_function(enum HAL_IOMUX_PIN_T pin, enum HAL_IOMUX_FUNCTION_T func, enum HAL_IOMUX_OP_TYPE_T type)
625 {
626 int i;
627 uint8_t val;
628 __IO uint32_t *reg;
629 uint32_t shift;
630
631 if (pin >= HAL_IOMUX_PIN_LED_NUM) {
632 return 1;
633 }
634 if (func >= HAL_IOMUX_FUNC_END) {
635 return 2;
636 }
637
638 if (pin == HAL_IOMUX_PIN_P1_6 || pin == HAL_IOMUX_PIN_P1_7) {
639 if (func == HAL_IOMUX_FUNC_I2C_M0_SCL || func == HAL_IOMUX_FUNC_I2C_M0_SDA) {
640 // Enable analog I2C slave
641 #ifndef FPGA
642 iomux->REG_050 &= ~IOMUX_GPIO_I2C_MODE;
643 #endif
644 // Set mcu GPIO func
645 iomux->REG_008 = (iomux->REG_008 & ~(IOMUX_GPIO_P16_SEL_MASK | IOMUX_GPIO_P17_SEL_MASK)) |
646 IOMUX_GPIO_P16_SEL(IOMUX_FUNC_VAL_GPIO) | IOMUX_GPIO_P17_SEL(IOMUX_FUNC_VAL_GPIO);
647 return 0;
648 } else {
649 #ifndef FPGA
650 iomux->REG_050 |= IOMUX_GPIO_I2C_MODE;
651 #endif
652 // Continue to set the alt func
653 }
654 } else if (pin == HAL_IOMUX_PIN_P0_2) {
655 if (func == HAL_IOMUX_FUNC_SPDIF0_DI) {
656 iomux->REG_004 = SET_BITFIELD(iomux->REG_004, IOMUX_GPIO_P02_SEL, 6);
657 return 0;
658 }
659 } else if (pin == HAL_IOMUX_PIN_P0_3) {
660 if (func == HAL_IOMUX_FUNC_SPDIF0_DO) {
661 iomux->REG_004 = SET_BITFIELD(iomux->REG_004, IOMUX_GPIO_P03_SEL, 6);
662 return 0;
663 }
664 } else if (pin == HAL_IOMUX_PIN_P2_0) {
665 if (func == HAL_IOMUX_FUNC_CLK_REQ_OUT) {
666 iomux->REG_00C = SET_BITFIELD(iomux->REG_00C, IOMUX_GPIO_P20_SEL, 9);
667 return 0;
668 }
669 } else if (pin == HAL_IOMUX_PIN_P2_1) {
670 if (func == HAL_IOMUX_FUNC_CLK_REQ_IN) {
671 iomux->REG_00C = SET_BITFIELD(iomux->REG_00C, IOMUX_GPIO_P21_SEL, 9);
672 return 0;
673 }
674 } else if (pin == HAL_IOMUX_PIN_LED1 || pin == HAL_IOMUX_PIN_LED2) {
675 ASSERT(func == HAL_IOMUX_FUNC_GPIO, "Bad func=%d for IOMUX pin=%d", func, pin);
676 return 0;
677 }
678
679 if (func == HAL_IOMUX_FUNC_GPIO) {
680 val = IOMUX_FUNC_VAL_GPIO;
681 } else {
682 for (i = 0; i < IOMUX_ALT_FUNC_NUM; i++) {
683 if (pin_func_map[pin][i] == func) {
684 break;
685 }
686 }
687
688 if (i == IOMUX_ALT_FUNC_NUM) {
689 ASSERT(0, "[Func %d io %d] is unsupported by pin_func_map. Check it or use reg assignment like iomux_set_uart0.", pin, func);
690 return 3;
691 }
692 val = index_to_func_val[i];
693 }
694
695 reg = &iomux->REG_004 + pin / 8;
696 shift = (pin % 8) * 4;
697
698 *reg = (*reg & ~(0xF << shift)) | (val << shift);
699
700 return 0;
701 }
702
hal_iomux_get_function(enum HAL_IOMUX_PIN_T pin)703 enum HAL_IOMUX_FUNCTION_T hal_iomux_get_function(enum HAL_IOMUX_PIN_T pin)
704 {
705 return HAL_IOMUX_FUNC_NONE;
706 }
707
hal_iomux_set_io_voltage_domains(enum HAL_IOMUX_PIN_T pin,enum HAL_IOMUX_PIN_VOLTAGE_DOMAINS_T volt)708 uint32_t hal_iomux_set_io_voltage_domains(enum HAL_IOMUX_PIN_T pin, enum HAL_IOMUX_PIN_VOLTAGE_DOMAINS_T volt)
709 {
710 if (pin >= HAL_IOMUX_PIN_LED_NUM) {
711 return 1;
712 }
713 #if !defined(CHIP_A7_DSP)
714 if (pin == HAL_IOMUX_PIN_LED1 || pin == HAL_IOMUX_PIN_LED2) {
715 pmu_led_set_voltage_domains(pin, volt);
716 }
717 #endif
718 return 0;
719 }
720
hal_iomux_set_io_pull_select(enum HAL_IOMUX_PIN_T pin,enum HAL_IOMUX_PIN_PULL_SELECT_T pull_sel)721 uint32_t hal_iomux_set_io_pull_select(enum HAL_IOMUX_PIN_T pin, enum HAL_IOMUX_PIN_PULL_SELECT_T pull_sel)
722 {
723 if (pin >= HAL_IOMUX_PIN_LED_NUM) {
724 return 1;
725 }
726
727 if (pin < HAL_IOMUX_PIN_NUM) {
728 iomux->REG_02C &= ~(1 << pin);
729 iomux->REG_030 &= ~(1 << pin);
730 if (pull_sel == HAL_IOMUX_PIN_PULLUP_ENABLE) {
731 iomux->REG_02C |= (1 << pin);
732 } else if (pull_sel == HAL_IOMUX_PIN_PULLDOWN_ENABLE) {
733 iomux->REG_030 |= (1 << pin);
734 }
735 #if !defined(CHIP_A7_DSP)
736 } else if (pin == HAL_IOMUX_PIN_LED1 || pin == HAL_IOMUX_PIN_LED2) {
737 pmu_led_set_pull_select(pin, pull_sel);
738 #endif
739 }
740
741 return 0;
742 }
743
hal_iomux_set_io_drv(enum HAL_IOMUX_PIN_T pin,uint32_t val)744 uint32_t hal_iomux_set_io_drv(enum HAL_IOMUX_PIN_T pin, uint32_t val)
745 {
746 if (pin >= HAL_IOMUX_PIN_NUM) {
747 return 1;
748 }
749 if (val > 3) {
750 return 2;
751 }
752 if (pin < HAL_IOMUX_PIN_P2_0)
753 iomux->REG_074 = (iomux->REG_074 & ~(IOMUX_GPIO_P0_DRV0_SEL_MASK << 2*(pin-HAL_IOMUX_PIN_P0_0))) |
754 (IOMUX_GPIO_P0_DRV0_SEL(val) << 2*(pin-HAL_IOMUX_PIN_P0_0));
755 else
756 iomux->REG_078 = (iomux->REG_078 & ~(IOMUX_GPIO_P0_DRV0_SEL_MASK << 2*(pin-HAL_IOMUX_PIN_P2_0))) |
757 (IOMUX_GPIO_P0_DRV0_SEL(val) << 2*(pin-HAL_IOMUX_PIN_P2_0));
758 return 0;
759 }
760
hal_iomux_set_sdmmc_dt_n_out_group(int enable)761 void hal_iomux_set_sdmmc_dt_n_out_group(int enable)
762 {
763 }
764
hal_iomux_set_uart0_voltage(enum HAL_IOMUX_PIN_VOLTAGE_DOMAINS_T volt)765 void hal_iomux_set_uart0_voltage(enum HAL_IOMUX_PIN_VOLTAGE_DOMAINS_T volt)
766 {
767 }
768
hal_iomux_set_uart1_voltage(enum HAL_IOMUX_PIN_VOLTAGE_DOMAINS_T volt)769 void hal_iomux_set_uart1_voltage(enum HAL_IOMUX_PIN_VOLTAGE_DOMAINS_T volt)
770 {
771 }
772
hal_iomux_uart0_connected(void)773 bool hal_iomux_uart0_connected(void)
774 {
775 uint32_t reg_050, reg_008, reg_02c, reg_030;
776 uint32_t mask;
777 int val;
778
779 // Save current iomux settings
780 reg_050 = iomux->REG_050;
781 reg_008 = iomux->REG_008;
782 reg_02c = iomux->REG_02C;
783 reg_030 = iomux->REG_030;
784
785 // Disable analog I2C slave & master
786 #ifndef FPGA
787 iomux->REG_050 |= IOMUX_GPIO_I2C_MODE | IOMUX_I2C0_M_SEL_GPIO;
788 #endif
789 // Set uart0-rx as gpio
790 iomux->REG_008 = SET_BITFIELD(iomux->REG_008, IOMUX_GPIO_P16_SEL, IOMUX_FUNC_VAL_GPIO);
791
792 mask = (1 << HAL_IOMUX_PIN_P1_6);
793 // Clear pullup
794 iomux->REG_02C &= ~mask;
795 // Setup pulldown
796 iomux->REG_030 |= mask;
797
798 hal_gpio_pin_set_dir((enum HAL_GPIO_PIN_T)HAL_IOMUX_PIN_P1_6, HAL_GPIO_DIR_IN, 0);
799
800 hal_sys_timer_delay(MS_TO_TICKS(2));
801
802 val = hal_gpio_pin_get_val((enum HAL_GPIO_PIN_T)HAL_IOMUX_PIN_P1_6);
803
804 // Restore iomux settings
805 iomux->REG_030 = reg_030;
806 iomux->REG_02C = reg_02c;
807 iomux->REG_008 = reg_008;
808 iomux->REG_050 = reg_050;
809
810 hal_sys_timer_delay(MS_TO_TICKS(2));
811
812 return !!val;
813 }
814
hal_iomux_uart1_connected(void)815 bool hal_iomux_uart1_connected(void)
816 {
817 uint32_t reg_00c, reg_02c, reg_030;
818 uint32_t mask;
819 int val;
820
821 // Save current iomux settings
822 reg_00c = iomux->REG_00C;
823 reg_02c = iomux->REG_02C;
824 reg_030 = iomux->REG_030;
825
826 // Set uart1-rx as gpio
827 iomux->REG_00C = SET_BITFIELD(iomux->REG_00C, IOMUX_GPIO_P20_SEL, IOMUX_FUNC_VAL_GPIO);
828
829 mask = (1 << HAL_IOMUX_PIN_P2_0);
830 // Clear pullup
831 iomux->REG_02C &= ~mask;
832 // Setup pulldown
833 iomux->REG_030 |= mask;
834
835 hal_gpio_pin_set_dir((enum HAL_GPIO_PIN_T)HAL_IOMUX_PIN_P2_0, HAL_GPIO_DIR_IN, 0);
836
837 hal_sys_timer_delay(MS_TO_TICKS(2));
838
839 val = hal_gpio_pin_get_val((enum HAL_GPIO_PIN_T)HAL_IOMUX_PIN_P2_0);
840
841 // Restore iomux settings
842 iomux->REG_030 = reg_030;
843 iomux->REG_02C = reg_02c;
844 iomux->REG_00C = reg_00c;
845
846 hal_sys_timer_delay(MS_TO_TICKS(2));
847
848 return !!val;
849 }
850
hal_iomux_set_uart0(void)851 void hal_iomux_set_uart0(void)
852 {
853 uint32_t mask;
854
855 // Disable analog I2C slave & master
856 #ifndef FPGA
857 iomux->REG_050 |= IOMUX_GPIO_I2C_MODE | IOMUX_I2C0_M_SEL_GPIO;
858 #endif
859 // Set uart0 func
860 iomux->REG_008 = (iomux->REG_008 & ~(IOMUX_GPIO_P16_SEL_MASK | IOMUX_GPIO_P17_SEL_MASK)) |
861 IOMUX_GPIO_P16_SEL(1) | IOMUX_GPIO_P17_SEL(1);
862
863 mask = (1 << HAL_IOMUX_PIN_P1_6) | (1 << HAL_IOMUX_PIN_P1_7);
864 // Setup pullup
865 iomux->REG_02C |= (1 << HAL_IOMUX_PIN_P1_6);
866 iomux->REG_02C &= ~(1 << HAL_IOMUX_PIN_P1_7);
867 // Clear pulldown
868 iomux->REG_030 &= ~mask;
869 }
870
hal_iomux_set_uart1(void)871 void hal_iomux_set_uart1(void)
872 {
873 uint32_t mask_pd_c, mask_pu, mask_pu_c;
874
875 // Set uart1 func
876 #if (UART1_IOMUX_INDEX == 02)
877 iomux->REG_004 = (iomux->REG_004 & ~(IOMUX_GPIO_P02_SEL_MASK | IOMUX_GPIO_P03_SEL_MASK)) |
878 IOMUX_GPIO_P02_SEL(1) | IOMUX_GPIO_P03_SEL(1);
879 mask_pd_c = (1 << HAL_IOMUX_PIN_P0_2) | (1 << HAL_IOMUX_PIN_P0_3);
880 mask_pu = (1 << HAL_IOMUX_PIN_P0_2);
881 mask_pu_c = (1 << HAL_IOMUX_PIN_P0_3);
882 #elif (UART1_IOMUX_INDEX == 03) // 32: UART1 RX; 03 UART1 TX
883 iomux->REG_010 = (iomux->REG_010 & ~(IOMUX_GPIO_P32_SEL_MASK)) | IOMUX_GPIO_P32_SEL(1);
884 iomux->REG_004 = (iomux->REG_004 & ~(IOMUX_GPIO_P03_SEL_MASK)) | IOMUX_GPIO_P03_SEL(1);
885
886 mask_pd_c = (1 << HAL_IOMUX_PIN_P0_3) | (1 << HAL_IOMUX_PIN_P3_2);
887 mask_pu = (1 << HAL_IOMUX_PIN_P3_2);
888 mask_pu_c = (1 << HAL_IOMUX_PIN_P0_3);
889 #elif (UART1_IOMUX_INDEX == 10)
890 iomux->REG_008 = (iomux->REG_008 & ~(IOMUX_GPIO_P10_SEL_MASK | IOMUX_GPIO_P11_SEL_MASK)) |
891 IOMUX_GPIO_P10_SEL(1) | IOMUX_GPIO_P11_SEL(1);
892
893 mask_pd_c = (1 << HAL_IOMUX_PIN_P1_0) | (1 << HAL_IOMUX_PIN_P1_1);
894 mask_pu = (1 << HAL_IOMUX_PIN_P1_0);
895 mask_pu_c = (1 << HAL_IOMUX_PIN_P1_1);
896 #elif (UART1_IOMUX_INDEX == 20)
897 iomux->REG_00C = (iomux->REG_00C & ~(IOMUX_GPIO_P20_SEL_MASK | IOMUX_GPIO_P21_SEL_MASK)) |
898 IOMUX_GPIO_P20_SEL(1) | IOMUX_GPIO_P21_SEL(1);
899
900 mask_pd_c = (1 << HAL_IOMUX_PIN_P2_0) | (1 << HAL_IOMUX_PIN_P2_1);
901 mask_pu = (1 << HAL_IOMUX_PIN_P2_0);
902 mask_pu_c = (1 << HAL_IOMUX_PIN_P2_1);
903 #elif (UART1_IOMUX_INDEX == 30)
904 iomux->REG_010 = (iomux->REG_010 & ~(IOMUX_GPIO_P30_SEL_MASK | IOMUX_GPIO_P31_SEL_MASK)) |
905 IOMUX_GPIO_P30_SEL(1) | IOMUX_GPIO_P31_SEL(1);
906
907 mask_pd_c = (1 << HAL_IOMUX_PIN_P3_0) | (1 << HAL_IOMUX_PIN_P3_1);
908 mask_pu = (1 << HAL_IOMUX_PIN_P3_0);
909 mask_pu_c = (1 << HAL_IOMUX_PIN_P3_1);
910 #elif (UART1_IOMUX_INDEX == 32)
911 iomux->REG_010 = (iomux->REG_010 & ~(IOMUX_GPIO_P32_SEL_MASK | IOMUX_GPIO_P33_SEL_MASK)) |
912 IOMUX_GPIO_P32_SEL(1) | IOMUX_GPIO_P33_SEL(1);
913
914 mask_pd_c = (1 << HAL_IOMUX_PIN_P3_2) | (1 << HAL_IOMUX_PIN_P3_3);
915 mask_pu = (1 << HAL_IOMUX_PIN_P3_2);
916 mask_pu_c = (1 << HAL_IOMUX_PIN_P3_3);
917 #else
918 #error "Unsupported UART1_IOMUX_INDEX"
919 #endif
920 // Setup pullup
921 iomux->REG_02C |= mask_pu;
922 iomux->REG_02C &= ~(mask_pu_c);
923 // Clear pulldown
924 iomux->REG_030 &= ~mask_pd_c;
925 }
926
hal_iomux_set_uart2(void)927 void hal_iomux_set_uart2(void)
928 {
929 uint32_t mask_pd_c, mask_pu, mask_pu_c;
930
931 // Set uart1 func
932 #if (UART2_IOMUX_INDEX == 00)
933 iomux->REG_004 = (iomux->REG_004 & ~(IOMUX_GPIO_P00_SEL_MASK | IOMUX_GPIO_P01_SEL_MASK)) |
934 IOMUX_GPIO_P00_SEL(1) | IOMUX_GPIO_P01_SEL(1);
935 mask_pd_c = (1 << HAL_IOMUX_PIN_P0_0) | (1 << HAL_IOMUX_PIN_P0_1);
936 mask_pu = (1 << HAL_IOMUX_PIN_P0_0);
937 mask_pu_c = (1 << HAL_IOMUX_PIN_P0_1);
938 #elif (UART2_IOMUX_INDEX == 12)
939 iomux->REG_008 = (iomux->REG_008 & ~(IOMUX_GPIO_P12_SEL_MASK | IOMUX_GPIO_P13_SEL_MASK)) |
940 IOMUX_GPIO_P12_SEL(1) | IOMUX_GPIO_P13_SEL(1);
941
942 mask_pd_c = (1 << HAL_IOMUX_PIN_P1_2) | (1 << HAL_IOMUX_PIN_P1_3);
943 mask_pu = (1 << HAL_IOMUX_PIN_P1_2);
944 mask_pu_c = (1 << HAL_IOMUX_PIN_P1_3);
945 #elif (UART2_IOMUX_INDEX == 14)
946 iomux->REG_008 = (iomux->REG_008 & ~(IOMUX_GPIO_P14_SEL_MASK | IOMUX_GPIO_P15_SEL_MASK)) |
947 IOMUX_GPIO_P14_SEL(1) | IOMUX_GPIO_P15_SEL(1);
948
949 mask_pd_c = (1 << HAL_IOMUX_PIN_P1_4) | (1 << HAL_IOMUX_PIN_P1_5);
950 mask_pu = (1 << HAL_IOMUX_PIN_P1_4);
951 mask_pu_c = (1 << HAL_IOMUX_PIN_P1_5);
952 #elif (UART2_IOMUX_INDEX == 22)
953 iomux->REG_00C = (iomux->REG_00C & ~(IOMUX_GPIO_P22_SEL_MASK | IOMUX_GPIO_P23_SEL_MASK)) |
954 IOMUX_GPIO_P22_SEL(1) | IOMUX_GPIO_P23_SEL(1);
955
956 mask_pd_c = (1 << HAL_IOMUX_PIN_P2_2) | (1 << HAL_IOMUX_PIN_P2_3);
957 mask_pu = (1 << HAL_IOMUX_PIN_P2_2);
958 mask_pu_c = (1 << HAL_IOMUX_PIN_P2_3);
959 #elif (UART2_IOMUX_INDEX == 36)
960 iomux->REG_010 = (iomux->REG_010 & ~(IOMUX_GPIO_P36_SEL_MASK | IOMUX_GPIO_P37_SEL_MASK)) |
961 IOMUX_GPIO_P36_SEL(1) | IOMUX_GPIO_P37_SEL(1);
962
963 mask_pd_c = (1 << HAL_IOMUX_PIN_P3_6) | (1 << HAL_IOMUX_PIN_P3_7);
964 mask_pu = (1 << HAL_IOMUX_PIN_P3_6);
965 mask_pu_c = (1 << HAL_IOMUX_PIN_P3_7);
966 #else
967 #error "Unsupported UART1_IOMUX_INDEX"
968 #endif
969 // Setup pullup
970 iomux->REG_02C |= mask_pu;
971 iomux->REG_02C &= ~(mask_pu_c);
972 // Clear pulldown
973 iomux->REG_030 &= ~mask_pd_c;
974 }
975
hal_iomux_set_uart3(void)976 void hal_iomux_set_uart3(void)
977 {
978 uint32_t mask_pd_c, mask_pu, mask_pu_c;
979
980 // Set uart1 func
981 #if (UART3_IOMUX_INDEX == 04)
982 iomux->REG_004 = (iomux->REG_004 & ~(IOMUX_GPIO_P04_SEL_MASK | IOMUX_GPIO_P05_SEL_MASK)) |
983 IOMUX_GPIO_P04_SEL(1) | IOMUX_GPIO_P05_SEL(1);
984 mask_pd_c = (1 << HAL_IOMUX_PIN_P0_4) | (1 << HAL_IOMUX_PIN_P0_5);
985 mask_pu = (1 << HAL_IOMUX_PIN_P0_4);
986 mask_pu_c = (1 << HAL_IOMUX_PIN_P0_5);
987 #elif (UART3_IOMUX_INDEX == 06)
988 iomux->REG_004 = (iomux->REG_004 & ~(IOMUX_GPIO_P06_SEL_MASK | IOMUX_GPIO_P07_SEL_MASK)) |
989 IOMUX_GPIO_P06_SEL(1) | IOMUX_GPIO_P07_SEL(1);
990 mask_pd_c = (1 << HAL_IOMUX_PIN_P0_6) | (1 << HAL_IOMUX_PIN_P0_7);
991 mask_pu = (1 << HAL_IOMUX_PIN_P0_6);
992 mask_pu_c = (1 << HAL_IOMUX_PIN_P0_7);
993 #elif (UART3_IOMUX_INDEX == 24)
994 iomux->REG_00C = (iomux->REG_00C & ~(IOMUX_GPIO_P24_SEL_MASK | IOMUX_GPIO_P25_SEL_MASK)) |
995 IOMUX_GPIO_P24_SEL(1) | IOMUX_GPIO_P25_SEL(1);
996
997 mask_pd_c = (1 << HAL_IOMUX_PIN_P2_4) | (1 << HAL_IOMUX_PIN_P2_5);
998 mask_pu = (1 << HAL_IOMUX_PIN_P2_4);
999 mask_pu_c = (1 << HAL_IOMUX_PIN_P2_5);
1000 #elif (UART3_IOMUX_INDEX == 26)
1001 iomux->REG_00C = (iomux->REG_00C & ~(IOMUX_GPIO_P26_SEL_MASK | IOMUX_GPIO_P27_SEL_MASK)) |
1002 IOMUX_GPIO_P26_SEL(1) | IOMUX_GPIO_P27_SEL(1);
1003
1004 mask_pd_c = (1 << HAL_IOMUX_PIN_P2_6) | (1 << HAL_IOMUX_PIN_P2_7);
1005 mask_pu = (1 << HAL_IOMUX_PIN_P2_6);
1006 mask_pu_c = (1 << HAL_IOMUX_PIN_P2_7);
1007 #elif (UART3_IOMUX_INDEX == 34)
1008 iomux->REG_010 = (iomux->REG_010 & ~(IOMUX_GPIO_P34_SEL_MASK | IOMUX_GPIO_P35_SEL_MASK)) |
1009 IOMUX_GPIO_P34_SEL(1) | IOMUX_GPIO_P35_SEL(1);
1010
1011 mask_pd_c = (1 << HAL_IOMUX_PIN_P3_4) | (1 << HAL_IOMUX_PIN_P3_5);
1012 mask_pu = (1 << HAL_IOMUX_PIN_P3_4);
1013 mask_pu_c = (1 << HAL_IOMUX_PIN_P3_5);
1014 #else
1015 #error "Unsupported UART1_IOMUX_INDEX"
1016 #endif
1017 // Setup pullup
1018 iomux->REG_02C |= mask_pu;
1019 iomux->REG_02C &= ~(mask_pu_c);
1020 // Clear pulldown
1021 iomux->REG_030 &= ~mask_pd_c;
1022 }
1023
hal_iomux_set_analog_i2c(void)1024 void hal_iomux_set_analog_i2c(void)
1025 {
1026 uint32_t mask;
1027
1028 // Disable analog I2C master
1029 iomux->REG_050 |= IOMUX_I2C0_M_SEL_GPIO;
1030 // Set mcu GPIO func
1031 iomux->REG_008 = (iomux->REG_008 & ~(IOMUX_GPIO_P16_SEL_MASK | IOMUX_GPIO_P17_SEL_MASK)) |
1032 IOMUX_GPIO_P16_SEL(0xF) | IOMUX_GPIO_P17_SEL(0xF);
1033 // Enable analog I2C slave
1034 iomux->REG_050 &= ~IOMUX_GPIO_I2C_MODE;
1035
1036 mask = (1 << HAL_IOMUX_PIN_P1_6) | (1 << HAL_IOMUX_PIN_P1_7);
1037 // Setup pullup
1038 iomux->REG_02C |= mask;
1039 // Clear pulldown
1040 iomux->REG_030 &= ~mask;
1041 }
1042
hal_iomux_set_jtag(void)1043 void hal_iomux_set_jtag(void)
1044 {
1045 uint32_t mask;
1046 uint32_t val;
1047
1048 // SWCLK/TCK, SWDIO/TMS
1049 mask = IOMUX_GPIO_P01_SEL_MASK | IOMUX_GPIO_P00_SEL_MASK;
1050 val = IOMUX_GPIO_P01_SEL(7) | IOMUX_GPIO_P00_SEL(7);
1051
1052 // TDI, TDO
1053 #ifdef JTAG_TDI_TDO_PIN
1054 mask |= IOMUX_GPIO_P02_SEL_MASK | IOMUX_GPIO_P03_SEL_MASK;
1055 val |= IOMUX_GPIO_P02_SEL(7) | IOMUX_GPIO_P03_SEL(7);
1056 #endif
1057 iomux->REG_004 = (iomux->REG_004 & ~mask) | val;
1058
1059 // RESET
1060 #if defined(JTAG_RESET_PIN) || defined(JTAG_TDI_TDO_PIN)
1061 iomux->REG_004 = (iomux->REG_004 & ~(IOMUX_GPIO_P05_SEL_MASK)) | IOMUX_GPIO_P05_SEL(7);
1062 #endif
1063
1064 mask = (1 << HAL_IOMUX_PIN_P0_1) | (1 << HAL_IOMUX_PIN_P0_0);
1065 #ifdef JTAG_TDI_TDO_PIN
1066 mask |= (1 << HAL_IOMUX_PIN_P0_2) | (1 << HAL_IOMUX_PIN_P0_3);
1067 #endif
1068 #if defined(JTAG_RESET_PIN) || defined(JTAG_TDI_TDO_PIN)
1069 mask |= (1 << HAL_IOMUX_PIN_P0_5);
1070 #endif
1071 // Clear pullup
1072 iomux->REG_02C &= ~mask;
1073 // Clear pulldown
1074 iomux->REG_030 &= ~mask;
1075 }
1076
hal_iomux_ispi_access_enable(enum HAL_IOMUX_ISPI_ACCESS_T access)1077 enum HAL_IOMUX_ISPI_ACCESS_T hal_iomux_ispi_access_enable(enum HAL_IOMUX_ISPI_ACCESS_T access)
1078 {
1079 uint32_t v;
1080
1081 v = iomux->REG_044;
1082 iomux->REG_044 |= access;
1083
1084 return v;
1085 }
1086
hal_iomux_ispi_access_disable(enum HAL_IOMUX_ISPI_ACCESS_T access)1087 enum HAL_IOMUX_ISPI_ACCESS_T hal_iomux_ispi_access_disable(enum HAL_IOMUX_ISPI_ACCESS_T access)
1088 {
1089 uint32_t v;
1090
1091 v = iomux->REG_044;
1092 iomux->REG_044 &= ~access;
1093
1094 return v;
1095 }
1096
hal_iomux_ispi_access_init(void)1097 void hal_iomux_ispi_access_init(void)
1098 {
1099 // Disable bt spi access ana/pmu interface
1100 hal_iomux_ispi_access_disable(HAL_IOMUX_ISPI_BT_ANA | HAL_IOMUX_ISPI_BT_PMU);
1101 }
1102
hal_iomux_set_i2s0(void)1103 void hal_iomux_set_i2s0(void)
1104 {
1105 static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_i2s[] = {
1106 {HAL_IOMUX_PIN_P0_2, HAL_IOMUX_FUNC_I2S0_WS, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1107 {HAL_IOMUX_PIN_P0_3, HAL_IOMUX_FUNC_I2S0_SCK, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1108 #if (I2S0_I_IOMUX_INDEX == 00)
1109 {HAL_IOMUX_PIN_P0_0, HAL_IOMUX_FUNC_I2S0_SDI0, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1110 #elif (I2S0_I_IOMUX_INDEX == 13)
1111 {HAL_IOMUX_PIN_P1_3, HAL_IOMUX_FUNC_I2S0_SDI0, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1112 #elif (I2S0_I_IOMUX_INDEX == 37)
1113 {HAL_IOMUX_PIN_P3_7, HAL_IOMUX_FUNC_I2S0_SDI0, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1114 #else
1115 #error "Unsupported I2S0_I_IOMUX_INDEX"
1116 #endif
1117 #if (I2S0_I1_IOMUX_INDEX == 12)
1118 {HAL_IOMUX_PIN_P1_2, HAL_IOMUX_FUNC_I2S0_SDI1, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1119 #elif (I2S0_I1_IOMUX_INDEX == 36)
1120 {HAL_IOMUX_PIN_P3_6, HAL_IOMUX_FUNC_I2S0_SDI1, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1121 #endif
1122 #if (I2S0_I2_IOMUX_INDEX == 11)
1123 {HAL_IOMUX_PIN_P1_1, HAL_IOMUX_FUNC_I2S0_SDI2, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1124 #elif (I2S0_I2_IOMUX_INDEX == 35)
1125 {HAL_IOMUX_PIN_P3_5, HAL_IOMUX_FUNC_I2S0_SDI2, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1126 #endif
1127 #if (I2S0_I3_IOMUX_INDEX == 10)
1128 {HAL_IOMUX_PIN_P1_0, HAL_IOMUX_FUNC_I2S0_SDI3, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1129 #elif (I2S0_I3_IOMUX_INDEX == 34)
1130 {HAL_IOMUX_PIN_P3_4, HAL_IOMUX_FUNC_I2S0_SDI3, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1131 #endif
1132
1133 #if (I2S0_O_IOMUX_INDEX == 01)
1134 {HAL_IOMUX_PIN_P0_1, HAL_IOMUX_FUNC_I2S0_SDO0, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1135 #elif (I2S0_O_IOMUX_INDEX == 07)
1136 {HAL_IOMUX_PIN_P0_7, HAL_IOMUX_FUNC_I2S0_SDO0, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1137 #else
1138 #error "Unsupported I2S0_O_IOMUX_INDEX"
1139 #endif
1140 #if (I2S0_O1_IOMUX_INDEX == 06)
1141 {HAL_IOMUX_PIN_P0_6, HAL_IOMUX_FUNC_I2S0_SDO1, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1142 #endif
1143 #if (I2S0_O2_IOMUX_INDEX == 05)
1144 {HAL_IOMUX_PIN_P0_5, HAL_IOMUX_FUNC_I2S0_SDO2, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1145 #endif
1146 #if (I2S0_O3_IOMUX_INDEX == 04)
1147 {HAL_IOMUX_PIN_P0_4, HAL_IOMUX_FUNC_I2S0_SDO3, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1148 #endif
1149 };
1150
1151 hal_iomux_init(pinmux_i2s, ARRAY_SIZE(pinmux_i2s));
1152 }
1153
hal_iomux_set_i2s1(void)1154 void hal_iomux_set_i2s1(void)
1155 {
1156 static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_i2s[] = {
1157 {HAL_IOMUX_PIN_P2_2, HAL_IOMUX_FUNC_I2S1_WS, I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1158 {HAL_IOMUX_PIN_P2_3, HAL_IOMUX_FUNC_I2S1_SCK, I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1159 #if (I2S1_I_IOMUX_INDEX == 20)
1160 {HAL_IOMUX_PIN_P2_0, HAL_IOMUX_FUNC_I2S1_SDI0, I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1161 #elif (I2S1_I_IOMUX_INDEX == 33)
1162 {HAL_IOMUX_PIN_P3_3, HAL_IOMUX_FUNC_I2S1_SDI0, I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1163 #else
1164 #error "Unsupported I2S1_I_IOMUX_INDEX"
1165 #endif
1166 #if (I2S1_I1_IOMUX_INDEX == 32)
1167 {HAL_IOMUX_PIN_P3_2, HAL_IOMUX_FUNC_I2S1_SDI1, I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1168 #endif
1169 #if (I2S1_I2_IOMUX_INDEX == 31)
1170 {HAL_IOMUX_PIN_P3_1, HAL_IOMUX_FUNC_I2S1_SDI2, I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1171 #endif
1172 #if (I2S1_I3_IOMUX_INDEX == 30)
1173 {HAL_IOMUX_PIN_P3_0, HAL_IOMUX_FUNC_I2S1_SDI3, I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1174 #endif
1175
1176 #if (I2S1_O_IOMUX_INDEX == 21)
1177 {HAL_IOMUX_PIN_P2_1, HAL_IOMUX_FUNC_I2S1_SDO0, I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1178 #elif (I2S1_O_IOMUX_INDEX == 27)
1179 {HAL_IOMUX_PIN_P2_7, HAL_IOMUX_FUNC_I2S1_SDO0, I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1180 #else
1181 #error "Unsupported I2S1_O_IOMUX_INDEX"
1182 #endif
1183 #if (I2S1_O1_IOMUX_INDEX == 26)
1184 {HAL_IOMUX_PIN_P2_6, HAL_IOMUX_FUNC_I2S1_SDO1, I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1185 #endif
1186 #if (I2S1_O2_IOMUX_INDEX == 25)
1187 {HAL_IOMUX_PIN_P2_5, HAL_IOMUX_FUNC_I2S1_SDO2, I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1188 #endif
1189 #if (I2S1_O3_IOMUX_INDEX == 24)
1190 {HAL_IOMUX_PIN_P2_4, HAL_IOMUX_FUNC_I2S1_SDO3, I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1191 #endif
1192 };
1193
1194 hal_iomux_init(pinmux_i2s, ARRAY_SIZE(pinmux_i2s));
1195 }
1196
hal_iomux_set_i2s_mclk(void)1197 void hal_iomux_set_i2s_mclk(void)
1198 {
1199 static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux[] = {
1200 #if (I2S_MCLK_IOMUX_INDEX == 04)
1201 {HAL_IOMUX_PIN_P0_4, HAL_IOMUX_FUNC_I2S_MCLK, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1202 #elif (I2S_MCLK_IOMUX_INDEX == 13)
1203 {HAL_IOMUX_PIN_P1_3, HAL_IOMUX_FUNC_I2S_MCLK, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1204 #elif (I2S_MCLK_IOMUX_INDEX == 15)
1205 {HAL_IOMUX_PIN_P1_5, HAL_IOMUX_FUNC_I2S_MCLK, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1206 #elif (I2S_MCLK_IOMUX_INDEX == 20)
1207 {HAL_IOMUX_PIN_P2_0, HAL_IOMUX_FUNC_I2S_MCLK, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1208 #elif (I2S_MCLK_IOMUX_INDEX == 22)
1209 {HAL_IOMUX_PIN_P2_2, HAL_IOMUX_FUNC_I2S_MCLK, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1210 #elif (I2S_MCLK_IOMUX_INDEX == 27)
1211 {HAL_IOMUX_PIN_P2_7, HAL_IOMUX_FUNC_I2S_MCLK, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1212 #elif (I2S_MCLK_IOMUX_INDEX == 34)
1213 {HAL_IOMUX_PIN_P3_4, HAL_IOMUX_FUNC_I2S_MCLK, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1214 #else
1215 #error "Unsupported I2S_MCLK_IOMUX_INDEX"
1216 #endif
1217 };
1218
1219 hal_iomux_init(pinmux, ARRAY_SIZE(pinmux));
1220 }
1221
hal_iomux_set_spdif0(void)1222 void hal_iomux_set_spdif0(void)
1223 {
1224 static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_spdif[] = {
1225 #if (SPDIF0_I_IOMUX_INDEX == 02)
1226 {HAL_IOMUX_PIN_P0_2, HAL_IOMUX_FUNC_SPDIF0_DI, SPDIF0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1227 #elif (SPDIF0_I_IOMUX_INDEX == 10)
1228 {HAL_IOMUX_PIN_P1_0, HAL_IOMUX_FUNC_SPDIF0_DI, SPDIF0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1229 #elif (SPDIF0_I_IOMUX_INDEX == 20)
1230 {HAL_IOMUX_PIN_P2_0, HAL_IOMUX_FUNC_SPDIF0_DI, SPDIF0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1231 #elif (SPDIF0_I_IOMUX_INDEX == 26)
1232 {HAL_IOMUX_PIN_P2_6, HAL_IOMUX_FUNC_SPDIF0_DI, SPDIF0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1233 #elif (SPDIF0_I_IOMUX_INDEX == 37)
1234 {HAL_IOMUX_PIN_P3_7, HAL_IOMUX_FUNC_SPDIF0_DI, SPDIF0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1235 #elif (SPDIF0_I_IOMUX_INDEX == 24)
1236 {HAL_IOMUX_PIN_P2_4, HAL_IOMUX_FUNC_SPDIF0_DI, SPDIF0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1237 #else
1238 #error "Unsupported SPDIF0_I_IOMUX_INDEX"
1239 #endif
1240
1241 #if (SPDIF0_O_IOMUX_INDEX == 03)
1242 {HAL_IOMUX_PIN_P0_3, HAL_IOMUX_FUNC_SPDIF0_DO, SPDIF0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1243 #elif (SPDIF0_O_IOMUX_INDEX == 11)
1244 {HAL_IOMUX_PIN_P1_1, HAL_IOMUX_FUNC_SPDIF0_DO, SPDIF0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1245 #elif (SPDIF0_O_IOMUX_INDEX == 21)
1246 {HAL_IOMUX_PIN_P2_1, HAL_IOMUX_FUNC_SPDIF0_DO, SPDIF0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1247 #elif (SPDIF0_O_IOMUX_INDEX == 27)
1248 {HAL_IOMUX_PIN_P2_7, HAL_IOMUX_FUNC_SPDIF0_DO, SPDIF0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1249 #elif (SPDIF0_O_IOMUX_INDEX == 37)
1250 {HAL_IOMUX_PIN_P3_7, HAL_IOMUX_FUNC_SPDIF0_DO, SPDIF0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1251 #elif (SPDIF0_O_IOMUX_INDEX == 07)
1252 {HAL_IOMUX_PIN_P0_7, HAL_IOMUX_FUNC_SPDIF0_DO, SPDIF0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1253 #else
1254 #error "Unsupported SPDIF0_O_IOMUX_INDEX"
1255 #endif
1256 };
1257 hal_iomux_init(pinmux_spdif, ARRAY_SIZE(pinmux_spdif));
1258 }
1259
1260
hal_iomux_set_dig_mic(uint32_t map)1261 void hal_iomux_set_dig_mic(uint32_t map)
1262 {
1263 struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_digitalmic_clk[] = {
1264 {HAL_IOMUX_PIN_P0_0, HAL_IOMUX_FUNC_PDM0_CK, DIGMIC_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1265 };
1266 struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_digitalmic0[] = {
1267 {HAL_IOMUX_PIN_P0_1, HAL_IOMUX_FUNC_PDM0_D, DIGMIC_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1268 };
1269 struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_digitalmic1[] = {
1270 {HAL_IOMUX_PIN_P0_2, HAL_IOMUX_FUNC_PDM1_D, DIGMIC_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1271 };
1272 struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_digitalmic2[] = {
1273 {HAL_IOMUX_PIN_P0_3, HAL_IOMUX_FUNC_PDM2_D, DIGMIC_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1274 };
1275
1276 if (digmic_ck_pin == HAL_IOMUX_PIN_P0_0) {
1277 pinmux_digitalmic_clk[0].pin = HAL_IOMUX_PIN_P0_0;
1278 pinmux_digitalmic_clk[0].function = HAL_IOMUX_FUNC_PDM0_CK;
1279 } else if (digmic_ck_pin == HAL_IOMUX_PIN_P0_4) {
1280 pinmux_digitalmic_clk[0].pin = HAL_IOMUX_PIN_P0_4;
1281 pinmux_digitalmic_clk[0].function = HAL_IOMUX_FUNC_PDM1_CK;
1282 } else if (digmic_ck_pin == HAL_IOMUX_PIN_P3_3) {
1283 pinmux_digitalmic_clk[0].pin = HAL_IOMUX_PIN_P3_3;
1284 pinmux_digitalmic_clk[0].function = HAL_IOMUX_FUNC_PDM2_CK;
1285 } else if (digmic_ck_pin == HAL_IOMUX_PIN_P3_4) {
1286 pinmux_digitalmic_clk[0].pin = HAL_IOMUX_PIN_P3_4;
1287 pinmux_digitalmic_clk[0].function = HAL_IOMUX_FUNC_PDM0_CK;
1288 }
1289
1290 if (digmic_d0_pin == HAL_IOMUX_PIN_P0_1) {
1291 pinmux_digitalmic0[0].pin = HAL_IOMUX_PIN_P0_1;
1292 } else if (digmic_d0_pin == HAL_IOMUX_PIN_P0_5) {
1293 pinmux_digitalmic0[0].pin = HAL_IOMUX_PIN_P0_5;
1294 } else if (digmic_d0_pin == HAL_IOMUX_PIN_P3_0) {
1295 pinmux_digitalmic0[0].pin = HAL_IOMUX_PIN_P3_0;
1296 } else if (digmic_d0_pin == HAL_IOMUX_PIN_P3_5) {
1297 pinmux_digitalmic0[0].pin = HAL_IOMUX_PIN_P3_5;
1298 }
1299
1300 if (digmic_d1_pin == HAL_IOMUX_PIN_P0_2) {
1301 pinmux_digitalmic1[0].pin = HAL_IOMUX_PIN_P0_2;
1302 } else if (digmic_d1_pin == HAL_IOMUX_PIN_P0_6) {
1303 pinmux_digitalmic1[0].pin = HAL_IOMUX_PIN_P0_6;
1304 } else if (digmic_d1_pin == HAL_IOMUX_PIN_P3_1) {
1305 pinmux_digitalmic1[0].pin = HAL_IOMUX_PIN_P3_1;
1306 } else if (digmic_d1_pin == HAL_IOMUX_PIN_P3_6) {
1307 pinmux_digitalmic1[0].pin = HAL_IOMUX_PIN_P3_6;
1308 }
1309
1310 if (digmic_d2_pin == HAL_IOMUX_PIN_P0_3) {
1311 pinmux_digitalmic2[0].pin = HAL_IOMUX_PIN_P0_3;
1312 } else if (digmic_d2_pin == HAL_IOMUX_PIN_P0_7) {
1313 pinmux_digitalmic2[0].pin = HAL_IOMUX_PIN_P0_7;
1314 } else if (digmic_d2_pin == HAL_IOMUX_PIN_P3_2) {
1315 pinmux_digitalmic2[0].pin = HAL_IOMUX_PIN_P3_2;
1316 } else if (digmic_d2_pin == HAL_IOMUX_PIN_P3_7) {
1317 pinmux_digitalmic2[0].pin = HAL_IOMUX_PIN_P3_7;
1318 }
1319
1320 if ((map & 0xF) == 0) {
1321 pinmux_digitalmic_clk[0].function = HAL_IOMUX_FUNC_GPIO;
1322 }
1323 hal_iomux_init(pinmux_digitalmic_clk, ARRAY_SIZE(pinmux_digitalmic_clk));
1324 if (map & (1 << 0)) {
1325 hal_iomux_init(pinmux_digitalmic0, ARRAY_SIZE(pinmux_digitalmic0));
1326 }
1327 if (map & (1 << 1)) {
1328 hal_iomux_init(pinmux_digitalmic1, ARRAY_SIZE(pinmux_digitalmic1));
1329 }
1330 if (map & (1 << 2)) {
1331 hal_iomux_init(pinmux_digitalmic2, ARRAY_SIZE(pinmux_digitalmic2));
1332 }
1333 }
1334
hal_iomux_set_spi(void)1335 void hal_iomux_set_spi(void)
1336 {
1337 static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_spi[] = {
1338 #if (SPI_IOMUX_INDEX == 04)
1339 #ifdef SPI_IOMUX_4WIRE
1340 {HAL_IOMUX_PIN_P0_4, HAL_IOMUX_FUNC_SPI_DI0, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1341 #endif
1342 {HAL_IOMUX_PIN_P0_5, HAL_IOMUX_FUNC_SPI_CLK, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1343 {HAL_IOMUX_PIN_P0_6, HAL_IOMUX_FUNC_SPI_CS0, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1344 {HAL_IOMUX_PIN_P0_7, HAL_IOMUX_FUNC_SPI_DIO, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1345
1346 #elif (SPI_IOMUX_INDEX == 24)
1347 #ifdef SPI_IOMUX_4WIRE
1348 {HAL_IOMUX_PIN_P2_4, HAL_IOMUX_FUNC_SPI_DI0, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1349 #endif
1350 {HAL_IOMUX_PIN_P2_7, HAL_IOMUX_FUNC_SPI_CLK, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1351 {HAL_IOMUX_PIN_P2_6, HAL_IOMUX_FUNC_SPI_CS0, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1352 {HAL_IOMUX_PIN_P2_5, HAL_IOMUX_FUNC_SPI_DIO, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1353
1354 #elif (SPI_IOMUX_INDEX == 30)
1355 #ifdef SPI_IOMUX_4WIRE
1356 {HAL_IOMUX_PIN_P3_0, HAL_IOMUX_FUNC_SPI_DI0, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1357 #endif
1358 {HAL_IOMUX_PIN_P3_3, HAL_IOMUX_FUNC_SPI_CLK, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1359 {HAL_IOMUX_PIN_P3_2, HAL_IOMUX_FUNC_SPI_CS0, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1360 {HAL_IOMUX_PIN_P3_1, HAL_IOMUX_FUNC_SPI_DIO, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1361 #else
1362 #error "Unsupported SPI_IOMUX_INDEX"
1363 #endif
1364
1365 #if (SPI_IOMUX_CS1_INDEX == 10)
1366 {HAL_IOMUX_PIN_P1_0, HAL_IOMUX_FUNC_SPI_CS1, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1367 #elif (SPI_IOMUX_CS1_INDEX == 35)
1368 {HAL_IOMUX_PIN_P3_5, HAL_IOMUX_FUNC_SPI_CS1, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1369 #endif
1370 #if (SPI_IOMUX_CS2_INDEX == 11)
1371 {HAL_IOMUX_PIN_P1_1, HAL_IOMUX_FUNC_SPI_CS2, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1372 #elif (SPI_IOMUX_CS2_INDEX == 37)
1373 {HAL_IOMUX_PIN_P3_7, HAL_IOMUX_FUNC_SPI_CS2, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1374 #endif
1375 #if (SPI_IOMUX_CS3_INDEX == 12)
1376 {HAL_IOMUX_PIN_P1_2, HAL_IOMUX_FUNC_SPI_CS3, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1377 #elif (SPI_IOMUX_CS3_INDEX == 25)
1378 {HAL_IOMUX_PIN_P2_5, HAL_IOMUX_FUNC_SPI_CS3, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1379 #endif
1380
1381 #ifdef SPI_IOMUX_4WIRE
1382 #if (SPI_IOMUX_DI1_INDEX == 13)
1383 {HAL_IOMUX_PIN_P1_3, HAL_IOMUX_FUNC_SPI_DI1, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1384 #elif (SPI_IOMUX_DI1_INDEX == 34)
1385 {HAL_IOMUX_PIN_P3_4, HAL_IOMUX_FUNC_SPI_DI1, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1386 #endif
1387 #if (SPI_IOMUX_DI2_INDEX == 14)
1388 {HAL_IOMUX_PIN_P1_4, HAL_IOMUX_FUNC_SPI_DI2, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1389 #elif (SPI_IOMUX_DI2_INDEX == 36)
1390 {HAL_IOMUX_PIN_P3_6, HAL_IOMUX_FUNC_SPI_DI2, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1391 #endif
1392 #if (SPI_IOMUX_DI3_INDEX == 15)
1393 {HAL_IOMUX_PIN_P1_5, HAL_IOMUX_FUNC_SPI_DI3, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1394 #elif (SPI_IOMUX_DI3_INDEX == 24)
1395 {HAL_IOMUX_PIN_P2_4, HAL_IOMUX_FUNC_SPI_DI3, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1396 #endif
1397 #endif
1398 };
1399
1400 hal_iomux_init(pinmux_spi, ARRAY_SIZE(pinmux_spi));
1401 }
1402
hal_iomux_set_spilcd_slave(void)1403 void hal_iomux_set_spilcd_slave(void)
1404 {
1405 iomux->REG_050 |= IOMUX_SPILCD1_MASTER_N;
1406 }
1407
hal_iomux_set_spilcd(void)1408 void hal_iomux_set_spilcd(void)
1409 {
1410 static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_spilcd[] = {
1411 #if (SPILCD_IOMUX_INDEX == 00)
1412 #ifdef SPILCD_IOMUX_4WIRE
1413 {HAL_IOMUX_PIN_P0_0, HAL_IOMUX_FUNC_SPILCD_DI0, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1414 #endif
1415 {HAL_IOMUX_PIN_P0_3, HAL_IOMUX_FUNC_SPILCD_CLK, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1416 {HAL_IOMUX_PIN_P0_2, HAL_IOMUX_FUNC_SPILCD_CS0, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1417 {HAL_IOMUX_PIN_P0_1, HAL_IOMUX_FUNC_SPILCD_DIO, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1418
1419 #elif (SPILCD_IOMUX_INDEX == 10)
1420 #ifdef SPILCD_IOMUX_4WIRE
1421 {HAL_IOMUX_PIN_P1_4, HAL_IOMUX_FUNC_SPILCD_DI0, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1422 #endif
1423 {HAL_IOMUX_PIN_P1_0, HAL_IOMUX_FUNC_SPILCD_CLK, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1424 {HAL_IOMUX_PIN_P1_1, HAL_IOMUX_FUNC_SPILCD_CS0, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1425 {HAL_IOMUX_PIN_P1_5, HAL_IOMUX_FUNC_SPILCD_DIO, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1426
1427 #elif (SPILCD_IOMUX_INDEX == 20)
1428 #ifdef SPILCD_IOMUX_4WIRE
1429 {HAL_IOMUX_PIN_P2_0, HAL_IOMUX_FUNC_SPILCD_DI0, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1430 #endif
1431 {HAL_IOMUX_PIN_P2_3, HAL_IOMUX_FUNC_SPILCD_CLK, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1432 {HAL_IOMUX_PIN_P2_2, HAL_IOMUX_FUNC_SPILCD_CS0, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1433 {HAL_IOMUX_PIN_P2_1, HAL_IOMUX_FUNC_SPILCD_DIO, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1434
1435 #elif (SPILCD_IOMUX_INDEX == 34)
1436 #ifdef SPILCD_IOMUX_4WIRE
1437 {HAL_IOMUX_PIN_P3_4, HAL_IOMUX_FUNC_SPILCD_DI0, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1438 #endif
1439 {HAL_IOMUX_PIN_P3_7, HAL_IOMUX_FUNC_SPILCD_CLK, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1440 {HAL_IOMUX_PIN_P3_6, HAL_IOMUX_FUNC_SPILCD_CS0, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1441 {HAL_IOMUX_PIN_P3_5, HAL_IOMUX_FUNC_SPILCD_DIO, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1442 #else
1443 #error "Unsupported SPILCD_IOMUX_INDEX"
1444 #endif
1445
1446 #if (SPILCD_IOMUX_CS1_INDEX == 05)
1447 {HAL_IOMUX_PIN_P0_5, HAL_IOMUX_FUNC_SPILCD_CS1, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1448 #elif (SPILCD_IOMUX_CS1_INDEX == 12)
1449 {HAL_IOMUX_PIN_P1_2, HAL_IOMUX_FUNC_SPILCD_CS1, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1450 #elif (SPILCD_IOMUX_CS1_INDEX == 27)
1451 {HAL_IOMUX_PIN_P2_7, HAL_IOMUX_FUNC_SPILCD_CS1, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1452 #endif
1453 #if (SPILCD_IOMUX_CS2_INDEX == 06)
1454 {HAL_IOMUX_PIN_P0_6, HAL_IOMUX_FUNC_SPILCD_CS2, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1455 #elif (SPILCD_IOMUX_CS2_INDEX == 31)
1456 {HAL_IOMUX_PIN_P3_1, HAL_IOMUX_FUNC_SPILCD_CS2, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1457 #endif
1458 #if (SPILCD_IOMUX_CS3_INDEX == 07)
1459 {HAL_IOMUX_PIN_P0_7, HAL_IOMUX_FUNC_SPILCD_CS3, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1460 #elif (SPILCD_IOMUX_CS3_INDEX == 32)
1461 {HAL_IOMUX_PIN_P3_2, HAL_IOMUX_FUNC_SPILCD_CS3, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1462 #endif
1463
1464 #ifdef SPILCD_IOMUX_4WIRE
1465 #if (SPILCD_IOMUX_DI1_INDEX == 02)
1466 {HAL_IOMUX_PIN_P0_2, HAL_IOMUX_FUNC_SPILCD_DI1, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1467 #elif (SPILCD_IOMUX_DI1_INDEX == 26)
1468 {HAL_IOMUX_PIN_P2_6, HAL_IOMUX_FUNC_SPILCD_DI1, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1469 #endif
1470 #if (SPILCD_IOMUX_DI2_INDEX == 03)
1471 {HAL_IOMUX_PIN_P0_3, HAL_IOMUX_FUNC_SPILCD_DI2, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1472 #elif (SPILCD_IOMUX_DI2_INDEX == 30)
1473 {HAL_IOMUX_PIN_P3_0, HAL_IOMUX_FUNC_SPILCD_DI2, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1474 #endif
1475 #if (SPILCD_IOMUX_DI3_INDEX == 04)
1476 {HAL_IOMUX_PIN_P0_4, HAL_IOMUX_FUNC_SPILCD_DI3, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1477 #elif (SPILCD_IOMUX_DI3_INDEX == 33)
1478 {HAL_IOMUX_PIN_P3_3, HAL_IOMUX_FUNC_SPILCD_DI3, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1479 #endif
1480 #endif
1481 };
1482
1483 hal_iomux_init(pinmux_spilcd, ARRAY_SIZE(pinmux_spilcd));
1484 }
1485
hal_iomux_set_i2c0(void)1486 void hal_iomux_set_i2c0(void)
1487 {
1488 static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_i2c[] = {
1489 #if (I2C0_IOMUX_INDEX == 00)
1490 {HAL_IOMUX_PIN_P0_0, HAL_IOMUX_FUNC_I2C_M0_SCL, I2C0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1491 {HAL_IOMUX_PIN_P0_1, HAL_IOMUX_FUNC_I2C_M0_SDA, I2C0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1492 #elif (I2C0_IOMUX_INDEX == 04)
1493 {HAL_IOMUX_PIN_P0_4, HAL_IOMUX_FUNC_I2C_M0_SCL, I2C0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1494 {HAL_IOMUX_PIN_P0_5, HAL_IOMUX_FUNC_I2C_M0_SDA, I2C0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1495 #elif (I2C0_IOMUX_INDEX == 16)
1496 {HAL_IOMUX_PIN_P1_6, HAL_IOMUX_FUNC_I2C_M0_SCL, I2C0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1497 {HAL_IOMUX_PIN_P1_7, HAL_IOMUX_FUNC_I2C_M0_SDA, I2C0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1498 #elif (I2C0_IOMUX_INDEX == 20)
1499 {HAL_IOMUX_PIN_P2_0, HAL_IOMUX_FUNC_I2C_M0_SCL, I2C0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1500 {HAL_IOMUX_PIN_P2_1, HAL_IOMUX_FUNC_I2C_M0_SDA, I2C0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1501 #elif (I2C0_IOMUX_INDEX == 26)
1502 {HAL_IOMUX_PIN_P2_6, HAL_IOMUX_FUNC_I2C_M0_SCL, I2C0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1503 {HAL_IOMUX_PIN_P2_7, HAL_IOMUX_FUNC_I2C_M0_SDA, I2C0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1504 #elif (I2C0_IOMUX_INDEX == 34)
1505 {HAL_IOMUX_PIN_P3_4, HAL_IOMUX_FUNC_I2C_M0_SCL, I2C0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1506 {HAL_IOMUX_PIN_P3_5, HAL_IOMUX_FUNC_I2C_M0_SDA, I2C0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1507 #else
1508 #error "Unsupported I2C0_IOMUX_INDEX"
1509 #endif
1510 };
1511 hal_iomux_init(pinmux_i2c, ARRAY_SIZE(pinmux_i2c));
1512 iomux->REG_050 |= IOMUX_I2C0_M_SEL_GPIO;
1513 }
1514
hal_iomux_set_i2c1(void)1515 void hal_iomux_set_i2c1(void)
1516 {
1517 static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_i2c[] = {
1518 #if (I2C1_IOMUX_INDEX == 02)
1519 {HAL_IOMUX_PIN_P0_2, HAL_IOMUX_FUNC_I2C_M1_SCL, I2C1_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1520 {HAL_IOMUX_PIN_P0_3, HAL_IOMUX_FUNC_I2C_M1_SDA, I2C1_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1521 #elif (I2C1_IOMUX_INDEX == 06)
1522 {HAL_IOMUX_PIN_P0_6, HAL_IOMUX_FUNC_I2C_M1_SCL, I2C1_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1523 {HAL_IOMUX_PIN_P0_7, HAL_IOMUX_FUNC_I2C_M1_SDA, I2C1_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1524 #elif (I2C1_IOMUX_INDEX == 14)
1525 {HAL_IOMUX_PIN_P1_4, HAL_IOMUX_FUNC_I2C_M1_SCL, I2C1_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1526 {HAL_IOMUX_PIN_P1_5, HAL_IOMUX_FUNC_I2C_M1_SDA, I2C1_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1527 #elif (I2C1_IOMUX_INDEX == 22)
1528 {HAL_IOMUX_PIN_P2_2, HAL_IOMUX_FUNC_I2C_M1_SCL, I2C1_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1529 {HAL_IOMUX_PIN_P2_3, HAL_IOMUX_FUNC_I2C_M1_SDA, I2C1_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1530 #elif (I2C1_IOMUX_INDEX == 30)
1531 {HAL_IOMUX_PIN_P3_0, HAL_IOMUX_FUNC_I2C_M1_SCL, I2C1_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1532 {HAL_IOMUX_PIN_P3_1, HAL_IOMUX_FUNC_I2C_M1_SDA, I2C1_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1533 #else
1534 #error "Unsupported I2C1_IOMUX_INDEX"
1535 #endif
1536 };
1537 hal_iomux_init(pinmux_i2c, ARRAY_SIZE(pinmux_i2c));
1538 iomux->REG_050 |= IOMUX_I2C1_M_SEL_GPIO;
1539 }
1540
hal_iomux_set_i2c2(void)1541 void hal_iomux_set_i2c2(void)
1542 {
1543 static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_i2c[] = {
1544 #if (I2C2_IOMUX_INDEX == 10)
1545 {HAL_IOMUX_PIN_P1_0, HAL_IOMUX_FUNC_I2C_M2_SCL, I2C2_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1546 {HAL_IOMUX_PIN_P1_1, HAL_IOMUX_FUNC_I2C_M2_SDA, I2C2_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1547 #elif (I2C2_IOMUX_INDEX == 12)
1548 {HAL_IOMUX_PIN_P1_2, HAL_IOMUX_FUNC_I2C_M2_SCL, I2C2_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1549 {HAL_IOMUX_PIN_P1_3, HAL_IOMUX_FUNC_I2C_M2_SDA, I2C2_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1550 #elif (I2C2_IOMUX_INDEX == 24)
1551 {HAL_IOMUX_PIN_P2_4, HAL_IOMUX_FUNC_I2C_M2_SCL, I2C2_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1552 {HAL_IOMUX_PIN_P2_5, HAL_IOMUX_FUNC_I2C_M2_SDA, I2C2_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1553 #elif (I2C2_IOMUX_INDEX == 32)
1554 {HAL_IOMUX_PIN_P3_2, HAL_IOMUX_FUNC_I2C_M2_SCL, I2C2_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1555 {HAL_IOMUX_PIN_P3_3, HAL_IOMUX_FUNC_I2C_M2_SDA, I2C2_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1556 #elif (I2C2_IOMUX_INDEX == 36)
1557 {HAL_IOMUX_PIN_P3_6, HAL_IOMUX_FUNC_I2C_M2_SCL, I2C2_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1558 {HAL_IOMUX_PIN_P3_7, HAL_IOMUX_FUNC_I2C_M2_SDA, I2C2_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1559 #else
1560 #error "Unsupported I2C2_IOMUX_INDEX"
1561 #endif
1562 };
1563 hal_iomux_init(pinmux_i2c, ARRAY_SIZE(pinmux_i2c));
1564 iomux->REG_050 |= IOMUX_I2C2_M_SEL_GPIO;
1565 }
1566
hal_iomux_set_pwm0(void)1567 void hal_iomux_set_pwm0(void)
1568 {
1569 static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_pwm[] = {
1570 #if (PWM0_IOMUX_INDEX == 00)
1571 {HAL_IOMUX_PIN_P0_0, HAL_IOMUX_FUNC_PWM0, PWM0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1572 #elif (PWM0_IOMUX_INDEX == 10)
1573 {HAL_IOMUX_PIN_P1_0, HAL_IOMUX_FUNC_PWM0, PWM0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1574 #elif (PWM0_IOMUX_INDEX == 20)
1575 {HAL_IOMUX_PIN_P2_0, HAL_IOMUX_FUNC_PWM0, PWM0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1576 #elif (PWM0_IOMUX_INDEX == 30)
1577 {HAL_IOMUX_PIN_P3_0, HAL_IOMUX_FUNC_PWM0, PWM0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1578 #else
1579 #error "Unsupported PWM0_IOMUX_INDEX"
1580 #endif
1581 };
1582 hal_iomux_init(pinmux_pwm, ARRAY_SIZE(pinmux_pwm));
1583 }
1584
hal_iomux_set_pwm1(void)1585 void hal_iomux_set_pwm1(void)
1586 {
1587 static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_pwm[] = {
1588 #if (PWM1_IOMUX_INDEX == 01)
1589 {HAL_IOMUX_PIN_P0_1, HAL_IOMUX_FUNC_PWM1, PWM1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1590 #elif (PWM1_IOMUX_INDEX == 11)
1591 {HAL_IOMUX_PIN_P1_1, HAL_IOMUX_FUNC_PWM1, PWM1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1592 #elif (PWM1_IOMUX_INDEX == 21)
1593 {HAL_IOMUX_PIN_P2_1, HAL_IOMUX_FUNC_PWM1, PWM1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1594 #elif (PWM1_IOMUX_INDEX == 31)
1595 {HAL_IOMUX_PIN_P3_1, HAL_IOMUX_FUNC_PWM1, PWM1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1596 #else
1597 #error "Unsupported PWM1_IOMUX_INDEX"
1598 #endif
1599 };
1600 hal_iomux_init(pinmux_pwm, ARRAY_SIZE(pinmux_pwm));
1601 }
1602
hal_iomux_set_pwm2(void)1603 void hal_iomux_set_pwm2(void)
1604 {
1605 static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_pwm[] = {
1606 #if (PWM2_IOMUX_INDEX == 02)
1607 {HAL_IOMUX_PIN_P0_2, HAL_IOMUX_FUNC_PWM2, PWM2_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1608 #elif (PWM2_IOMUX_INDEX == 12)
1609 {HAL_IOMUX_PIN_P1_2, HAL_IOMUX_FUNC_PWM2, PWM2_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1610 #elif (PWM2_IOMUX_INDEX == 22)
1611 {HAL_IOMUX_PIN_P2_2, HAL_IOMUX_FUNC_PWM2, PWM2_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1612 #elif (PWM2_IOMUX_INDEX == 32)
1613 {HAL_IOMUX_PIN_P3_2, HAL_IOMUX_FUNC_PWM2, PWM2_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1614 #else
1615 #error "Unsupported PWM2_IOMUX_INDEX"
1616 #endif
1617 };
1618 hal_iomux_init(pinmux_pwm, ARRAY_SIZE(pinmux_pwm));
1619 }
1620
hal_iomux_set_pwm3(void)1621 void hal_iomux_set_pwm3(void)
1622 {
1623 static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_pwm[] = {
1624 #if (PWM3_IOMUX_INDEX == 03)
1625 {HAL_IOMUX_PIN_P0_3, HAL_IOMUX_FUNC_PWM3, PWM3_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1626 #elif (PWM3_IOMUX_INDEX == 13)
1627 {HAL_IOMUX_PIN_P1_3, HAL_IOMUX_FUNC_PWM3, PWM3_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1628 #elif (PWM3_IOMUX_INDEX == 23)
1629 {HAL_IOMUX_PIN_P2_3, HAL_IOMUX_FUNC_PWM3, PWM3_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1630 #elif (PWM3_IOMUX_INDEX == 33)
1631 {HAL_IOMUX_PIN_P3_3, HAL_IOMUX_FUNC_PWM3, PWM3_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1632 #else
1633 #error "Unsupported PWM3_IOMUX_INDEX"
1634 #endif
1635 };
1636 hal_iomux_init(pinmux_pwm, ARRAY_SIZE(pinmux_pwm));
1637 }
1638
hal_iomux_set_pwm4(void)1639 void hal_iomux_set_pwm4(void)
1640 {
1641 static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_pwm[] = {
1642 #if (PWM4_IOMUX_INDEX == 04)
1643 {HAL_IOMUX_PIN_P0_4, HAL_IOMUX_FUNC_PWM4, PWM4_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1644 #elif (PWM4_IOMUX_INDEX == 14)
1645 {HAL_IOMUX_PIN_P1_4, HAL_IOMUX_FUNC_PWM4, PWM4_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1646 #elif (PWM4_IOMUX_INDEX == 24)
1647 {HAL_IOMUX_PIN_P2_4, HAL_IOMUX_FUNC_PWM4, PWM4_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1648 #elif (PWM4_IOMUX_INDEX == 34)
1649 {HAL_IOMUX_PIN_P3_4, HAL_IOMUX_FUNC_PWM4, PWM4_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1650 #else
1651 #error "Unsupported PWM4_IOMUX_INDEX"
1652 #endif
1653 };
1654 hal_iomux_init(pinmux_pwm, ARRAY_SIZE(pinmux_pwm));
1655 }
1656
hal_iomux_set_pwm5(void)1657 void hal_iomux_set_pwm5(void)
1658 {
1659 static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_pwm[] = {
1660 #if (PWM5_IOMUX_INDEX == 05)
1661 {HAL_IOMUX_PIN_P0_5, HAL_IOMUX_FUNC_PWM5, PWM5_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1662 #elif (PWM5_IOMUX_INDEX == 15)
1663 {HAL_IOMUX_PIN_P1_5, HAL_IOMUX_FUNC_PWM5, PWM5_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1664 #elif (PWM5_IOMUX_INDEX == 25)
1665 {HAL_IOMUX_PIN_P2_5, HAL_IOMUX_FUNC_PWM5, PWM5_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1666 #elif (PWM5_IOMUX_INDEX == 35)
1667 {HAL_IOMUX_PIN_P3_5, HAL_IOMUX_FUNC_PWM5, PWM5_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1668 #else
1669 #error "Unsupported PWM5_IOMUX_INDEX"
1670 #endif
1671 };
1672 hal_iomux_init(pinmux_pwm, ARRAY_SIZE(pinmux_pwm));
1673 }
1674
hal_iomux_set_pwm6(void)1675 void hal_iomux_set_pwm6(void)
1676 {
1677 static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_pwm[] = {
1678 #if (PWM6_IOMUX_INDEX == 06)
1679 {HAL_IOMUX_PIN_P0_6, HAL_IOMUX_FUNC_PWM6, PWM6_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1680 #elif (PWM6_IOMUX_INDEX == 16)
1681 {HAL_IOMUX_PIN_P1_6, HAL_IOMUX_FUNC_PWM6, PWM6_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1682 #elif (PWM6_IOMUX_INDEX == 26)
1683 {HAL_IOMUX_PIN_P2_6, HAL_IOMUX_FUNC_PWM6, PWM6_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1684 #elif (PWM6_IOMUX_INDEX == 36)
1685 {HAL_IOMUX_PIN_P3_6, HAL_IOMUX_FUNC_PWM6, PWM6_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1686 #else
1687 #error "Unsupported PWM6_IOMUX_INDEX"
1688 #endif
1689 };
1690 hal_iomux_init(pinmux_pwm, ARRAY_SIZE(pinmux_pwm));
1691 }
1692
hal_iomux_set_pwm7(void)1693 void hal_iomux_set_pwm7(void)
1694 {
1695 static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_pwm[] = {
1696 #if (PWM7_IOMUX_INDEX == 07)
1697 {HAL_IOMUX_PIN_P0_7, HAL_IOMUX_FUNC_PWM7, PWM7_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1698 #elif (PWM7_IOMUX_INDEX == 17)
1699 {HAL_IOMUX_PIN_P1_7, HAL_IOMUX_FUNC_PWM7, PWM7_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1700 #elif (PWM7_IOMUX_INDEX == 27)
1701 {HAL_IOMUX_PIN_P2_7, HAL_IOMUX_FUNC_PWM7, PWM7_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1702 #elif (PWM7_IOMUX_INDEX == 37)
1703 {HAL_IOMUX_PIN_P3_7, HAL_IOMUX_FUNC_PWM7, PWM7_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1704 #else
1705 #error "Unsupported PWM7_IOMUX_INDEX"
1706 #endif
1707 };
1708 hal_iomux_init(pinmux_pwm, ARRAY_SIZE(pinmux_pwm));
1709 }
1710
hal_iomux_set_ir(void)1711 void hal_iomux_set_ir(void)
1712 {
1713 static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_ir[] = {
1714 #if (IR_RX_IOMUX_INDEX == 00)
1715 {HAL_IOMUX_PIN_P0_0, HAL_IOMUX_FUNC_IR_RX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1716 #elif (IR_RX_IOMUX_INDEX == 02)
1717 {HAL_IOMUX_PIN_P0_2, HAL_IOMUX_FUNC_IR_RX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1718 #elif (IR_RX_IOMUX_INDEX == 06)
1719 {HAL_IOMUX_PIN_P0_6, HAL_IOMUX_FUNC_IR_RX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1720 #elif (IR_RX_IOMUX_INDEX == 10)
1721 {HAL_IOMUX_PIN_P1_0, HAL_IOMUX_FUNC_IR_RX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1722 #elif (IR_RX_IOMUX_INDEX == 12)
1723 {HAL_IOMUX_PIN_P1_2, HAL_IOMUX_FUNC_IR_RX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1724 #elif (IR_RX_IOMUX_INDEX == 14)
1725 {HAL_IOMUX_PIN_P1_4, HAL_IOMUX_FUNC_IR_RX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1726 #elif (IR_RX_IOMUX_INDEX == 22)
1727 {HAL_IOMUX_PIN_P2_2, HAL_IOMUX_FUNC_IR_RX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1728 #elif (IR_RX_IOMUX_INDEX == 26)
1729 {HAL_IOMUX_PIN_P2_6, HAL_IOMUX_FUNC_IR_RX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1730 #elif (IR_RX_IOMUX_INDEX == 31)
1731 {HAL_IOMUX_PIN_P3_1, HAL_IOMUX_FUNC_IR_RX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1732 #elif (IR_RX_IOMUX_INDEX == 33)
1733 {HAL_IOMUX_PIN_P3_3, HAL_IOMUX_FUNC_IR_RX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1734 #elif (IR_RX_IOMUX_INDEX == 36)
1735 {HAL_IOMUX_PIN_P3_6, HAL_IOMUX_FUNC_IR_RX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1736 #else
1737 #error "Unsupported IR_RX_IOMUX_INDEX"
1738 #endif
1739
1740 #if (IR_TX_IOMUX_INDEX == 01)
1741 {HAL_IOMUX_PIN_P0_1, HAL_IOMUX_FUNC_IR_TX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1742 #elif (IR_TX_IOMUX_INDEX == 03)
1743 {HAL_IOMUX_PIN_P0_3, HAL_IOMUX_FUNC_IR_TX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1744 #elif (IR_TX_IOMUX_INDEX == 07)
1745 {HAL_IOMUX_PIN_P0_7, HAL_IOMUX_FUNC_IR_TX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1746 #elif (IR_TX_IOMUX_INDEX == 11)
1747 {HAL_IOMUX_PIN_P1_1, HAL_IOMUX_FUNC_IR_TX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1748 #elif (IR_TX_IOMUX_INDEX == 13)
1749 {HAL_IOMUX_PIN_P1_3, HAL_IOMUX_FUNC_IR_TX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1750 #elif (IR_TX_IOMUX_INDEX == 15)
1751 {HAL_IOMUX_PIN_P1_5, HAL_IOMUX_FUNC_IR_TX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1752 #elif (IR_TX_IOMUX_INDEX == 21)
1753 {HAL_IOMUX_PIN_P2_1, HAL_IOMUX_FUNC_IR_TX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1754 #elif (IR_TX_IOMUX_INDEX == 27)
1755 {HAL_IOMUX_PIN_P2_7, HAL_IOMUX_FUNC_IR_TX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1756 #elif (IR_TX_IOMUX_INDEX == 32)
1757 {HAL_IOMUX_PIN_P3_2, HAL_IOMUX_FUNC_IR_TX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1758 #elif (IR_TX_IOMUX_INDEX == 34)
1759 {HAL_IOMUX_PIN_P3_4, HAL_IOMUX_FUNC_IR_TX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1760 #elif (IR_TX_IOMUX_INDEX == 37)
1761 {HAL_IOMUX_PIN_P3_7, HAL_IOMUX_FUNC_IR_TX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1762 #else
1763 #error "Unsupported IR_TX_IOMUX_INDEX"
1764 #endif
1765 };
1766
1767 hal_iomux_init(pinmux_ir, ARRAY_SIZE(pinmux_ir));
1768 }
1769
hal_iomux_set_sdmmc(void)1770 void hal_iomux_set_sdmmc(void)
1771 {
1772 static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_sdmmc[] = {
1773 {HAL_IOMUX_PIN_P1_3, HAL_IOMUX_FUNC_SDMMC_CLK, SDMMC_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1774 {HAL_IOMUX_PIN_P1_2, HAL_IOMUX_FUNC_SDMMC_CMD, SDMMC_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1775 {HAL_IOMUX_PIN_P1_4, HAL_IOMUX_FUNC_SDMMC_DATA0, SDMMC_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1776 {HAL_IOMUX_PIN_P1_5, HAL_IOMUX_FUNC_SDMMC_DATA1, SDMMC_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1777 {HAL_IOMUX_PIN_P1_0, HAL_IOMUX_FUNC_SDMMC_DATA2, SDMMC_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1778 {HAL_IOMUX_PIN_P1_1, HAL_IOMUX_FUNC_SDMMC_DATA3, SDMMC_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1779 };
1780
1781 hal_iomux_init(pinmux_sdmmc, ARRAY_SIZE(pinmux_sdmmc));
1782 }
1783
hal_iomux_set_clock_out(void)1784 void hal_iomux_set_clock_out(void)
1785 {
1786 static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_clkout[] = {
1787 #if (CLKOUT_IOMUX_INDEX == 04)
1788 {HAL_IOMUX_PIN_P0_4, HAL_IOMUX_FUNC_CLK_OUT, CLKOUT_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1789 #elif (CLKOUT_IOMUX_INDEX == 13)
1790 {HAL_IOMUX_PIN_P1_3, HAL_IOMUX_FUNC_CLK_OUT, CLKOUT_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1791 #elif (CLKOUT_IOMUX_INDEX == 15)
1792 {HAL_IOMUX_PIN_P1_5, HAL_IOMUX_FUNC_CLK_OUT, CLKOUT_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1793 #elif (CLKOUT_IOMUX_INDEX == 20)
1794 {HAL_IOMUX_PIN_P2_0, HAL_IOMUX_FUNC_CLK_OUT, CLKOUT_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1795 #elif (CLKOUT_IOMUX_INDEX == 21)
1796 {HAL_IOMUX_PIN_P2_1, HAL_IOMUX_FUNC_CLK_OUT, CLKOUT_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1797 #elif (CLKOUT_IOMUX_INDEX == 22)
1798 {HAL_IOMUX_PIN_P2_2, HAL_IOMUX_FUNC_CLK_OUT, CLKOUT_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1799 #elif (CLKOUT_IOMUX_INDEX == 23)
1800 {HAL_IOMUX_PIN_P2_3, HAL_IOMUX_FUNC_CLK_OUT, CLKOUT_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1801 #elif (CLKOUT_IOMUX_INDEX == 27)
1802 {HAL_IOMUX_PIN_P2_7, HAL_IOMUX_FUNC_CLK_OUT, CLKOUT_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1803 #elif (CLKOUT_IOMUX_INDEX == 34)
1804 {HAL_IOMUX_PIN_P3_4, HAL_IOMUX_FUNC_CLK_OUT, CLKOUT_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1805 #else
1806 #error "Unsupported CLKOUT_IOMUX_INDEX"
1807 #endif
1808 };
1809
1810 hal_iomux_init(pinmux_clkout, ARRAY_SIZE(pinmux_clkout));
1811 }
1812
hal_iomux_set_mcu_clock_out(void)1813 void hal_iomux_set_mcu_clock_out(void)
1814 {
1815 }
1816
hal_iomux_set_bt_clock_out(void)1817 void hal_iomux_set_bt_clock_out(void)
1818 {
1819 }
1820
hal_iomux_set_bt_tport(void)1821 void hal_iomux_set_bt_tport(void)
1822 {
1823 ///TODO:
1824 return ;
1825 // P0_0 ~ P0_3,
1826 iomux->REG_004 = (iomux->REG_004 & ~(IOMUX_GPIO_P00_SEL_MASK | IOMUX_GPIO_P01_SEL_MASK | IOMUX_GPIO_P02_SEL_MASK | IOMUX_GPIO_P03_SEL_MASK)) |
1827 IOMUX_GPIO_P00_SEL(0xA) | IOMUX_GPIO_P01_SEL(0xA) | IOMUX_GPIO_P02_SEL(0xA) |IOMUX_GPIO_P03_SEL(0xA);
1828 //P1_0 ~ P1_3,
1829 iomux->REG_008 = (iomux->REG_008 & ~(IOMUX_GPIO_P10_SEL_MASK | IOMUX_GPIO_P11_SEL_MASK | IOMUX_GPIO_P12_SEL_MASK | IOMUX_GPIO_P13_SEL_MASK )) |
1830 IOMUX_GPIO_P10_SEL(0xA) | IOMUX_GPIO_P11_SEL(0xA) | IOMUX_GPIO_P12_SEL(0xA) | IOMUX_GPIO_P13_SEL(0xA);
1831 // ANA TEST DIR
1832 iomux->REG_014 = 0x0f0f;
1833 // ANA TEST SEL
1834 iomux->REG_018 = IOMUX_ANA_TEST_SEL(5);
1835 }
1836
hal_iomux_set_bt_rf_sw(int rx_on,int tx_on)1837 void hal_iomux_set_bt_rf_sw(int rx_on, int tx_on)
1838 {
1839 ///TODO:
1840 return ;
1841 uint32_t val;
1842 uint32_t dir;
1843
1844 //iomux->REG_004 = (iomux->REG_004 & ~(IOMUX_GPIO_P00_SEL_MASK | IOMUX_GPIO_P01_SEL_MASK)) |
1845 // IOMUX_GPIO_P00_SEL(6) | IOMUX_GPIO_P01_SEL(6);
1846
1847 val = iomux->REG_004;
1848 dir = 0;
1849 if (rx_on) {
1850 val = SET_BITFIELD(val, IOMUX_GPIO_P00_SEL, 0xA);
1851 dir = (1 << HAL_IOMUX_PIN_P0_0);
1852 }
1853 if (tx_on) {
1854 val = SET_BITFIELD(val, IOMUX_GPIO_P01_SEL, 0xA);
1855 dir = (1 << HAL_IOMUX_PIN_P0_1);
1856 }
1857 iomux->REG_004 = val;
1858 // ANA TEST DIR
1859 iomux->REG_014 |= dir;
1860 // ANA TEST SEL
1861 iomux->REG_018 = IOMUX_ANA_TEST_SEL(5);
1862 }
hal_iomux_set_wifi_uart(void)1863 void hal_iomux_set_wifi_uart(void)
1864 {
1865 #if (WIFI_UART_IOMUX_INDEX == 20)
1866 uint32_t mask_pd, mask_pu, mask_pu_c;
1867 iomux->REG_00C = (iomux->REG_00C & ~(IOMUX_GPIO_P20_SEL_MASK | IOMUX_GPIO_P21_SEL_MASK)) |
1868 IOMUX_GPIO_P20_SEL(8) | IOMUX_GPIO_P21_SEL(8);
1869
1870 mask_pd = (1 << HAL_IOMUX_PIN_P2_0) | (1 << HAL_IOMUX_PIN_P2_1);
1871 mask_pu = (1 << HAL_IOMUX_PIN_P2_0);
1872 mask_pu_c = (1 << HAL_IOMUX_PIN_P2_1);
1873
1874 // Setup pullup
1875 iomux->REG_02C |= mask_pu;
1876 iomux->REG_02C &= ~(mask_pu_c);
1877 // Clear pulldown
1878 iomux->REG_030 &= ~mask_pd;
1879
1880 #elif (WIFI_UART_IOMUX_INDEX == 21)
1881 uint32_t mask_pd, mask_pu, mask_pu_c;
1882 iomux->REG_00C = (iomux->REG_00C & ~(IOMUX_GPIO_P21_SEL_MASK)) | IOMUX_GPIO_P21_SEL(8);
1883
1884 mask_pd = (1 << HAL_IOMUX_PIN_P2_1);
1885 mask_pu_c = (1 << HAL_IOMUX_PIN_P2_1);
1886
1887 // Setup pullup
1888 // iomux->REG_02C |= mask_pu;
1889 iomux->REG_02C &= ~(mask_pu_c);
1890 // Clear pulldown
1891 iomux->REG_030 &= ~mask_pd;
1892
1893 #elif (WIFI_UART_IOMUX_INDEX == 30)
1894 uint32_t mask_pd, mask_pu, mask_pu_c;
1895 iomux->REG_010 = (iomux->REG_010 & ~(IOMUX_GPIO_P30_SEL_MASK | IOMUX_GPIO_P31_SEL_MASK)) |
1896 IOMUX_GPIO_P30_SEL(7) | IOMUX_GPIO_P31_SEL(7);
1897
1898 mask_pd = (1 << HAL_IOMUX_PIN_P3_0) | (1 << HAL_IOMUX_PIN_P3_1);
1899 mask_pu = (1 << HAL_IOMUX_PIN_P3_0);
1900 mask_pu_c = (1 << HAL_IOMUX_PIN_P3_1);
1901
1902 // Setup pullup
1903 iomux->REG_02C |= mask_pu;
1904 iomux->REG_02C &= ~(mask_pu_c);
1905 // Clear pulldown
1906 iomux->REG_030 &= ~mask_pd;
1907
1908 #else
1909 //default:nothing
1910 #endif
1911 }
1912
hal_pwrkey_set_irq(enum HAL_PWRKEY_IRQ_T type)1913 int WEAK hal_pwrkey_set_irq(enum HAL_PWRKEY_IRQ_T type)
1914 {
1915 uint32_t v;
1916
1917 if (type == HAL_PWRKEY_IRQ_NONE) {
1918 v = IOMUX_POWER_KEY_ON_INT_STATUS | IOMUX_POWER_KEY_OFF_INT_STATUS;
1919 } else if (type == HAL_PWRKEY_IRQ_FALLING_EDGE) {
1920 v = IOMUX_POWER_KEY_ON_INT_EN | IOMUX_POWER_KEY_ON_INT_MSK;
1921 } else if (type == HAL_PWRKEY_IRQ_RISING_EDGE) {
1922 v = IOMUX_POWER_KEY_OFF_INT_EN | IOMUX_POWER_KEY_OFF_INT_MSK;
1923 } else if (type == HAL_PWRKEY_IRQ_BOTH_EDGE) {
1924 v = IOMUX_POWER_KEY_ON_INT_EN | IOMUX_POWER_KEY_ON_INT_MSK |
1925 IOMUX_POWER_KEY_OFF_INT_EN | IOMUX_POWER_KEY_OFF_INT_MSK;
1926 } else {
1927 return 1;
1928 }
1929
1930 iomux->REG_040 = v;
1931
1932 return 0;
1933 }
1934
1935
hal_pwrkey_pressed(void)1936 bool WEAK hal_pwrkey_pressed(void)
1937 {
1938 uint32_t v = iomux->REG_040;
1939 return !!(v & IOMUX_POWER_ON_FEEDOUT);
1940
1941 }
1942
hal_pwrkey_startup_pressed(void)1943 bool hal_pwrkey_startup_pressed(void)
1944 {
1945 return hal_pwrkey_pressed();
1946 }
1947
hal_pwrkey_get_irq_state(void)1948 enum HAL_PWRKEY_IRQ_T WEAK hal_pwrkey_get_irq_state(void)
1949 {
1950 enum HAL_PWRKEY_IRQ_T state = HAL_PWRKEY_IRQ_NONE;
1951 uint32_t v = iomux->REG_040;
1952
1953 if (v & IOMUX_R_POWER_KEY_INTR_U) {
1954 state |= HAL_PWRKEY_IRQ_FALLING_EDGE;
1955 }
1956
1957 if (v & IOMUX_R_POWER_KEY_INTR_D) {
1958 state |= HAL_PWRKEY_IRQ_RISING_EDGE;
1959 }
1960
1961 return state;
1962 }
1963
hal_iomux_set_codec_gpio_trigger(enum HAL_IOMUX_PIN_T pin,bool polarity)1964 void hal_iomux_set_codec_gpio_trigger(enum HAL_IOMUX_PIN_T pin, bool polarity)
1965 {
1966 iomux->REG_064 = SET_BITFIELD(iomux->REG_064, IOMUX_CFG_CODEC_TRIG_SEL, pin);
1967 if (polarity) {
1968 iomux->REG_064 &= ~IOMUX_CFG_CODEC_TRIG_POL;
1969 } else {
1970 iomux->REG_064 |= IOMUX_CFG_CODEC_TRIG_POL;
1971 }
1972 }
1973
hal_iomux_single_wire_uart_rx(uint32_t uart)1974 void hal_iomux_single_wire_uart_rx(uint32_t uart)
1975 {
1976 #ifdef UART_HALF_DUPLEX
1977 #define SUART_TX_PIN_PULL_SEL_IN_RX HAL_IOMUX_PIN_NOPULL
1978 #else
1979 #define SUART_TX_PIN_PULL_SEL_IN_RX HAL_IOMUX_PIN_PULLUP_ENABLE
1980 #endif
1981
1982 struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_uart[] =
1983 {
1984 {HAL_IOMUX_PIN_P2_0, HAL_IOMUX_FUNC_UART1_RX, HAL_IOMUX_PIN_VOLTAGE_VIO, HAL_IOMUX_PIN_PULLUP_ENABLE},
1985 {HAL_IOMUX_PIN_P2_1, HAL_IOMUX_FUNC_GPIO, HAL_IOMUX_PIN_VOLTAGE_VIO, SUART_TX_PIN_PULL_SEL_IN_RX},
1986 };
1987
1988 if (uart == HAL_UART_ID_2) {
1989 pinmux_uart[0].pin = HAL_IOMUX_PIN_P2_2;
1990 pinmux_uart[0].function = HAL_IOMUX_FUNC_UART2_RX;
1991 pinmux_uart[1].pin = HAL_IOMUX_PIN_P2_3;
1992 #ifdef UART_HALF_DUPLEX
1993 iomux->REG_050 &= ~IOMUX_UART2_HALFN;
1994 } else {
1995 iomux->REG_050 &= ~IOMUX_UART1_HALFN;
1996 #endif
1997 }
1998
1999 hal_gpio_pin_set_dir((enum HAL_GPIO_PIN_T)pinmux_uart[0].pin, HAL_GPIO_DIR_IN, 1);
2000 hal_gpio_pin_set_dir((enum HAL_GPIO_PIN_T)pinmux_uart[1].pin, HAL_GPIO_DIR_IN, 1);
2001
2002 hal_iomux_init(pinmux_uart, ARRAY_SIZE(pinmux_uart));
2003
2004 #ifndef UART_HALF_DUPLEX
2005 hal_uart_flush(uart, 0);
2006 #endif
2007 }
2008
hal_iomux_single_wire_uart_tx(uint32_t uart)2009 void hal_iomux_single_wire_uart_tx(uint32_t uart)
2010 {
2011 #ifndef UART_HALF_DUPLEX
2012 struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_uart[] =
2013 {
2014 {HAL_IOMUX_PIN_P2_0, HAL_IOMUX_FUNC_GPIO, HAL_IOMUX_PIN_VOLTAGE_VIO, HAL_IOMUX_PIN_PULLUP_ENABLE},
2015 {HAL_IOMUX_PIN_P2_1, HAL_IOMUX_FUNC_UART1_TX, HAL_IOMUX_PIN_VOLTAGE_VIO, HAL_IOMUX_PIN_NOPULL},
2016 };
2017
2018 if (uart == HAL_UART_ID_2) {
2019 pinmux_uart[0].pin = HAL_IOMUX_PIN_P2_2;
2020 pinmux_uart[1].pin = HAL_IOMUX_PIN_P2_3;
2021 pinmux_uart[1].function = HAL_IOMUX_FUNC_UART2_TX;
2022 }
2023
2024 hal_gpio_pin_set_dir((enum HAL_GPIO_PIN_T)pinmux_uart[0].pin, HAL_GPIO_DIR_IN, 1);
2025 hal_gpio_pin_set_dir((enum HAL_GPIO_PIN_T)pinmux_uart[1].pin, HAL_GPIO_DIR_IN, 1);
2026
2027 hal_iomux_init(pinmux_uart, ARRAY_SIZE(pinmux_uart));
2028 #endif
2029 }
2030
hal_iomux_set_dsi_te(void)2031 void hal_iomux_set_dsi_te(void)
2032 {
2033 struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux[] =
2034 {
2035 {HAL_IOMUX_PIN_P2_1, HAL_IOMUX_FUNC_DISPLAY_TE, HAL_IOMUX_PIN_VOLTAGE_VIO, HAL_IOMUX_PIN_NOPULL},
2036 };
2037
2038 hal_iomux_init(pinmux, ARRAY_SIZE(pinmux));
2039 }
2040
hal_iomux_get_dsi_te_pin(void)2041 enum HAL_IOMUX_PIN_T hal_iomux_get_dsi_te_pin(void)
2042 {
2043 return HAL_IOMUX_PIN_P2_1;
2044 }
2045
hal_iomux_set_wf_fem(int rf_switch)2046 void hal_iomux_set_wf_fem(int rf_switch)
2047 {
2048 uint32_t mask_pd, mask_pu;
2049 #if (1 == WIFI_RF_SWITCH) //bes EVB v2
2050
2051 iomux->REG_00C = (iomux->REG_00C & ~(IOMUX_GPIO_P20_SEL_MASK)) | IOMUX_GPIO_P20_SEL(13);
2052
2053 // mask_pd = (1 << HAL_IOMUX_PIN_P2_0) | (1 << HAL_IOMUX_PIN_P2_1);
2054 mask_pd = (1 << HAL_IOMUX_PIN_P2_0);
2055 mask_pu = (1 << HAL_IOMUX_PIN_P2_0);
2056 // mask_pu_c = (1 << HAL_IOMUX_PIN_P2_1);
2057
2058 // Setup voltage as VIO
2059 iomux->REG_090 &= ~(IOMUX_GPIO_P20_SEL_VIO);
2060
2061 // Setup pullup
2062 iomux->REG_02C |= mask_pu;
2063 // iomux->REG_02C &= ~(mask_pu_c);
2064 // Clear pulldown
2065 iomux->REG_030 &= ~mask_pd;
2066
2067 #else
2068 if( (rf_switch == 20) && hal_get_chip_metal_id() >= HAL_CHIP_METAL_ID_4 )
2069 {
2070 iomux->REG_00C = (iomux->REG_00C & ~(IOMUX_GPIO_P24_SEL_MASK)) | IOMUX_GPIO_P24_SEL(13);
2071
2072 mask_pd = (1 << HAL_IOMUX_PIN_P2_4);
2073 mask_pu = (1 << HAL_IOMUX_PIN_P2_4);
2074
2075 // Setup voltage as VIO
2076 iomux->REG_094 &= ~(IOMUX_GPIO_P24_SEL_VIO);
2077
2078 // Setup pullup
2079 iomux->REG_02C |= mask_pu;
2080 // Clear pulldown
2081 iomux->REG_030 &= ~mask_pd;
2082 }
2083
2084 if( (rf_switch == 12) && hal_get_chip_metal_id() >= HAL_CHIP_METAL_ID_4)
2085 {
2086 iomux->REG_008 = (iomux->REG_008 & ~(IOMUX_GPIO_P14_SEL_MASK)) | IOMUX_GPIO_P14_SEL(13);
2087
2088 mask_pd = (1 << HAL_IOMUX_PIN_P1_4);
2089 mask_pu = (1 << HAL_IOMUX_PIN_P1_4);
2090
2091 // Setup voltage as VIO
2092 iomux->REG_090 &= ~(IOMUX_GPIO_P14_SEL_VIO);
2093
2094 // Setup pullup
2095 iomux->REG_02C |= mask_pu;
2096 // Clear pulldown
2097 iomux->REG_030 &= ~mask_pd;
2098 }
2099
2100 if( (rf_switch == 16) && hal_get_chip_metal_id() >= HAL_CHIP_METAL_ID_4)
2101 {
2102 iomux->REG_00C = (iomux->REG_00C & ~(IOMUX_GPIO_P20_SEL_MASK)) | IOMUX_GPIO_P20_SEL(13);
2103
2104 // mask_pd = (1 << HAL_IOMUX_PIN_P2_0) | (1 << HAL_IOMUX_PIN_P2_1);
2105 mask_pd = (1 << HAL_IOMUX_PIN_P2_0);
2106 mask_pu = (1 << HAL_IOMUX_PIN_P2_0);
2107 // mask_pu_c = (1 << HAL_IOMUX_PIN_P2_1);
2108
2109 // Setup voltage as VIO
2110 iomux->REG_094 &= ~(IOMUX_GPIO_P20_SEL_VIO);
2111
2112 // Setup pullup
2113 iomux->REG_02C |= mask_pu;
2114 // iomux->REG_02C &= ~(mask_pu_c);
2115 // Clear pulldown
2116 iomux->REG_030 &= ~mask_pd;
2117 }
2118
2119 if( (rf_switch == 2) && hal_get_chip_metal_id() >= HAL_CHIP_METAL_ID_4)
2120 {
2121 iomux->REG_004 = (iomux->REG_004 & ~(IOMUX_GPIO_P02_SEL_MASK)) | IOMUX_GPIO_P02_SEL(13);
2122
2123 mask_pd = (1 << HAL_IOMUX_PIN_P0_2);
2124 mask_pu = (1 << HAL_IOMUX_PIN_P0_2);
2125
2126 // Setup voltage as VIO
2127 iomux->REG_090 &= ~(IOMUX_GPIO_P02_SEL_VIO);
2128
2129 // Setup pullup
2130 iomux->REG_02C |= mask_pu;
2131 // Clear pulldown
2132 iomux->REG_030 &= ~mask_pd;
2133 }
2134
2135 //gpio12(sw2)5g txon; gpio13(sw3)0:bt, 1:2g4;
2136 if( (rf_switch == 10) && hal_get_chip_metal_id() >= HAL_CHIP_METAL_ID_4)
2137 {
2138 iomux->REG_008 = (iomux->REG_008 & ~(IOMUX_GPIO_P12_SEL_MASK)) | IOMUX_GPIO_P12_SEL(13);
2139 iomux->REG_008 = (iomux->REG_008 & ~(IOMUX_GPIO_P13_SEL_MASK)) | IOMUX_GPIO_P13_SEL(13);
2140 }
2141
2142 //gpio4 no 5G 2.4g/bt --> 1: 2.4, 0:bt;
2143 if( (rf_switch == 4) && hal_get_chip_metal_id() >= HAL_CHIP_METAL_ID_4)
2144 {
2145 iomux->REG_004 = (iomux->REG_004 & ~(IOMUX_GPIO_P04_SEL_MASK)) | IOMUX_GPIO_P04_SEL(13);
2146 }
2147
2148 //5G GPIO-02 -sw1,2.4G GPIO-04-sw4
2149 if( (rf_switch == 6) && hal_get_chip_metal_id() >= HAL_CHIP_METAL_ID_4)
2150 {
2151 iomux->REG_004 = (iomux->REG_004 & ~(IOMUX_GPIO_P02_SEL_MASK)) | IOMUX_GPIO_P02_SEL(13);
2152
2153 mask_pd = (1 << HAL_IOMUX_PIN_P0_2);
2154 mask_pu = (1 << HAL_IOMUX_PIN_P0_2);
2155
2156 // Setup voltage as VIO
2157 iomux->REG_090 &= ~(IOMUX_GPIO_P02_SEL_VIO);
2158
2159 // Setup pullup
2160 iomux->REG_02C |= mask_pu;
2161 // Clear pulldown
2162 iomux->REG_030 &= ~mask_pd;
2163
2164 iomux->REG_004 = (iomux->REG_004 & ~(IOMUX_GPIO_P04_SEL_MASK)) | IOMUX_GPIO_P04_SEL(13);
2165
2166 mask_pd = (1 << HAL_IOMUX_PIN_P0_4);
2167 mask_pu = (1 << HAL_IOMUX_PIN_P0_4);
2168
2169 // Setup voltage as VIO
2170 iomux->REG_090 &= ~(IOMUX_GPIO_P04_SEL_VIO);
2171
2172 // Setup pullup
2173 iomux->REG_02C |= mask_pu;
2174 // Clear pulldown
2175 iomux->REG_030 &= ~mask_pd;
2176
2177 }
2178
2179 if( (rf_switch == 25) && hal_get_chip_metal_id() >= HAL_CHIP_METAL_ID_4)
2180 {
2181 iomux->REG_010 = (iomux->REG_010 & ~(IOMUX_GPIO_P31_SEL_MASK)) | IOMUX_GPIO_P31_SEL(13);
2182
2183 mask_pd = (1 << HAL_IOMUX_PIN_P3_1);
2184 mask_pu = (1 << HAL_IOMUX_PIN_P3_1);
2185
2186 // Setup voltage as VIO
2187 iomux->REG_094 &= ~(IOMUX_GPIO_P31_SEL_VIO);
2188
2189 // Setup pullup
2190 iomux->REG_02C |= mask_pu;
2191 // Clear pulldown
2192 iomux->REG_030 &= ~mask_pd;
2193 }
2194
2195 //gpio4:epta; gpio20: rxon
2196 if ((rf_switch == 100) && hal_get_chip_metal_id() >= HAL_CHIP_METAL_ID_4)
2197 {
2198 iomux->REG_004 = (iomux->REG_004 & ~(IOMUX_GPIO_P04_SEL_MASK)) | IOMUX_GPIO_P04_SEL(13);
2199 iomux->REG_00C = (iomux->REG_00C & ~(IOMUX_GPIO_P20_SEL_MASK)) | IOMUX_GPIO_P20_SEL(13);
2200 }
2201
2202 //gpio02 rxon
2203 if ((rf_switch == 102) && hal_get_chip_metal_id() >= HAL_CHIP_METAL_ID_4)
2204 {
2205 iomux->REG_004 = (iomux->REG_004 & ~(IOMUX_GPIO_P02_SEL_MASK)) | IOMUX_GPIO_P02_SEL(13);
2206 }
2207 //gpio35 :epta;
2208 if ((rf_switch == 105) && hal_get_chip_metal_id() >= HAL_CHIP_METAL_ID_4)
2209 {
2210 iomux->REG_010 = (iomux->REG_010 & ~(IOMUX_GPIO_P35_SEL_MASK)) | IOMUX_GPIO_P35_SEL(13);
2211 }
2212
2213 /*out fem */
2214 if( (rf_switch == 37) && hal_get_chip_metal_id() >= HAL_CHIP_METAL_ID_4 )
2215 {
2216 iomux->REG_008 = (iomux->REG_008 & ~(IOMUX_GPIO_P13_SEL_MASK)) | IOMUX_GPIO_P13_SEL(13);
2217 iomux->REG_00C = (iomux->REG_00C & ~(IOMUX_GPIO_P24_SEL_MASK)) | IOMUX_GPIO_P24_SEL(13);
2218 iomux->REG_00C = (iomux->REG_00C & ~(IOMUX_GPIO_P27_SEL_MASK)) | IOMUX_GPIO_P27_SEL(13);
2219 }
2220 if( (rf_switch == 101) && hal_get_chip_metal_id() >= HAL_CHIP_METAL_ID_4 )
2221 {
2222 iomux->REG_004 = (iomux->REG_004 & ~(IOMUX_GPIO_P02_SEL_MASK)) | IOMUX_GPIO_P02_SEL(13);
2223 iomux->REG_004 = (iomux->REG_004 & ~(IOMUX_GPIO_P04_SEL_MASK)) | IOMUX_GPIO_P04_SEL(13);
2224 }
2225 //gpio13(sw2)5g txon; gpio12(sw3)0:bt, 1:2g4;
2226 if((rf_switch == 103) && hal_get_chip_metal_id() >= HAL_CHIP_METAL_ID_4)
2227 {
2228 iomux->REG_008 = (iomux->REG_008 & ~(IOMUX_GPIO_P12_SEL_MASK)) | IOMUX_GPIO_P12_SEL(13);
2229 iomux->REG_008 = (iomux->REG_008 & ~(IOMUX_GPIO_P13_SEL_MASK)) | IOMUX_GPIO_P13_SEL(13);
2230 }
2231 if( (rf_switch == 104) && hal_get_chip_metal_id() >= HAL_CHIP_METAL_ID_4 )
2232 {
2233 iomux->REG_008 = (iomux->REG_008 & ~(IOMUX_GPIO_P12_SEL_MASK)) | IOMUX_GPIO_P12_SEL(13);
2234 iomux->REG_008 = (iomux->REG_008 & ~(IOMUX_GPIO_P13_SEL_MASK)) | IOMUX_GPIO_P13_SEL(13);
2235 iomux->REG_00C = (iomux->REG_00C & ~(IOMUX_GPIO_P24_SEL_MASK)) | IOMUX_GPIO_P24_SEL(13);
2236 iomux->REG_00C = (iomux->REG_00C & ~(IOMUX_GPIO_P27_SEL_MASK)) | IOMUX_GPIO_P27_SEL(13);
2237 }
2238
2239 if ((rf_switch == 106) && hal_get_chip_metal_id() >= HAL_CHIP_METAL_ID_4)
2240 {
2241 iomux->REG_004 = (iomux->REG_004 & ~(IOMUX_GPIO_P04_SEL_MASK)) | IOMUX_GPIO_P04_SEL(13);
2242 }
2243
2244 if( (rf_switch == 107) && hal_get_chip_metal_id() >= HAL_CHIP_METAL_ID_4 )
2245 {
2246 iomux->REG_00C = (iomux->REG_00C & ~(IOMUX_GPIO_P22_SEL_MASK)) | IOMUX_GPIO_P22_SEL(13);
2247 mask_pd = (1 << HAL_IOMUX_PIN_P2_2);
2248 mask_pu = (1 << HAL_IOMUX_PIN_P2_2);
2249 // Setup voltage as VIO
2250 iomux->REG_094 &= ~(IOMUX_GPIO_P22_SEL_VIO);
2251
2252 // Setup pullup
2253 iomux->REG_02C |= mask_pu;
2254 // Clear pulldown
2255 iomux->REG_030 &= ~mask_pd;
2256 }
2257
2258 if( (rf_switch == 108) && hal_get_chip_metal_id() >= HAL_CHIP_METAL_ID_4 )
2259 {
2260 iomux->REG_00C = (iomux->REG_00C & ~(IOMUX_GPIO_P22_SEL_MASK)) | IOMUX_GPIO_P22_SEL(13);
2261 }
2262
2263 #endif
2264
2265 }
2266