1 /****************************************************************************** 2 * 3 * Copyright(c) 2017 - 2019 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 ******************************************************************************/ 15 16 #ifndef _HALMAC_STATE_MACHINE_H_ 17 #define _HALMAC_STATE_MACHINE_H_ 18 19 enum halmac_dlfw_state { 20 HALMAC_DLFW_NONE = 0, 21 HALMAC_DLFW_DONE = 1, 22 HALMAC_GEN_INFO_SENT = 2, 23 24 /* Data CPU firmware download framework */ 25 HALMAC_DLFW_INIT = 0x11, 26 HALMAC_DLFW_START = 0x12, 27 HALMAC_DLFW_CONF_READY = 0x13, 28 HALMAC_DLFW_CPU_READY = 0x14, 29 HALMAC_DLFW_MEM_READY = 0x15, 30 HALMAC_DLFW_SW_READY = 0x16, 31 HALMAC_DLFW_OFLD_READY = 0x17, 32 33 HALMAC_DLFW_UNDEFINED = 0x7F, 34 }; 35 36 enum halmac_gpio_cfg_state { 37 HALMAC_GPIO_CFG_STATE_IDLE = 0, 38 HALMAC_GPIO_CFG_STATE_BUSY = 1, 39 HALMAC_GPIO_CFG_STATE_UNDEFINED = 0x7F, 40 }; 41 42 enum halmac_rsvd_pg_state { 43 HALMAC_RSVD_PG_STATE_IDLE = 0, 44 HALMAC_RSVD_PG_STATE_BUSY = 1, 45 HALMAC_RSVD_PG_STATE_UNDEFINED = 0x7F, 46 }; 47 48 enum halmac_api_state { 49 HALMAC_API_STATE_INIT = 0, 50 HALMAC_API_STATE_HALT = 1, 51 HALMAC_API_STATE_UNDEFINED = 0x7F, 52 }; 53 54 enum halmac_cmd_construct_state { 55 HALMAC_CMD_CNSTR_IDLE = 0, 56 HALMAC_CMD_CNSTR_BUSY = 1, 57 HALMAC_CMD_CNSTR_H2C_SENT = 2, 58 HALMAC_CMD_CNSTR_CNSTR = 3, 59 HALMAC_CMD_CNSTR_BUF_CLR = 4, 60 HALMAC_CMD_CNSTR_UNDEFINED = 0x7F, 61 }; 62 63 enum halmac_cmd_process_status { 64 HALMAC_CMD_PROCESS_IDLE = 0x01, /* Init status */ 65 HALMAC_CMD_PROCESS_SENDING = 0x02, /* Wait ack */ 66 HALMAC_CMD_PROCESS_RCVD = 0x03, /* Rcvd ack */ 67 HALMAC_CMD_PROCESS_DONE = 0x04, /* Event done */ 68 HALMAC_CMD_PROCESS_ERROR = 0x05, /* Return code error */ 69 HALMAC_CMD_PROCESS_UNDEFINE = 0x7F, 70 }; 71 72 enum halmac_mac_power { 73 HALMAC_MAC_POWER_OFF = 0x0, 74 HALMAC_MAC_POWER_ON = 0x1, 75 HALMAC_MAC_POWER_UNDEFINE = 0x7F, 76 }; 77 78 enum halmac_wlcpu_mode { 79 HALMAC_WLCPU_ACTIVE = 0x0, 80 HALMAC_WLCPU_ENTER_SLEEP = 0x1, 81 HALMAC_WLCPU_SLEEP = 0x2, 82 HALMAC_WLCPU_UNDEFINE = 0x7F, 83 }; 84 85 struct halmac_efuse_state { 86 enum halmac_cmd_construct_state cmd_cnstr_state; 87 enum halmac_cmd_process_status proc_status; 88 u8 fw_rc; 89 u16 seq_num; 90 }; 91 92 struct halmac_cfg_param_state { 93 enum halmac_cmd_construct_state cmd_cnstr_state; 94 enum halmac_cmd_process_status proc_status; 95 u8 fw_rc; 96 u16 seq_num; 97 }; 98 99 struct halmac_scan_state { 100 enum halmac_cmd_construct_state cmd_cnstr_state; 101 enum halmac_cmd_process_status proc_status; 102 u8 fw_rc; 103 u16 seq_num; 104 }; 105 106 struct halmac_update_pkt_state { 107 enum halmac_cmd_process_status proc_status; 108 u8 fw_rc; 109 u16 seq_num; 110 u8 used_page; 111 }; 112 113 struct halmac_scan_pkt_state { 114 enum halmac_cmd_process_status proc_status; 115 u8 fw_rc; 116 u16 seq_num; 117 }; 118 119 struct halmac_drop_pkt_state { 120 enum halmac_cmd_process_status proc_status; 121 u8 fw_rc; 122 u16 seq_num; 123 }; 124 125 struct halmac_iqk_state { 126 enum halmac_cmd_process_status proc_status; 127 u8 fw_rc; 128 u16 seq_num; 129 }; 130 131 struct halmac_dpk_state { 132 enum halmac_cmd_process_status proc_status; 133 u16 data_size; 134 u16 seg_size; 135 u8 *data; 136 u8 fw_rc; 137 u16 seq_num; 138 }; 139 140 struct halmac_pwr_tracking_state { 141 enum halmac_cmd_process_status proc_status; 142 u8 fw_rc; 143 u16 seq_num; 144 }; 145 146 struct halmac_psd_state { 147 enum halmac_cmd_process_status proc_status; 148 u16 data_size; 149 u16 seg_size; 150 u8 *data; 151 u8 fw_rc; 152 u16 seq_num; 153 }; 154 155 struct halmac_fw_snding_state { 156 enum halmac_cmd_construct_state cmd_cnstr_state; 157 enum halmac_cmd_process_status proc_status; 158 u8 fw_rc; 159 u16 seq_num; 160 }; 161 162 struct halmac_state { 163 struct halmac_efuse_state efuse_state; 164 struct halmac_cfg_param_state cfg_param_state; 165 struct halmac_scan_state scan_state; 166 struct halmac_update_pkt_state update_pkt_state; 167 struct halmac_scan_pkt_state scan_pkt_state; 168 struct halmac_drop_pkt_state drop_pkt_state; 169 struct halmac_iqk_state iqk_state; 170 struct halmac_dpk_state dpk_state; 171 struct halmac_pwr_tracking_state pwr_trk_state; 172 struct halmac_psd_state psd_state; 173 struct halmac_fw_snding_state fw_snding_state; 174 enum halmac_api_state api_state; 175 enum halmac_mac_power mac_pwr; 176 enum halmac_dlfw_state dlfw_state; 177 enum halmac_wlcpu_mode wlcpu_mode; 178 enum halmac_gpio_cfg_state gpio_cfg_state; 179 enum halmac_rsvd_pg_state rsvd_pg_state; 180 }; 181 182 #endif 183