1 /*
2 * Copyright (C) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
17 */
18 #include "hdmi_reg_crg.h"
19 #include "hdmi_product_define.h"
20
21 static volatile hdmi_reg_crg *g_crg_regs = NULL;
22
hdmi_reg_crg_init(void)23 int hdmi_reg_crg_init(void)
24 {
25 if (g_crg_regs != HI_NULL) {
26 return HI_SUCCESS;
27 }
28 g_crg_regs = (hdmi_reg_crg *)osal_ioremap_nocache(HDMI_ADDR_CRG, sizeof(hdmi_reg_crg));
29 if (g_crg_regs == HI_NULL) {
30 hdmi_err("ioremap_nocache gophdmi2tx_dphy_reg_all_reg failed!!!!!!!\n");
31 return HI_FAILURE;
32 }
33
34 return HI_SUCCESS;
35 }
36
hdmi_reg_crg_deinit(void)37 int hdmi_reg_crg_deinit(void)
38 {
39 if (g_crg_regs != HI_NULL) {
40 osal_iounmap((void *)g_crg_regs, sizeof(hdmi_reg_crg));
41 g_crg_regs = HI_NULL;
42 }
43 return HI_SUCCESS;
44 }
45
hdmi_reg_ssc_in_cken_set(unsigned int ssc_in_cken)46 int hdmi_reg_ssc_in_cken_set(unsigned int ssc_in_cken)
47 {
48 hi_u32 *reg_addr = NULL;
49 peri_crg67 peri_crg68;
50
51 reg_addr = (hi_u32 *)&(g_crg_regs->crg68.u32);
52 peri_crg68.u32 = hdmi_tx_reg_read(reg_addr);
53 peri_crg68.bits.ssc_in_cken = ssc_in_cken;
54 hdmi_tx_reg_write(reg_addr, peri_crg68.u32);
55
56 return HI_SUCCESS;
57 }
58
hdmi_reg_ssc_bypass_cken_set(unsigned int ssc_bypass_cken)59 int hdmi_reg_ssc_bypass_cken_set(unsigned int ssc_bypass_cken)
60 {
61 hi_u32 *reg_addr = NULL;
62 peri_crg67 peri_crg68;
63
64 reg_addr = (hi_u32 *)&(g_crg_regs->crg68.u32);
65 peri_crg68.u32 = hdmi_tx_reg_read(reg_addr);
66 peri_crg68.bits.ssc_bypass_cken = ssc_bypass_cken;
67 hdmi_tx_reg_write(reg_addr, peri_crg68.u32);
68
69 return HI_SUCCESS;
70 }
71
hdmi_reg_ctrl_osc_24m_cken_set(unsigned int hdmitx_ctrl_osc_24m_cken)72 int hdmi_reg_ctrl_osc_24m_cken_set(unsigned int hdmitx_ctrl_osc_24m_cken)
73 {
74 hi_u32 *reg_addr = NULL;
75 peri_crg67 peri_crg68;
76
77 reg_addr = (hi_u32 *)&(g_crg_regs->crg68.u32);
78 peri_crg68.u32 = hdmi_tx_reg_read(reg_addr);
79 peri_crg68.bits.hdmitx_ctrl_osc_24m_cken = hdmitx_ctrl_osc_24m_cken;
80 hdmi_tx_reg_write(reg_addr, peri_crg68.u32);
81
82 return HI_SUCCESS;
83 }
84
hdmi_reg_ctrl_cec_cken_set(unsigned int hdmitx_ctrl_cec_cken)85 int hdmi_reg_ctrl_cec_cken_set(unsigned int hdmitx_ctrl_cec_cken)
86 {
87 hi_u32 *reg_addr = NULL;
88 peri_crg67 peri_crg68;
89
90 reg_addr = (hi_u32 *)&(g_crg_regs->crg68.u32);
91 peri_crg68.u32 = hdmi_tx_reg_read(reg_addr);
92 peri_crg68.bits.hdmitx_ctrl_cec_cken = hdmitx_ctrl_cec_cken;
93 hdmi_tx_reg_write(reg_addr, peri_crg68.u32);
94
95 return HI_SUCCESS;
96 }
97
hdmi_reg_ctrl_os_cken_set(unsigned int hdmitx_ctrl_os_cken)98 int hdmi_reg_ctrl_os_cken_set(unsigned int hdmitx_ctrl_os_cken)
99 {
100 hi_u32 *reg_addr = NULL;
101 peri_crg67 peri_crg68;
102
103 reg_addr = (hi_u32 *)&(g_crg_regs->crg68.u32);
104 peri_crg68.u32 = hdmi_tx_reg_read(reg_addr);
105 peri_crg68.bits.hdmitx_ctrl_os_cken = hdmitx_ctrl_os_cken;
106 hdmi_tx_reg_write(reg_addr, peri_crg68.u32);
107
108 return HI_SUCCESS;
109 }
110
hdmi_reg_ctrl_as_cken_set(unsigned int hdmitx_ctrl_as_cken)111 int hdmi_reg_ctrl_as_cken_set(unsigned int hdmitx_ctrl_as_cken)
112 {
113 hi_u32 *reg_addr = NULL;
114 peri_crg67 peri_crg68;
115
116 reg_addr = (hi_u32 *)&(g_crg_regs->crg68.u32);
117 peri_crg68.u32 = hdmi_tx_reg_read(reg_addr);
118 peri_crg68.bits.hdmitx_ctrl_as_cken = hdmitx_ctrl_as_cken;
119 hdmi_tx_reg_write(reg_addr, peri_crg68.u32);
120
121 return HI_SUCCESS;
122 }
123
hdmi_reg_ctrl_bus_srst_req_set(unsigned int hdmitx_ctrl_bus_srst_req)124 int hdmi_reg_ctrl_bus_srst_req_set(unsigned int hdmitx_ctrl_bus_srst_req)
125 {
126 hi_u32 *reg_addr = NULL;
127 peri_crg67 peri_crg68;
128
129 reg_addr = (hi_u32 *)&(g_crg_regs->crg68.u32);
130 peri_crg68.u32 = hdmi_tx_reg_read(reg_addr);
131 peri_crg68.bits.hdmitx_ctrl_bus_srst_req = hdmitx_ctrl_bus_srst_req;
132 hdmi_tx_reg_write(reg_addr, peri_crg68.u32);
133
134 return HI_SUCCESS;
135 }
136
hdmi_reg_ctrl_srst_req_set(unsigned int hdmitx_ctrl_srst_req)137 int hdmi_reg_ctrl_srst_req_set(unsigned int hdmitx_ctrl_srst_req)
138 {
139 hi_u32 *reg_addr = NULL;
140 peri_crg67 peri_crg68;
141
142 reg_addr = (hi_u32 *)&(g_crg_regs->crg68.u32);
143 peri_crg68.u32 = hdmi_tx_reg_read(reg_addr);
144 peri_crg68.bits.hdmitx_ctrl_srst_req = hdmitx_ctrl_srst_req;
145 hdmi_tx_reg_write(reg_addr, peri_crg68.u32);
146
147 return HI_SUCCESS;
148 }
149
hdmi_reg_ctrl_cec_srst_req_set(unsigned int hdmitx_ctrl_cec_srst_req)150 int hdmi_reg_ctrl_cec_srst_req_set(unsigned int hdmitx_ctrl_cec_srst_req)
151 {
152 hi_u32 *reg_addr = NULL;
153 peri_crg67 peri_crg68;
154
155 reg_addr = (hi_u32 *)&(g_crg_regs->crg68.u32);
156 peri_crg68.u32 = hdmi_tx_reg_read(reg_addr);
157 peri_crg68.bits.hdmitx_ctrl_cec_srst_req = hdmitx_ctrl_cec_srst_req;
158 hdmi_tx_reg_write(reg_addr, peri_crg68.u32);
159
160 return HI_SUCCESS;
161 }
162
hdmi_reg_ssc_srst_req_set(unsigned int hdmitx_ssc_srst_req)163 int hdmi_reg_ssc_srst_req_set(unsigned int hdmitx_ssc_srst_req)
164 {
165 hi_u32 *reg_addr = NULL;
166 peri_crg67 peri_crg68;
167
168 reg_addr = (hi_u32 *)&(g_crg_regs->crg68.u32);
169 peri_crg68.u32 = hdmi_tx_reg_read(reg_addr);
170 peri_crg68.bits.hdmitx_ssc_srst_req = hdmitx_ssc_srst_req;
171 hdmi_tx_reg_write(reg_addr, peri_crg68.u32);
172
173 return HI_SUCCESS;
174 }
175
hdmi_reg_ssc_clk_div_set(unsigned int ssc_clk_div)176 int hdmi_reg_ssc_clk_div_set(unsigned int ssc_clk_div)
177 {
178 hi_u32 *reg_addr = NULL;
179 peri_crg67 peri_crg68;
180
181 reg_addr = (hi_u32 *)&(g_crg_regs->crg68.u32);
182 peri_crg68.u32 = hdmi_tx_reg_read(reg_addr);
183 peri_crg68.bits.ssc_clk_div = ssc_clk_div;
184 hdmi_tx_reg_write(reg_addr, peri_crg68.u32);
185
186 return HI_SUCCESS;
187 }
188
hdmi_reg_pxl_cken_set(unsigned int hdmitx_pxl_cken)189 int hdmi_reg_pxl_cken_set(unsigned int hdmitx_pxl_cken)
190 {
191 hi_u32 *reg_addr = NULL;
192 peri_crg67 peri_crg68;
193
194 reg_addr = (hi_u32 *)&(g_crg_regs->crg68.u32);
195 peri_crg68.u32 = hdmi_tx_reg_read(reg_addr);
196 peri_crg68.bits.hdmitx_pxl_cken = hdmitx_pxl_cken;
197 hdmi_tx_reg_write(reg_addr, peri_crg68.u32);
198
199 return HI_SUCCESS;
200 }
201
reg_hdmi_crg_ssc_bypass_clk_sel_set(unsigned int ssc_bypass_clk_sel)202 int reg_hdmi_crg_ssc_bypass_clk_sel_set(unsigned int ssc_bypass_clk_sel)
203 {
204 hi_u32 *reg_addr = NULL;
205 peri_crg67 peri_crg68;
206
207 reg_addr = (hi_u32 *)&(g_crg_regs->crg68.u32);
208 peri_crg68.u32 = hdmi_tx_reg_read(reg_addr);
209 peri_crg68.bits.ssc_bypass_clk_sel = ssc_bypass_clk_sel;
210 hdmi_tx_reg_write(reg_addr, peri_crg68.u32);
211
212 return HI_SUCCESS;
213 }
214
hdmi_reg_hdmirx_phy_tmds_cken_set(unsigned int phy_tmds_cken)215 int hdmi_reg_hdmirx_phy_tmds_cken_set(unsigned int phy_tmds_cken)
216 {
217 hi_u32 *reg_addr = NULL;
218 peri_crg69 peri_crg_69;
219
220 reg_addr = (hi_u32 *)&(g_crg_regs->crg69.u32);
221 peri_crg_69.u32 = hdmi_tx_reg_read(reg_addr);
222 peri_crg_69.bits.phy_tmds_cken = phy_tmds_cken;
223 hdmi_tx_reg_write(reg_addr, peri_crg_69.u32);
224
225 return HI_SUCCESS;
226 }
227
hdmi_reg_phy_srst_req_set(unsigned int hdmitx_phy_srst_req)228 int hdmi_reg_phy_srst_req_set(unsigned int hdmitx_phy_srst_req)
229 {
230 hi_u32 *reg_addr = NULL;
231 peri_crg69 peri_crg_69;
232
233 reg_addr = (hi_u32 *)&(g_crg_regs->crg69.u32);
234 peri_crg_69.u32 = hdmi_tx_reg_read(reg_addr);
235 peri_crg_69.bits.hdmitx_phy_srst_req = hdmitx_phy_srst_req;
236 hdmi_tx_reg_write(reg_addr, peri_crg_69.u32);
237
238 return HI_SUCCESS;
239 }
240
hdmi_reg_phy_srst_req_get(hi_void)241 int hdmi_reg_phy_srst_req_get(hi_void)
242 {
243 hi_u32 *reg_addr = NULL;
244 peri_crg69 peri_crg_69;
245
246 reg_addr = (hi_u32 *)&(g_crg_regs->crg69.u32);
247 peri_crg_69.u32 = hdmi_tx_reg_read(reg_addr);
248 return peri_crg_69.bits.hdmitx_phy_srst_req;
249 }
250
hdmi_reg_phy_tmds_srst_req_set(unsigned int phy_tmds_srst_req)251 int hdmi_reg_phy_tmds_srst_req_set(unsigned int phy_tmds_srst_req)
252 {
253 hi_u32 *reg_addr = NULL;
254 peri_crg69 peri_crg_69;
255
256 reg_addr = (hi_u32 *)&(g_crg_regs->crg69.u32);
257 peri_crg_69.u32 = hdmi_tx_reg_read(reg_addr);
258 peri_crg_69.bits.phy_tmds_srst_req = phy_tmds_srst_req;
259 hdmi_tx_reg_write(reg_addr, peri_crg_69.u32);
260
261 return HI_SUCCESS;
262 }
263
hdmi_reg_phy_tmds_srst_req_get(hi_void)264 int hdmi_reg_phy_tmds_srst_req_get(hi_void)
265 {
266 hi_u32 *reg_addr = NULL;
267 peri_crg69 peri_crg_69;
268
269 reg_addr = (hi_u32 *)&(g_crg_regs->crg69.u32);
270 peri_crg_69.u32 = hdmi_tx_reg_read(reg_addr);
271 return peri_crg_69.bits.phy_tmds_srst_req;
272 }
273
hdmi_reg_tmds_clk_div_set(unsigned int tmds_clk_div)274 int hdmi_reg_tmds_clk_div_set(unsigned int tmds_clk_div)
275 {
276 hi_u32 *reg_addr = NULL;
277 peri_crg69 peri_crg_69;
278
279 reg_addr = (hi_u32 *)&(g_crg_regs->crg69.u32);
280 peri_crg_69.u32 = hdmi_tx_reg_read(reg_addr);
281 peri_crg_69.bits.tmds_clk_div = tmds_clk_div;
282 hdmi_tx_reg_write(reg_addr, peri_crg_69.u32);
283
284 return HI_SUCCESS;
285 }
286
reg_hdmi_crg_tmds_clk_div_get(hi_void)287 int reg_hdmi_crg_tmds_clk_div_get(hi_void)
288 {
289 hi_u32 *reg_addr = NULL;
290 peri_crg69 peri_crg_69;
291
292 reg_addr = (hi_u32 *)&(g_crg_regs->crg69.u32);
293 peri_crg_69.u32 = hdmi_tx_reg_read(reg_addr);
294 return peri_crg_69.bits.tmds_clk_div;
295 }
296
297