1 /*
2 * Copyright (C) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
17 */
18 #include "hdmi_reg_ctrl.h"
19 #include "hdmi_product_define.h"
20
21 volatile hdmi_reg_tx_ctrl *g_tx_ctrl_regs = NULL;
22
hdmi_reg_tx_ctrl_regs_init(hi_char * addr)23 int hdmi_reg_tx_ctrl_regs_init(hi_char *addr)
24 {
25 g_tx_ctrl_regs = (volatile hdmi_reg_tx_ctrl *)(addr + HDMI_TX_BASE_ADDR_CTRL);
26 return HI_SUCCESS;
27 }
28
hdmi_reg_tx_ctrl_regs_deinit(void)29 int hdmi_reg_tx_ctrl_regs_deinit(void)
30 {
31 if (g_tx_ctrl_regs != HI_NULL) {
32 g_tx_ctrl_regs = HI_NULL;
33 }
34 return HI_SUCCESS;
35 }
36
hdmi_reg_tx_mcu_srst_req_set(unsigned int tx_mcu_srst_req)37 int hdmi_reg_tx_mcu_srst_req_set(unsigned int tx_mcu_srst_req)
38 {
39 hi_u32 *reg_addr = NULL;
40 tx_pwd_rst_ctrl tx_pwd_rst;
41
42 reg_addr = (hi_u32 *)&(g_tx_ctrl_regs->pwd_rst_ctrl.u32);
43 tx_pwd_rst.u32 = hdmi_tx_reg_read(reg_addr);
44 tx_pwd_rst.bits.tx_mcu_srst_req = tx_mcu_srst_req;
45 hdmi_tx_reg_write(reg_addr, tx_pwd_rst.u32);
46
47 return HI_SUCCESS;
48 }
49
hdmi_reg_tx_afifo_srst_req_set(unsigned int tx_afifo_srst_req)50 int hdmi_reg_tx_afifo_srst_req_set(unsigned int tx_afifo_srst_req)
51 {
52 hi_u32 *reg_addr = NULL;
53 tx_pwd_rst_ctrl tx_pwd_rst;
54
55 reg_addr = (hi_u32 *)&(g_tx_ctrl_regs->pwd_rst_ctrl.u32);
56 tx_pwd_rst.u32 = hdmi_tx_reg_read(reg_addr);
57 tx_pwd_rst.bits.tx_afifo_srst_req = tx_afifo_srst_req;
58 hdmi_tx_reg_write(reg_addr, tx_pwd_rst.u32);
59
60 return HI_SUCCESS;
61 }
62
hdmi_reg_tx_acr_srst_req_set(unsigned int tx_acr_srst_req)63 int hdmi_reg_tx_acr_srst_req_set(unsigned int tx_acr_srst_req)
64 {
65 hi_u32 *reg_addr = NULL;
66 tx_pwd_rst_ctrl tx_pwd_rst;
67
68 reg_addr = (hi_u32 *)&(g_tx_ctrl_regs->pwd_rst_ctrl.u32);
69 tx_pwd_rst.u32 = hdmi_tx_reg_read(reg_addr);
70 tx_pwd_rst.bits.tx_acr_srst_req = tx_acr_srst_req;
71 hdmi_tx_reg_write(reg_addr, tx_pwd_rst.u32);
72
73 return HI_SUCCESS;
74 }
75
hdmi_reg_tx_aud_srst_req_set(unsigned int tx_aud_srst_req)76 int hdmi_reg_tx_aud_srst_req_set(unsigned int tx_aud_srst_req)
77 {
78 hi_u32 *reg_addr = NULL;
79 tx_pwd_rst_ctrl tx_pwd_rst;
80
81 reg_addr = (hi_u32 *)&(g_tx_ctrl_regs->pwd_rst_ctrl.u32);
82 tx_pwd_rst.u32 = hdmi_tx_reg_read(reg_addr);
83 tx_pwd_rst.bits.tx_aud_srst_req = tx_aud_srst_req;
84 hdmi_tx_reg_write(reg_addr, tx_pwd_rst.u32);
85
86 return HI_SUCCESS;
87 }
88
hdmi_reg_tx_hdmi_srst_req_set(unsigned int tx_hdmi_srst_req)89 int hdmi_reg_tx_hdmi_srst_req_set(unsigned int tx_hdmi_srst_req)
90 {
91 hi_u32 *reg_addr = NULL;
92 tx_pwd_rst_ctrl tx_pwd_rst;
93
94 reg_addr = (hi_u32 *)&(g_tx_ctrl_regs->pwd_rst_ctrl.u32);
95 tx_pwd_rst.u32 = hdmi_tx_reg_read(reg_addr);
96 tx_pwd_rst.bits.tx_hdmi_srst_req = tx_hdmi_srst_req;
97 hdmi_tx_reg_write(reg_addr, tx_pwd_rst.u32);
98
99 return HI_SUCCESS;
100 }
101
hdmi_reg_tx_pwd_srst_req_set(unsigned int tx_pwd_srst_req)102 int hdmi_reg_tx_pwd_srst_req_set(unsigned int tx_pwd_srst_req)
103 {
104 hi_u32 *reg_addr = NULL;
105 tx_pwd_rst_ctrl tx_pwd_rst;
106
107 reg_addr = (hi_u32 *)&(g_tx_ctrl_regs->pwd_rst_ctrl.u32);
108 tx_pwd_rst.u32 = hdmi_tx_reg_read(reg_addr);
109 tx_pwd_rst.bits.tx_pwd_srst_req = tx_pwd_srst_req;
110 hdmi_tx_reg_write(reg_addr, tx_pwd_rst.u32);
111
112 return HI_SUCCESS;
113 }
114
hdmi_reg_pwd_fifo_data_in_set(unsigned int pwd_fifo_data_in)115 int hdmi_reg_pwd_fifo_data_in_set(unsigned int pwd_fifo_data_in)
116 {
117 hi_u32 *reg_addr = NULL;
118 pwd_fifo_wdata fifo_wdata;
119
120 reg_addr = (hi_u32 *)&(g_tx_ctrl_regs->wdata.u32);
121 fifo_wdata.u32 = hdmi_tx_reg_read(reg_addr);
122 fifo_wdata.bits.pwd_fifo_data_in = pwd_fifo_data_in;
123 hdmi_tx_reg_write(reg_addr, fifo_wdata.u32);
124
125 return HI_SUCCESS;
126 }
127
hdmi_reg_pwd_data_out_cnt_set(unsigned int pwd_data_out_cnt)128 int hdmi_reg_pwd_data_out_cnt_set(unsigned int pwd_data_out_cnt)
129 {
130 hi_u32 *reg_addr = NULL;
131 pwd_data_cnt data_cnt;
132
133 reg_addr = (hi_u32 *)&(g_tx_ctrl_regs->data_cnt.u32);
134 data_cnt.u32 = hdmi_tx_reg_read(reg_addr);
135 data_cnt.bits.pwd_data_out_cnt = pwd_data_out_cnt;
136 hdmi_tx_reg_write(reg_addr, data_cnt.u32);
137
138 return HI_SUCCESS;
139 }
140
hdmi_reg_pwd_slave_seg_set(unsigned int pwd_slave_seg)141 int hdmi_reg_pwd_slave_seg_set(unsigned int pwd_slave_seg)
142 {
143 hi_u32 *reg_addr = NULL;
144 pwd_slave_cfg cfg;
145
146 reg_addr = (hi_u32 *)&(g_tx_ctrl_regs->slave_cfg.u32);
147 cfg.u32 = hdmi_tx_reg_read(reg_addr);
148 cfg.bits.pwd_slave_seg = pwd_slave_seg;
149 hdmi_tx_reg_write(reg_addr, cfg.u32);
150
151 return HI_SUCCESS;
152 }
153
hdmi_reg_pwd_slave_offset_set(unsigned int pwd_slave_offset)154 int hdmi_reg_pwd_slave_offset_set(unsigned int pwd_slave_offset)
155 {
156 hi_u32 *reg_addr = NULL;
157 pwd_slave_cfg cfg;
158
159 reg_addr = (hi_u32 *)&(g_tx_ctrl_regs->slave_cfg.u32);
160 cfg.u32 = hdmi_tx_reg_read(reg_addr);
161 cfg.bits.pwd_slave_offset = pwd_slave_offset;
162 hdmi_tx_reg_write(reg_addr, cfg.u32);
163
164 return HI_SUCCESS;
165 }
166
hdmi_reg_pwd_slave_addr_set(unsigned int pwd_slave_addr)167 int hdmi_reg_pwd_slave_addr_set(unsigned int pwd_slave_addr)
168 {
169 hi_u32 *reg_addr = NULL;
170 pwd_slave_cfg cfg;
171
172 reg_addr = (hi_u32 *)&(g_tx_ctrl_regs->slave_cfg.u32);
173 cfg.u32 = hdmi_tx_reg_read(reg_addr);
174 cfg.bits.pwd_slave_addr = pwd_slave_addr;
175 hdmi_tx_reg_write(reg_addr, cfg.u32);
176
177 return HI_SUCCESS;
178 }
179
hdmi_reg_pwd_mst_cmd_set(unsigned int mst_cmd)180 int hdmi_reg_pwd_mst_cmd_set(unsigned int mst_cmd)
181 {
182 hi_u32 *reg_addr = NULL;
183 pwd_mst_cmd cmd;
184
185 reg_addr = (hi_u32 *)&(g_tx_ctrl_regs->mst_cmd.u32);
186 cmd.u32 = hdmi_tx_reg_read(reg_addr);
187 cmd.bits.pwd_mst_cmd = mst_cmd;
188 hdmi_tx_reg_write(reg_addr, cmd.u32);
189
190 return HI_SUCCESS;
191 }
192
hdmi_reg_cpu_ddc_req_set(unsigned int cpu_ddc_req)193 int hdmi_reg_cpu_ddc_req_set(unsigned int cpu_ddc_req)
194 {
195 hi_u32 *reg_addr = NULL;
196 ddc_mst_arb_reql arb_req;
197
198 reg_addr = (hi_u32 *)&(g_tx_ctrl_regs->ddc_arb_req.u32);
199 arb_req.u32 = hdmi_tx_reg_read(reg_addr);
200 arb_req.bits.cpu_ddc_req = cpu_ddc_req;
201 hdmi_tx_reg_write(reg_addr, arb_req.u32);
202
203 return HI_SUCCESS;
204 }
205
hdmi_reg_rdata_pwd_fifo_data_out_get(void)206 hi_u8 hdmi_reg_rdata_pwd_fifo_data_out_get(void)
207 {
208 hi_u32 *reg_addr = NULL;
209 pwd_fifo_rdata fifo_rdata;
210
211 reg_addr = (hi_u32 *)&(g_tx_ctrl_regs->rdata.u32);
212 fifo_rdata.u32 = hdmi_tx_reg_read(reg_addr);
213 return fifo_rdata.bits.pwd_fifo_data_out;
214 }
215
hdmi_reg_pwd_fifo_data_out_get(void)216 hi_u32 hdmi_reg_pwd_fifo_data_out_get(void)
217 {
218 hi_u32 *reg_addr = NULL;
219 pwd_data_cnt data_cnt;
220
221 reg_addr = (hi_u32 *)&(g_tx_ctrl_regs->data_cnt.u32);
222 data_cnt.u32 = hdmi_tx_reg_read(reg_addr);
223 return data_cnt.bits.pwd_fifo_data_cnt;
224 }
225
hdmi_reg_pwd_fifo_empty_get(void)226 hi_u32 hdmi_reg_pwd_fifo_empty_get(void)
227 {
228 hi_u32 *reg_addr = NULL;
229 pwd_mst_state mst_state;
230
231 reg_addr = (hi_u32 *)&(g_tx_ctrl_regs->mst_state.u32);
232 mst_state.u32 = hdmi_tx_reg_read(reg_addr);
233 return mst_state.bits.pwd_fifo_empty;
234 }
235
hdmi_reg_pwd_i2c_in_prog_get(void)236 hi_u32 hdmi_reg_pwd_i2c_in_prog_get(void)
237 {
238 hi_u32 *reg_addr = NULL;
239 pwd_mst_state mst_state;
240
241 reg_addr = (hi_u32 *)&(g_tx_ctrl_regs->mst_state.u32);
242 mst_state.u32 = hdmi_tx_reg_read(reg_addr);
243 return mst_state.bits.pwd_i2c_in_prog;
244 }
245
hdmi_reg_cpu_ddc_req_ack_get(void)246 hi_u32 hdmi_reg_cpu_ddc_req_ack_get(void)
247 {
248 hi_u32 *reg_addr = NULL;
249 ddc_mst_arb_ack arb_ack;
250
251 reg_addr = (hi_u32 *)&(g_tx_ctrl_regs->ddc_arb_ack.u32);
252 arb_ack.u32 = hdmi_tx_reg_read(reg_addr);
253 return arb_ack.bits.cpu_ddc_req_ack;
254 }
255
256