1 /* 2 * linux-5.4/drivers/media/platform/sunxi-vin/vin-mipi/dphy/dphy_reg_i.h 3 * 4 * Copyright (c) 2007-2017 Allwinnertech Co., Ltd. 5 * 6 * This software is licensed under the terms of the GNU General Public 7 * License version 2, as published by the Free Software Foundation, and 8 * may be copied, distributed, and modified under those terms. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 */ 16 17 18 #ifndef __DPHY_REG_I_H__ 19 #define __DPHY_REG_I_H__ 20 21 #ifdef __cplusplus 22 extern "C" { 23 #endif 24 25 /* 26 * Register Offset 27 */ 28 #define DPHY_CTL_REG_OFF 0x000 29 #define DPHY_TX_CTL_REG_OFF 0x004 30 #define DPHY_RX_CTL_REG_OFF 0x008 31 #define DPHY_TX_TIME0_REG_OFF 0x010 32 #define DPHY_TX_TIME1_REG_OFF 0x014 33 #define DPHY_TX_TIME2_REG_OFF 0x018 34 #define DPHY_TX_TIME3_REG_OFF 0x01C 35 #define DPHY_TX_TIME4_REG_OFF 0x020 36 #define DPHY_RX_TIME0_REG_OFF 0x030 37 #define DPHY_RX_TIME1_REG_OFF 0x034 38 #define DPHY_RX_TIME2_REG_OFF 0x038 39 #define DPHY_RX_TIME3_REG_OFF 0x040 40 #define DPHY_ANA0_REG_OFF 0x04C 41 #define DPHY_ANA1_REG_OFF 0x050 42 #define DPHY_ANA2_REG_OFF 0x054 43 #define DPHY_ANA3_REG_OFF 0x058 44 #define DPHY_ANA4_REG_OFF 0x05C 45 #define DPHY_INT_EN0_REG_OFF 0x060 46 #define DPHY_INT_EN1_REG_OFF 0x064 47 #define DPHY_INT_EN2_REG_OFF 0x068 48 #define DPHY_INT_PD0_REG_OFF 0x070 49 #define DPHY_INT_PD1_REG_OFF 0x074 50 #define DPHY_INT_PD2_REG_OFF 0x078 51 #define DPHY_DBG0_REG_OFF 0x0E0 52 #define DPHY_DBG1_REG_OFF 0x0E4 53 #define DPHY_DBG2_REG_OFF 0x0E8 54 #define DPHY_DBG3_REG_OFF 0x0EC 55 #define DPHY_DBG4_REG_OFF 0x0F0 56 #define DPHY_DBG5_REG_OFF 0x0F4 57 58 /* 59 * Register Address 60 */ 61 #define DPHY_CTL_REG_ADDR (DPHY_VBASE + DPHY_CTL_REG_OFF) 62 #define DPHY_TX_CTL_REG_ADDR (DPHY_VBASE + DPHY_TX_CTL_REG_OFF) 63 #define DPHY_RX_CTL_REG_ADDR (DPHY_VBASE + DPHY_RX_CTL_REG_OFF) 64 #define DPHY_TX_TIME0_REG_ADDR (DPHY_VBASE + DPHY_TX_TIME0_REG_OFF) 65 #define DPHY_TX_TIME1_REG_ADDR (DPHY_VBASE + DPHY_TX_TIME1_REG_OFF) 66 #define DPHY_TX_TIME2_REG_ADDR (DPHY_VBASE + DPHY_TX_TIME2_REG_OFF) 67 #define DPHY_TX_TIME3_REG_ADDR (DPHY_VBASE + DPHY_TX_TIME3_REG_OFF) 68 #define DPHY_TX_TIME4_REG_ADDR (DPHY_VBASE + DPHY_TX_TIME4_REG_OFF) 69 #define DPHY_RX_TIME0_REG_ADDR (DPHY_VBASE + DPHY_RX_TIME0_REG_OFF) 70 #define DPHY_RX_TIME1_REG_ADDR (DPHY_VBASE + DPHY_RX_TIME1_REG_OFF) 71 #define DPHY_RX_TIME2_REG_ADDR (DPHY_VBASE + DPHY_RX_TIME2_REG_OFF) 72 #define DPHY_RX_TIME3_REG_ADDR (DPHY_VBASE + DPHY_RX_TIME3_REG_OFF) 73 #define DPHY_ANA0_REG_ADDR (DPHY_VBASE + DPHY_ANA0_REG_OFF) 74 #define DPHY_ANA1_REG_ADDR (DPHY_VBASE + DPHY_ANA1_REG_OFF) 75 #define DPHY_ANA2_REG_ADDR (DPHY_VBASE + DPHY_ANA2_REG_OFF) 76 #define DPHY_ANA3_REG_ADDR (DPHY_VBASE + DPHY_ANA3_REG_OFF) 77 #define DPHY_ANA4_REG_ADDR (DPHY_VBASE + DPHY_ANA4_REG_OFF) 78 #define DPHY_INT_EN0_REG_ADDR (DPHY_VBASE + DPHY_INT_EN0_REG_OFF) 79 #define DPHY_INT_EN1_REG_ADDR (DPHY_VBASE + DPHY_INT_EN1_REG_OFF) 80 #define DPHY_INT_EN2_REG_ADDR (DPHY_VBASE + DPHY_INT_EN2_REG_OFF) 81 #define DPHY_INT_PD0_REG_ADDR (DPHY_VBASE + DPHY_INT_PD0_REG_OFF) 82 #define DPHY_INT_PD1_REG_ADDR (DPHY_VBASE + DPHY_INT_PD1_REG_OFF) 83 #define DPHY_INT_PD2_REG_ADDR (DPHY_VBASE + DPHY_INT_PD2_REG_OFF) 84 #define DPHY_DBG0_REG_ADDR (DPHY_VBASE + DPHY_DBG0_REG_OFF) 85 #define DPHY_DBG1_REG_ADDR (DPHY_VBASE + DPHY_DBG1_REG_OFF) 86 #define DPHY_DBG2_REG_ADDR (DPHY_VBASE + DPHY_DBG2_REG_OFF) 87 #define DPHY_DBG3_REG_ADDR (DPHY_VBASE + DPHY_DBG3_REG_OFF) 88 #define DPHY_DBG4_REG_ADDR (DPHY_VBASE + DPHY_DBG4_REG_OFF) 89 #define DPHY_DBG5_REG_ADDR (DPHY_VBASE + DPHY_DBG5_REG_OFF) 90 91 /* 92 * Detail information of registers 93 */ 94 95 typedef union { 96 unsigned int dwval; 97 struct { 98 unsigned int module_en:1; 99 unsigned int res0:3; 100 unsigned int lane_num:2; 101 unsigned int res1:26; 102 } bits; 103 } DPHY_CTL_REG_t; 104 105 typedef union { 106 unsigned int dwval; 107 struct { 108 unsigned int tx_d0_force:1; 109 unsigned int tx_d1_force:1; 110 unsigned int tx_d2_force:1; 111 unsigned int tx_d3_force:1; 112 unsigned int tx_clk_force:1; 113 unsigned int res0:3; 114 unsigned int lptx_endian:1; 115 unsigned int hstx_endian:1; 116 unsigned int lptx_8b9b_en:1; 117 unsigned int hstx_8b9b_en:1; 118 unsigned int force_lp11:1; 119 unsigned int res1:3; 120 unsigned int ulpstx_data0_exit:1; 121 unsigned int ulpstx_data1_exit:1; 122 unsigned int ulpstx_data2_exit:1; 123 unsigned int ulpstx_data3_exit:1; 124 unsigned int ulpstx_clk_exit:1; 125 unsigned int res2:3; 126 unsigned int hstx_data_exit:1; 127 unsigned int hstx_clk_exit:1; 128 unsigned int res3:2; 129 unsigned int hstx_clk_cont:1; 130 unsigned int ulpstx_enter:1; 131 unsigned int res4:2; 132 } bits; 133 } DPHY_TX_CTL_REG_t; 134 135 typedef union { 136 unsigned int dwval; 137 struct { 138 unsigned int res0:8; 139 unsigned int lprx_endian:1; 140 unsigned int hsrx_endian:1; 141 unsigned int lprx_8b9b_en:1; 142 unsigned int hsrx_8b9b_en:1; 143 unsigned int hsrx_sync:1; 144 unsigned int res1:3; 145 unsigned int lprx_trnd_mask:4; 146 unsigned int rx_d0_force:1; 147 unsigned int rx_d1_force:1; 148 unsigned int rx_d2_force:1; 149 unsigned int rx_d3_force:1; 150 unsigned int rx_clk_force:1; 151 unsigned int res2:6; 152 unsigned int dbc_en:1; 153 } bits; 154 } DPHY_RX_CTL_REG_t; 155 156 typedef union { 157 unsigned int dwval; 158 struct { 159 unsigned int lpx_tm_set:8; 160 unsigned int dterm_set:8; 161 unsigned int hs_pre_set:8; 162 unsigned int hs_trail_set:8; 163 } bits; 164 } DPHY_TX_TIME0_REG_t; 165 166 typedef union { 167 unsigned int dwval; 168 struct { 169 unsigned int ck_prep_set:8; 170 unsigned int ck_zero_set:8; 171 unsigned int ck_pre_set:8; 172 unsigned int ck_post_set:8; 173 } bits; 174 } DPHY_TX_TIME1_REG_t; 175 176 typedef union { 177 unsigned int dwval; 178 struct { 179 unsigned int ck_trail_set:8; 180 unsigned int hs_dly_set:16; 181 unsigned int res0:4; 182 unsigned int hs_dly_mode:1; 183 unsigned int res1:3; 184 } bits; 185 } DPHY_TX_TIME2_REG_t; 186 187 typedef union { 188 unsigned int dwval; 189 struct { 190 unsigned int lptx_ulps_exit_set:20; 191 unsigned int res0:12; 192 } bits; 193 } DPHY_TX_TIME3_REG_t; 194 195 typedef union { 196 unsigned int dwval; 197 struct { 198 unsigned int hstx_ana0_set:8; 199 unsigned int hstx_ana1_set:8; 200 unsigned int res0:16; 201 } bits; 202 } DPHY_TX_TIME4_REG_t; 203 204 typedef union { 205 unsigned int dwval; 206 struct { 207 unsigned int lprx_to_en:1; 208 unsigned int freq_cnt_en:1; 209 unsigned int res0:2; 210 unsigned int hsrx_clk_miss_en:1; 211 unsigned int hsrx_sync_err_to_en:1; 212 unsigned int res1:2; 213 unsigned int lprx_to:8; 214 unsigned int hsrx_clk_miss:8; 215 unsigned int hsrx_sync_err_to:8; 216 } bits; 217 } DPHY_RX_TIME0_REG_t; 218 219 typedef union { 220 unsigned int dwval; 221 struct { 222 unsigned int lprx_ulps_wp:20; 223 unsigned int rx_dly:12; 224 } bits; 225 } DPHY_RX_TIME1_REG_t; 226 227 typedef union { 228 unsigned int dwval; 229 struct { 230 unsigned int hsrx_ana0_set:8; 231 unsigned int hsrx_ana1_set:8; 232 unsigned int res0:16; 233 } bits; 234 } DPHY_RX_TIME2_REG_t; 235 236 typedef union { 237 unsigned int dwval; 238 struct { 239 unsigned int freq_cnt:16; 240 unsigned int lprst_dly:16; 241 } bits; 242 } DPHY_RX_TIME3_REG_t; 243 244 typedef union { 245 unsigned int dwval; 246 struct { 247 unsigned int reg_selsck:1; 248 unsigned int reg_rsd:1; 249 unsigned int reg_sfb:2; 250 unsigned int reg_plr:4; 251 unsigned int reg_den:4; 252 unsigned int reg_slv:3; 253 unsigned int reg_sdiv2:1; 254 unsigned int reg_srxck:4; 255 unsigned int reg_srxdt:4; 256 unsigned int reg_dmp:4; 257 unsigned int reg_dmpc:1; 258 unsigned int reg_pwenc:1; 259 unsigned int reg_pwend:1; 260 unsigned int reg_pws:1; 261 } bits; 262 } DPHY_ANA0_REG_t; 263 264 typedef union { 265 unsigned int dwval; 266 struct { 267 unsigned int reg_stxck:1; 268 unsigned int res0:3; 269 unsigned int reg_svdl0:4; 270 unsigned int reg_svdl1:4; 271 unsigned int reg_svdl2:4; 272 unsigned int reg_svdl3:4; 273 unsigned int reg_svdlc:4; 274 unsigned int reg_svtt:4; 275 unsigned int reg_csmps:2; 276 unsigned int res1:1; 277 unsigned int reg_vttmode:1; 278 } bits; 279 } DPHY_ANA1_REG_t; 280 281 typedef union { 282 unsigned int dwval; 283 struct { 284 unsigned int ana_cpu_en:1; 285 unsigned int enib:1; 286 unsigned int enrvs:1; 287 unsigned int res0:1; 288 unsigned int enck_cpu:1; 289 unsigned int entxc_cpu:1; 290 unsigned int enckq_cpu:1; 291 unsigned int res1:1; 292 unsigned int entx_cpu:4; 293 unsigned int res2:1; 294 unsigned int entermc_cpu:1; 295 unsigned int enrxc_cpu:1; 296 unsigned int res3:1; 297 unsigned int enterm_cpu:4; 298 unsigned int enrx_cpu:4; 299 unsigned int enp2s_cpu:4; 300 unsigned int res4:4; 301 } bits; 302 } DPHY_ANA2_REG_t; 303 304 typedef union { 305 unsigned int dwval; 306 struct { 307 unsigned int enlptx_cpu:4; 308 unsigned int enlprx_cpu:4; 309 unsigned int enlpcd_cpu:4; 310 unsigned int enlprxc_cpu:1; 311 unsigned int enlptxc_cpu:1; 312 unsigned int enlpcdc_cpu:1; 313 unsigned int res0:1; 314 unsigned int entest:1; 315 unsigned int enckdbg:1; 316 unsigned int enldor:1; 317 unsigned int res1:5; 318 unsigned int enldod:1; 319 unsigned int enldoc:1; 320 unsigned int endiv:1; 321 unsigned int envttc:1; 322 unsigned int envtt:4; 323 } bits; 324 } DPHY_ANA3_REG_t; 325 326 typedef union { 327 unsigned int dwval; 328 struct { 329 unsigned int reg_txpusd:2; 330 unsigned int reg_txpusc:2; 331 unsigned int reg_txdnsd:2; 332 unsigned int reg_txdnsc:2; 333 unsigned int reg_tmsd:2; 334 unsigned int reg_tmsc:2; 335 unsigned int reg_ckdv:5; 336 unsigned int res0:3; 337 unsigned int reg_dmplvd:4; 338 unsigned int reg_dmplvc:1; 339 unsigned int res1:7; 340 } bits; 341 } DPHY_ANA4_REG_t; 342 343 typedef union { 344 unsigned int dwval; 345 struct { 346 unsigned int sot_d0_int:1; 347 unsigned int sot_d1_int:1; 348 unsigned int sot_d2_int:1; 349 unsigned int sot_d3_int:1; 350 unsigned int sot_err_d0_int:1; 351 unsigned int sot_err_d1_int:1; 352 unsigned int sot_err_d2_int:1; 353 unsigned int sot_err_d3_int:1; 354 unsigned int sot_sync_err_d0_int:1; 355 unsigned int sot_sync_err_d1_int:1; 356 unsigned int sot_sync_err_d2_int:1; 357 unsigned int sot_sync_err_d3_int:1; 358 unsigned int rx_alg_err_d0_int:1; 359 unsigned int rx_alg_err_d1_int:1; 360 unsigned int rx_alg_err_d2_int:1; 361 unsigned int rx_alg_err_d3_int:1; 362 unsigned int res0:6; 363 unsigned int cd_lp0_err_clk_int:1; 364 unsigned int cd_lp1_err_clk_int:1; 365 unsigned int cd_lp0_err_d0_int:1; 366 unsigned int cd_lp1_err_d0_int:1; 367 unsigned int cd_lp0_err_d1_int:1; 368 unsigned int cd_lp1_err_d1_int:1; 369 unsigned int cd_lp0_err_d2_int:1; 370 unsigned int cd_lp1_err_d2_int:1; 371 unsigned int cd_lp0_err_d3_int:1; 372 unsigned int cd_lp1_err_d3_int:1; 373 } bits; 374 } DPHY_INT_EN0_REG_t; 375 376 typedef union { 377 unsigned int dwval; 378 struct { 379 unsigned int ulps_d0_int:1; 380 unsigned int ulps_d1_int:1; 381 unsigned int ulps_d2_int:1; 382 unsigned int ulps_d3_int:1; 383 unsigned int ulps_wp_d0_int:1; 384 unsigned int ulps_wp_d1_int:1; 385 unsigned int ulps_wp_d2_int:1; 386 unsigned int ulps_wp_d3_int:1; 387 unsigned int ulps_clk_int:1; 388 unsigned int ulps_wp_clk_int:1; 389 unsigned int res0:2; 390 unsigned int lpdt_d0_int:1; 391 unsigned int rx_trnd_d0_int:1; 392 unsigned int tx_trnd_err_d0_int:1; 393 unsigned int undef1_d0_int:1; 394 unsigned int undef2_d0_int:1; 395 unsigned int undef3_d0_int:1; 396 unsigned int undef4_d0_int:1; 397 unsigned int undef5_d0_int:1; 398 unsigned int rst_d0_int:1; 399 unsigned int rst_d1_int:1; 400 unsigned int rst_d2_int:1; 401 unsigned int rst_d3_int:1; 402 unsigned int esc_cmd_err_d0_int:1; 403 unsigned int esc_cmd_err_d1_int:1; 404 unsigned int esc_cmd_err_d2_int:1; 405 unsigned int esc_cmd_err_d3_int:1; 406 unsigned int false_ctl_d0_int:1; 407 unsigned int false_ctl_d1_int:1; 408 unsigned int false_ctl_d2_int:1; 409 unsigned int false_ctl_d3_int:1; 410 } bits; 411 } DPHY_INT_EN1_REG_t; 412 413 typedef union { 414 unsigned int dwval; 415 struct { 416 unsigned int res0; 417 } bits; 418 } DPHY_INT_EN2_REG_t; 419 420 typedef union { 421 unsigned int dwval; 422 struct { 423 unsigned int sot_d0_pd:1; 424 unsigned int sot_d1_pd:1; 425 unsigned int sot_d2_pd:1; 426 unsigned int sot_d3_pd:1; 427 unsigned int sot_err_d0_pd:1; 428 unsigned int sot_err_d1_pd:1; 429 unsigned int sot_err_d2_pd:1; 430 unsigned int sot_err_d3_pd:1; 431 unsigned int sot_sync_err_d0_pd:1; 432 unsigned int sot_sync_err_d1_pd:1; 433 unsigned int sot_sync_err_d2_pd:1; 434 unsigned int sot_sync_err_d3_pd:1; 435 unsigned int rx_alg_err_d0_pd:1; 436 unsigned int rx_alg_err_d1_pd:1; 437 unsigned int rx_alg_err_d2_pd:1; 438 unsigned int rx_alg_err_d3_pd:1; 439 unsigned int res0:6; 440 unsigned int cd_lp0_err_clk_pd:1; 441 unsigned int cd_lp1_err_clk_pd:1; 442 unsigned int cd_lp0_err_d1_pd:1; 443 unsigned int cd_lp1_err_d1_pd:1; 444 unsigned int cd_lp0_err_d0_pd:1; 445 unsigned int cd_lp1_err_d0_pd:1; 446 unsigned int cd_lp0_err_d2_pd:1; 447 unsigned int cd_lp1_err_d2_pd:1; 448 unsigned int cd_lp0_err_d3_pd:1; 449 unsigned int cd_lp1_err_d3_pd:1; 450 } bits; 451 } DPHY_INT_PD0_REG_t; 452 453 typedef union { 454 unsigned int dwval; 455 struct { 456 unsigned int ulps_d0_pd:1; 457 unsigned int ulps_d1_pd:1; 458 unsigned int ulps_d2_pd:1; 459 unsigned int ulps_d3_pd:1; 460 unsigned int ulps_wp_d0_pd:1; 461 unsigned int ulps_wp_d1_pd:1; 462 unsigned int ulps_wp_d2_pd:1; 463 unsigned int ulps_wp_d3_pd:1; 464 unsigned int ulps_clk_pd:1; 465 unsigned int ulps_wp_clk_pd:1; 466 unsigned int res0:2; 467 unsigned int lpdt_d0_pd:1; 468 unsigned int rx_trnd_d0_pd:1; 469 unsigned int tx_trnd_err_d0_pd:1; 470 unsigned int undef1_d0_pd:1; 471 unsigned int undef2_d0_pd:1; 472 unsigned int undef3_d0_pd:1; 473 unsigned int undef4_d0_pd:1; 474 unsigned int undef5_d0_pd:1; 475 unsigned int rst_d0_pd:1; 476 unsigned int rst_d1_pd:1; 477 unsigned int rst_d2_pd:1; 478 unsigned int rst_d3_pd:1; 479 unsigned int esc_cmd_err_d0_pd:1; 480 unsigned int esc_cmd_err_d1_pd:1; 481 unsigned int esc_cmd_err_d2_pd:1; 482 unsigned int esc_cmd_err_d3_pd:1; 483 unsigned int false_ctl_d0_pd:1; 484 unsigned int false_ctl_d1_pd:1; 485 unsigned int false_ctl_d2_pd:1; 486 unsigned int false_ctl_d3_pd:1; 487 } bits; 488 } DPHY_INT_PD1_REG_t; 489 490 typedef union { 491 unsigned int dwval; 492 struct { 493 unsigned int res0; 494 } bits; 495 } DPHY_INT_PD2_REG_t; 496 497 typedef union { 498 unsigned int dwval; 499 struct { 500 unsigned int lptx_sta_d0:3; 501 unsigned int res0:1; 502 unsigned int lptx_sta_d1:3; 503 unsigned int res1:1; 504 unsigned int lptx_sta_d2:3; 505 unsigned int res2:1; 506 unsigned int lptx_sta_d3:3; 507 unsigned int res3:1; 508 unsigned int lptx_sta_clk:3; 509 unsigned int res4:9; 510 unsigned int direction:1; 511 unsigned int res5:3; 512 } bits; 513 } DPHY_DBG0_REG_t; 514 515 typedef union { 516 unsigned int dwval; 517 struct { 518 unsigned int lptx_dbg_en:1; 519 unsigned int hstx_dbg_en:1; 520 unsigned int res0:2; 521 unsigned int lptx_set_d0:2; 522 unsigned int lptx_set_d1:2; 523 unsigned int lptx_set_d2:2; 524 unsigned int lptx_set_d3:2; 525 unsigned int lptx_set_ck:2; 526 unsigned int res1:18; 527 } bits; 528 } DPHY_DBG1_REG_t; 529 530 typedef union { 531 unsigned int dwval; 532 struct { 533 unsigned int hstx_data; 534 } bits; 535 } DPHY_DBG2_REG_t; 536 537 typedef union { 538 unsigned int dwval; 539 struct { 540 unsigned int lprx_sta_d0:4; 541 unsigned int lprx_sta_d1:4; 542 unsigned int lprx_sta_d2:4; 543 unsigned int lprx_sta_d3:4; 544 unsigned int lprx_sta_clk:4; 545 unsigned int res0:12; 546 } bits; 547 } DPHY_DBG3_REG_t; 548 549 typedef union { 550 unsigned int dwval; 551 struct { 552 unsigned int lprx_phy_d0:2; 553 unsigned int lprx_phy_d1:2; 554 unsigned int lprx_phy_d2:2; 555 unsigned int lprx_phy_d3:2; 556 unsigned int lprx_phy_clk:2; 557 unsigned int res0:6; 558 unsigned int lpcd_phy_d0:2; 559 unsigned int lpcd_phy_d1:2; 560 unsigned int lpcd_phy_d2:2; 561 unsigned int lpcd_phy_d3:2; 562 unsigned int lpcd_phy_clk:2; 563 unsigned int res1:6; 564 } bits; 565 } DPHY_DBG4_REG_t; 566 567 typedef union { 568 unsigned int dwval; 569 struct { 570 unsigned int hsrx_data0:8; 571 unsigned int hsrx_data1:8; 572 unsigned int hsrx_data2:8; 573 unsigned int hsrx_data3:8; 574 } bits; 575 } DPHY_DBG5_REG_t; 576 577 #ifdef __cplusplus 578 } 579 #endif 580 581 #endif 582