1 // Copyright (C) 2022 Beken Corporation 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 16 #include <common/bk_include.h> 17 #include "i2s_hal.h" 18 #include "i2s_ll_macro_def.h" 19 #include <driver/i2s_types.h> 20 i2s_hal_config(const i2s_config_t * config)21bk_err_t i2s_hal_config(const i2s_config_t *config) 22 { 23 i2s_ll_set_reg0x0_i2spcmen(config->i2s_en); 24 i2s_ll_set_reg0x0_msten(config->role); 25 i2s_ll_set_reg0x0_modesel(config->work_mode); 26 i2s_ll_set_reg0x0_lrckrp(config->lrck_invert); 27 i2s_ll_set_reg0x0_sclkinv(config->sck_invert); 28 i2s_ll_set_reg0x0_lsbfirst(config->lsb_first_en); 29 i2s_ll_set_reg0x0_synclen(config->sync_length); 30 i2s_ll_set_reg0x0_datalen(config->data_length); 31 i2s_ll_set_reg0x0_pcm_dlen(config->pcm_dlength); 32 i2s_ll_set_reg0x0_smpratio(config->sample_ratio); 33 i2s_ll_set_reg0x0_bitratio(config->sck_ratio); 34 35 i2s_ll_set_reg0x1_parallel_en(config->parallel_en); 36 i2s_ll_set_reg0x1_lrcom_store(config->store_mode); 37 i2s_ll_set_reg0x1_bitratio_h4b(config->sck_ratio_h4b); 38 i2s_ll_set_reg0x1_smpratio_h2b(config->sample_ratio_h2b); 39 i2s_ll_set_reg0x1_txint_level(config->txint_level); 40 i2s_ll_set_reg0x1_rxint_level(config->rxint_level); 41 42 return BK_OK; 43 } 44 i2s_hal_deconfig(void)45bk_err_t i2s_hal_deconfig(void) 46 { 47 i2s_ll_set_reg0x0_value(0); 48 i2s_ll_set_reg0x1_value(0); 49 i2s_ll_set_reg0x3_value(0); 50 i2s_ll_set_reg0x4_value(0); 51 i2s_ll_set_reg0x5_rx2ovf(1); 52 i2s_ll_set_reg0x5_tx2udf(1); 53 i2s_ll_set_reg0x6_value(0); 54 i2s_ll_set_reg0x7_value(0); 55 i2s_ll_set_reg0x8_value(0); 56 57 return BK_OK; 58 } 59 i2s_hal_int_status_get(i2s_int_status_t * int_status)60bk_err_t i2s_hal_int_status_get(i2s_int_status_t *int_status) 61 { 62 switch(int_status->channel_id) 63 { 64 case I2S_CHANNEL_1: 65 int_status->tx_udf = (bool)i2s_ll_get_reg0x2_txudf(); 66 int_status->rx_ovf = (bool)i2s_ll_get_reg0x2_rxovf(); 67 int_status->tx_int = (bool)i2s_ll_get_reg0x2_txint(); 68 int_status->rx_int = (bool)i2s_ll_get_reg0x2_rxint(); 69 break; 70 case I2S_CHANNEL_2: 71 int_status->tx_udf = (bool)i2s_ll_get_reg0x5_tx2udf(); 72 int_status->rx_ovf = (bool)i2s_ll_get_reg0x5_rx2ovf(); 73 int_status->tx_int = (bool)i2s_ll_get_reg0x5_tx2int(); 74 int_status->rx_int = (bool)i2s_ll_get_reg0x5_rx2int(); 75 break; 76 case I2S_CHANNEL_3: 77 int_status->tx_udf = (bool)i2s_ll_get_reg0x5_tx3udf(); 78 int_status->rx_ovf = (bool)i2s_ll_get_reg0x5_rx3ovf(); 79 int_status->tx_int = (bool)i2s_ll_get_reg0x5_tx3int(); 80 int_status->rx_int = (bool)i2s_ll_get_reg0x5_rx3int(); 81 break; 82 case I2S_CHANNEL_4: 83 int_status->tx_udf = (bool)i2s_ll_get_reg0x5_tx4udf(); 84 int_status->rx_ovf = (bool)i2s_ll_get_reg0x5_rx4ovf(); 85 int_status->tx_int = (bool)i2s_ll_get_reg0x5_tx4int(); 86 int_status->rx_int = (bool)i2s_ll_get_reg0x5_rx4int(); 87 break; 88 default: 89 break; 90 } 91 92 return BK_OK; 93 } 94 i2s_hal_read_ready_get(uint32_t * read_flag)95bk_err_t i2s_hal_read_ready_get(uint32_t *read_flag) 96 { 97 *read_flag = i2s_ll_get_reg0x2_rxfifo_rd_ready(); 98 return BK_OK; 99 } 100 i2s_hal_write_ready_get(uint32_t * write_flag)101bk_err_t i2s_hal_write_ready_get(uint32_t *write_flag) 102 { 103 *write_flag = i2s_ll_get_reg0x2_txfifo_wr_ready(); 104 return BK_OK; 105 } 106 i2s_hal_en_set(uint32_t value)107bk_err_t i2s_hal_en_set(uint32_t value) 108 { 109 i2s_ll_set_reg0x0_i2spcmen(value); 110 return BK_OK; 111 } 112 i2s_hal_int_set(i2s_isr_id_t int_id,uint32_t value)113bk_err_t i2s_hal_int_set(i2s_isr_id_t int_id, uint32_t value) 114 { 115 switch(int_id) 116 { 117 case I2S_ISR_CHL1_TXUDF: 118 i2s_ll_set_reg0x1_txudf_en(value); 119 break; 120 case I2S_ISR_CHL1_RXOVF: 121 i2s_ll_set_reg0x1_rxovf_en(value); 122 break; 123 124 case I2S_ISR_CHL1_TXINT: 125 i2s_ll_set_reg0x1_txint_en(value); 126 break; 127 case I2S_ISR_CHL1_RXINT: 128 i2s_ll_set_reg0x1_rxint_en(value); 129 break; 130 131 case I2S_ISR_CHL2_TXUDF: 132 i2s_ll_set_reg0x4_tx2udf_en(value); 133 break; 134 case I2S_ISR_CHL2_RXOVF: 135 i2s_ll_set_reg0x4_rx2ovf_en(value); 136 break; 137 case I2S_ISR_CHL2_TXINT: 138 i2s_ll_set_reg0x4_tx2int_en(value); 139 break; 140 case I2S_ISR_CHL2_RXINT: 141 i2s_ll_set_reg0x4_rx2int_en(value); 142 break; 143 144 case I2S_ISR_CHL3_TXUDF: 145 i2s_ll_set_reg0x4_tx3udf_en(value); 146 break; 147 case I2S_ISR_CHL3_RXOVF: 148 i2s_ll_set_reg0x4_rx3ovf_en(value); 149 break; 150 case I2S_ISR_CHL3_TXINT: 151 i2s_ll_set_reg0x4_tx3int_en(value); 152 break; 153 case I2S_ISR_CHL3_RXINT: 154 i2s_ll_set_reg0x4_rx3int_en(value); 155 break; 156 157 case I2S_ISR_CHL4_TXUDF: 158 i2s_ll_set_reg0x4_tx4udf_en(value); 159 break; 160 case I2S_ISR_CHL4_RXOVF: 161 i2s_ll_set_reg0x4_rx4ovf_en(value); 162 break; 163 case I2S_ISR_CHL4_TXINT: 164 i2s_ll_set_reg0x4_tx4int_en(value); 165 break; 166 case I2S_ISR_CHL4_RXINT: 167 i2s_ll_set_reg0x4_rx4int_en(value); 168 break; 169 170 default: 171 break; 172 } 173 174 return BK_OK; 175 } 176 i2s_hal_role_set(uint32_t value)177bk_err_t i2s_hal_role_set(uint32_t value) 178 { 179 i2s_ll_set_reg0x0_msten(value); 180 return BK_OK; 181 } 182 i2s_hal_work_mode_set(uint32_t value)183bk_err_t i2s_hal_work_mode_set(uint32_t value) 184 { 185 i2s_ll_set_reg0x0_modesel(value); 186 return BK_OK; 187 } 188 i2s_hal_lrck_invert_set(uint32_t value)189bk_err_t i2s_hal_lrck_invert_set(uint32_t value) 190 { 191 i2s_ll_set_reg0x0_lrckrp(value); 192 return BK_OK; 193 } 194 i2s_hal_sck_invert_set(uint32_t value)195bk_err_t i2s_hal_sck_invert_set(uint32_t value) 196 { 197 i2s_ll_set_reg0x0_sclkinv(value); 198 return BK_OK; 199 } 200 i2s_hal_lsb_first_set(uint32_t value)201bk_err_t i2s_hal_lsb_first_set(uint32_t value) 202 { 203 i2s_ll_set_reg0x0_lsbfirst(value); 204 return BK_OK; 205 } 206 i2s_hal_sync_len_set(uint32_t value)207bk_err_t i2s_hal_sync_len_set(uint32_t value) 208 { 209 i2s_ll_set_reg0x0_synclen(value); 210 return BK_OK; 211 } 212 i2s_hal_data_len_set(uint32_t value)213bk_err_t i2s_hal_data_len_set(uint32_t value) 214 { 215 i2s_ll_set_reg0x0_datalen(value); 216 return BK_OK; 217 } 218 i2s_hal_pcm_dlen_set(uint32_t value)219bk_err_t i2s_hal_pcm_dlen_set(uint32_t value) 220 { 221 i2s_ll_set_reg0x0_pcm_dlen(value); 222 return BK_OK; 223 } 224 i2s_hal_store_mode_set(uint32_t value)225bk_err_t i2s_hal_store_mode_set(uint32_t value) 226 { 227 i2s_ll_set_reg0x1_lrcom_store(value); 228 return BK_OK; 229 } 230 i2s_hal_rxfifo_clear(void)231bk_err_t i2s_hal_rxfifo_clear(void) 232 { 233 i2s_ll_set_reg0x1_rxfifo_clr(1); 234 return BK_OK; 235 } 236 i2s_hal_txfifo_clear(void)237bk_err_t i2s_hal_txfifo_clear(void) 238 { 239 i2s_ll_set_reg0x1_txfifo_clr(1); 240 return BK_OK; 241 } 242 i2s_hal_txudf_int_clear(i2s_channel_id_t channel_id)243bk_err_t i2s_hal_txudf_int_clear(i2s_channel_id_t channel_id) 244 { 245 switch (channel_id) 246 { 247 case I2S_CHANNEL_1: 248 i2s_ll_set_reg0x2_txudf(1); 249 break; 250 case I2S_CHANNEL_2: 251 i2s_ll_set_reg0x5_tx2udf(1); 252 break; 253 case I2S_CHANNEL_3: 254 i2s_ll_set_reg0x5_tx3udf(1); 255 break; 256 case I2S_CHANNEL_4: 257 i2s_ll_set_reg0x5_tx4udf(1); 258 break; 259 default: 260 break; 261 } 262 263 return BK_OK; 264 } 265 i2s_hal_rxovf_int_clear(i2s_channel_id_t channel_id)266bk_err_t i2s_hal_rxovf_int_clear(i2s_channel_id_t channel_id) 267 { 268 switch (channel_id) 269 { 270 case I2S_CHANNEL_1: 271 i2s_ll_set_reg0x2_rxovf(1); 272 break; 273 case I2S_CHANNEL_2: 274 i2s_ll_set_reg0x5_rx2ovf(1); 275 break; 276 case I2S_CHANNEL_3: 277 i2s_ll_set_reg0x5_rx3ovf(1); 278 break; 279 case I2S_CHANNEL_4: 280 i2s_ll_set_reg0x5_rx4ovf(1); 281 break; 282 default: 283 break; 284 } 285 286 return BK_OK; 287 } 288 i2s_hal_txint_level_set(uint32_t value)289bk_err_t i2s_hal_txint_level_set(uint32_t value) 290 { 291 i2s_ll_set_reg0x1_txint_level(value); 292 return BK_OK; 293 } 294 i2s_hal_rxint_level_set(uint32_t value)295bk_err_t i2s_hal_rxint_level_set(uint32_t value) 296 { 297 i2s_ll_set_reg0x1_rxint_level(value); 298 return BK_OK; 299 } 300 i2s_hal_data_write(uint32_t channel_id,uint32_t value)301bk_err_t i2s_hal_data_write(uint32_t channel_id, uint32_t value) 302 { 303 switch(channel_id) 304 { 305 case 1: 306 i2s_ll_set_reg0x3_i2s_dat(value); 307 break; 308 case 2: 309 i2s_ll_set_reg0x6_value(value); 310 break; 311 case 3: 312 i2s_ll_set_reg0x7_value(value); 313 break; 314 case 4: 315 i2s_ll_set_reg0x8_value(value); 316 break; 317 default: 318 break; 319 } 320 321 return BK_OK; 322 } 323 i2s_hal_data_read(uint32_t * value)324bk_err_t i2s_hal_data_read(uint32_t *value) 325 { 326 *value = i2s_ll_get_reg0x3_i2s_dat(); 327 return BK_OK; 328 } 329 i2s_hal_sample_ratio_set(uint32_t value)330bk_err_t i2s_hal_sample_ratio_set(uint32_t value) 331 { 332 i2s_ll_set_reg0x0_smpratio(value); 333 return BK_OK; 334 } 335 i2s_hal_sck_ratio_set(uint32_t value)336bk_err_t i2s_hal_sck_ratio_set(uint32_t value) 337 { 338 i2s_ll_set_reg0x0_bitratio(value); 339 return BK_OK; 340 } 341 i2s_hal_sample_ratio_h2b_set(uint32_t value)342bk_err_t i2s_hal_sample_ratio_h2b_set(uint32_t value) 343 { 344 i2s_ll_set_reg0x1_smpratio_h2b(value); 345 return BK_OK; 346 } 347 i2s_hal_sck_ratio_h4b_set(uint32_t value)348bk_err_t i2s_hal_sck_ratio_h4b_set(uint32_t value) 349 { 350 i2s_ll_set_reg0x1_bitratio_h4b(value); 351 return BK_OK; 352 } 353 354