1 /*
2 // Copyright (C) 2022 Beken Corporation
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15 #include <common/bk_include.h>
16 #include "bk_arm_arch.h"
17 #include <common/bk_typedef.h>
18 #include "i2s.h"
19 #include "bk_i2s.h"
20 #include "bk_gpio.h"
21 #include "bk_drv_model.h"
22 #include <driver/int.h>
23 #include "bk_icu.h"
24 #include "bk_music_msg.h"
25 #include "bk_driver_audio.h"
26 #include "bk_uart.h"
27 #include <common/sys_config.h>
28 #include <common/bk_kernel_err.h>
29 #include <os/os.h>
30 #include <os/mem.h>
31 #include "bk_misc.h"
32 #include "bk_sys_ctrl.h"
33 #include "sys_ctrl.h"
34 #include "sys_driver.h"
35 #include <common/bk_generic.h>
36
37 #if CONFIG_I2S
38
39 #define RT_I2S_BIT_DEBUG
40 #ifdef RT_I2S_BIT_DEBUG
41 #define bit_dbg(fmt, ...) BK_LOG_RAW(fmt, ##__VA_ARGS__)
42 #else
43 #define bit_dbg(fmt, ...)
44 #endif
45
46 struct bk_i2s_dev {
47 UINT8 *tx_ptr;
48 UINT32 tx_len;
49 beken_semaphore_t tx_sem;
50
51 UINT8 *rx_ptr;
52 UINT32 rx_len;
53 UINT32 rx_offset;
54 UINT32 rx_drop;
55
56 UINT32 total_len;
57 UINT32 flag;
58
59 beken_mutex_t mutex;
60 };
61
62 volatile i2s_trans_t i2s_trans;
63 i2s_level_t i2s_fifo_level;
64
65 #if (!CONFIG_SOC_BK7271)
66 static UINT32 i2s_ctrl(UINT32 cmd, void *param);
67
68 static const DD_OPERATIONS i2s_op = {
69 NULL,
70 NULL,
71 NULL,
72 NULL,
73 i2s_ctrl
74 };
75
i2s_active(UINT8 enable)76 static void i2s_active(UINT8 enable)
77 {
78 UINT32 value_ctrl;
79
80 value_ctrl = REG_READ(PCM_CTRL);
81
82 if (enable)
83 value_ctrl |= I2S_PCM_EN;
84 else
85 value_ctrl &= ~I2S_PCM_EN;
86
87 REG_WRITE(PCM_CTRL, value_ctrl);
88 }
89
i2s_set_msten(UINT8 enable)90 static void i2s_set_msten(UINT8 enable)
91 {
92 UINT32 value_ctrl;
93
94 value_ctrl = REG_READ(PCM_CTRL);
95
96 if (enable)
97 value_ctrl |= MSTEN;
98 else
99 value_ctrl &= (~MSTEN);
100
101 REG_WRITE(PCM_CTRL, value_ctrl);
102 }
103
i2s_select_mode(UINT8 val)104 static void i2s_select_mode(UINT8 val)
105 {
106 UINT32 value;
107
108 if (val == 3 || val > 7)
109 return;
110
111 value = REG_READ(PCM_CTRL);
112 value &= ~(MODE_SEL_MASK << MODE_SEL_POSI);
113 value |= (val << MODE_SEL_POSI);
114 REG_WRITE(PCM_CTRL, value);
115 }
116
i2s_set_lrck(UINT8 val)117 static void i2s_set_lrck(UINT8 val)
118 {
119 UINT32 value;
120
121 value = REG_READ(PCM_CTRL);
122 if (val)
123 value |= LRCK_RP;
124 else
125 value &= ~LRCK_RP;
126 REG_WRITE(PCM_CTRL, value);
127 }
128
i2s_set_sck_inv(UINT8 val)129 static void i2s_set_sck_inv(UINT8 val)
130 {
131 UINT32 value;
132
133 value = REG_READ(PCM_CTRL);
134
135 if (val)
136 value |= SCK_INV;
137 else
138 value &= ~SCK_INV;
139
140 REG_WRITE(PCM_CTRL, value);
141 }
142
i2s_set_sck_lsb(UINT8 val)143 static void i2s_set_sck_lsb(UINT8 val)
144 {
145 UINT32 value;
146
147 value = REG_READ(PCM_CTRL);
148 if (val)
149 value |= LSB_FIRST;
150 else
151 value &= ~LSB_FIRST;
152 REG_WRITE(PCM_CTRL, value);
153 }
154
i2s_set_sck_synclen(UINT8 val)155 static void i2s_set_sck_synclen(UINT8 val)
156 {
157 UINT32 value;
158
159 value = REG_READ(PCM_CTRL);
160 value &= ~ SYNCLEN_MASK;
161 value |= (val << SYNCLEN_POSI);
162 REG_WRITE(PCM_CTRL, value);
163 }
164
i2s_set_pcm_dlen(UINT8 val)165 static void i2s_set_pcm_dlen(UINT8 val)
166 {
167 UINT32 value;
168
169 value = REG_READ(PCM_CTRL);
170 value &= ~ PCM_DLEN_MASK;
171 value |= (val << PCM_DLEN_POSI);
172 REG_WRITE(PCM_CTRL, value);
173 }
174
i2s_set_freq_datawidth(i2s_rate_t * p_rate)175 static void i2s_set_freq_datawidth(i2s_rate_t *p_rate)
176 {
177 UINT32 bitratio, value = 0, lrck_div, sys_clk = 0;
178
179 if ((p_rate->freq != 8000) && (p_rate->freq != 16000) &&
180 (p_rate->freq != 24000) && (p_rate->freq != 32000) && (p_rate->freq != 48000) &&
181 (p_rate->freq != 11025) && (p_rate->freq != 22050) && (p_rate->freq != 44100))
182 return;
183
184 /*set irck div*/
185 if (p_rate->datawidth == 8)
186 lrck_div = 7;
187 else if (p_rate->datawidth == 16)
188 lrck_div = 15;
189 else if (p_rate->datawidth == 24)
190 lrck_div = 23;
191 else
192 lrck_div = 31;
193
194 /*set system clock*/
195 if (p_rate->freq == 8000) {
196 if (p_rate->datawidth == 24) {
197 sys_clk = 48384000;
198 sddev_control(DD_DEV_TYPE_SCTRL, CMD_SCTRL_AUDIO_PLL, &sys_clk);
199 } else {
200 sys_clk = 48128000;
201 sddev_control(DD_DEV_TYPE_SCTRL, CMD_SCTRL_AUDIO_PLL, &sys_clk);
202 }
203 } else if (p_rate->freq == 16000) {
204 if ((p_rate->datawidth == 16) || (p_rate->datawidth == 8)) {
205 sys_clk = 48128000;
206 sddev_control(DD_DEV_TYPE_SCTRL, CMD_SCTRL_AUDIO_PLL, &sys_clk);
207 } else {
208 sys_clk = 49152000;
209 sddev_control(DD_DEV_TYPE_SCTRL, CMD_SCTRL_AUDIO_PLL, &sys_clk);
210 }
211 } else if (p_rate->freq == 44100) {
212 sys_clk = 50803200;
213 sddev_control(DD_DEV_TYPE_SCTRL, CMD_SCTRL_AUDIO_PLL, &sys_clk);
214 } else {
215 if (p_rate->datawidth == 24) {
216 sys_clk = 50688000;
217 sddev_control(DD_DEV_TYPE_SCTRL, CMD_SCTRL_AUDIO_PLL, &sys_clk);
218 } else {
219 sys_clk = 49152000;
220 sddev_control(DD_DEV_TYPE_SCTRL, CMD_SCTRL_AUDIO_PLL, &sys_clk);
221 }
222 }
223
224 /*set bit clock divd*/
225 bitratio = MAX((NUMBER_ROUND_UP((sys_clk / 2), (p_rate->freq * 2 * (lrck_div + 1))) - 1), 5);
226 value = value | ((p_rate->datawidth - 1) << DATALEN_POSI)
227 | (lrck_div << SMPRATIO_POSI)
228 | (bitratio << BITRATIO_POSI);//this value is unused in slave mode
229
230 REG_WRITE(PCM_CTRL, value);
231 }
232
i2s_rxint_enable(UINT8 val)233 static void i2s_rxint_enable(UINT8 val)
234 {
235 UINT32 value;
236
237 value = REG_READ(PCM_CN);
238 if (val)
239 value |= RX_INT_EN;
240 else
241 value &= ~RX_INT_EN;
242 REG_WRITE(PCM_CN, value);
243 }
244
i2s_txint_enable(UINT8 val)245 static void i2s_txint_enable(UINT8 val)
246 {
247 UINT32 value;
248
249 value = REG_READ(PCM_CN);
250 if (val)
251 value |= TX_INT0_EN;
252 else
253 value &= ~TX_INT0_EN;
254 REG_WRITE(PCM_CN, value);
255 }
256
i2s_rxovr_enable(UINT8 val)257 static void i2s_rxovr_enable(UINT8 val)
258 {
259 UINT32 value;
260
261 value = REG_READ(PCM_CN);
262 if (val)
263 value |= RX_OVF_EN;
264 else
265 value &= ~RX_OVF_EN;
266 REG_WRITE(PCM_CN, value);
267 }
268
i2s_txovr_enable(UINT8 val)269 static void i2s_txovr_enable(UINT8 val)
270 {
271 UINT32 value;
272
273 value = REG_READ(PCM_CN);
274 if (val)
275 value |= TX_UDF0_EN;
276 else
277 value &= ~TX_UDF0_EN;
278 REG_WRITE(PCM_CN, value);
279 }
280
281
i2s_rxint_mode(UINT8 val)282 static void i2s_rxint_mode(UINT8 val)
283 {
284 UINT32 value;
285
286 value = REG_READ(PCM_CN);
287
288 value &= ~(RX_FIFO_LEVEL_MASK << RX_FIFO_LEVEL_POSI) ;
289 value |= ((val & RX_FIFO_LEVEL_MASK) << RX_FIFO_LEVEL_POSI);
290
291 REG_WRITE(PCM_CN, value);
292 }
293
i2s_txint_mode(UINT8 val)294 static void i2s_txint_mode(UINT8 val)
295 {
296 UINT32 value;
297
298 value = REG_READ(PCM_CN);
299
300 value &= ~(RX_FIFO_LEVEL_MASK << TX_FIFO0_LEVEL_POSI) ;
301 value |= ((val & RX_FIFO_LEVEL_MASK) << TX_FIFO0_LEVEL_POSI);
302
303 REG_WRITE(PCM_CN, value);
304 }
305
i2s_rxfifo_clr_enable(void)306 static void i2s_rxfifo_clr_enable(void)
307 {
308 UINT32 value;
309
310 value = REG_READ(PCM_CN);
311 value |= RX_FIFO_CLR;
312
313 REG_WRITE(PCM_CN, value);
314 }
315
i2s_txfifo_clr_enable(void)316 static void i2s_txfifo_clr_enable(void)
317 {
318 UINT32 value;
319
320 value = REG_READ(PCM_CN);
321 value = value | TX_FIFO0_CLR | TX_FIFO1_CLR | TX_FIFO2_CLR;
322
323 REG_WRITE(PCM_CN, value);
324 }
325
i2s_icu_configuration(UINT32 enable)326 static void i2s_icu_configuration(UINT32 enable)
327 {
328 UINT32 param;
329
330 if (enable) {
331 param = PWD_I2S_PCM_CLK_BIT;
332 sddev_control(DD_DEV_TYPE_ICU, CMD_CLK_PWR_UP, ¶m);
333
334 param = (IRQ_I2S_PCM_BIT);
335 // sddev_control(DD_DEV_TYPE_ICU, CMD_ICU_INT_ENABLE, ¶m);
336 (void)sys_drv_int_enable(param);
337 } else {
338 param = (IRQ_I2S_PCM_BIT);
339 // sddev_control(DD_DEV_TYPE_ICU, CMD_ICU_INT_DISABLE, ¶m);
340 (void)sys_drv_int_disable(param);
341
342 param = PWD_I2S_PCM_CLK_BIT;
343 sddev_control(DD_DEV_TYPE_ICU, CMD_CLK_PWR_DOWN, ¶m);
344 }
345 }
346
i2s_gpio_configuration()347 static void i2s_gpio_configuration()
348 {
349 uint32_t val;
350 val = GFUNC_MODE_I2S; /*gpio 2-5*/
351 sddev_control(DD_DEV_TYPE_GPIO, CMD_GPIO_ENABLE_SECOND, &val);
352 }
353
i2s_get_busy(void)354 static UINT8 i2s_get_busy(void)
355 {
356 //TODO
357 return 0;
358 }
359
i2s_master_enable(UINT32 enable)360 static void i2s_master_enable(UINT32 enable)
361 {
362 UINT32 value, ultemp;
363
364 ultemp = 1;
365
366 value = REG_READ(PCM_CN);
367 value = value | (RX_INT_EN | TX_INT0_EN);
368 REG_WRITE(PCM_CN, value);
369
370 /* enable i2s unit */
371 i2s_ctrl(I2S_CMD_UNIT_ENABLE, (void *) &ultemp);
372
373 /* 1:MASTER 0:SLAVE */
374 if (enable)
375 i2s_ctrl(I2S_CMD_SET_MSTEN, (void *) &enable);
376 else
377 i2s_ctrl(I2S_CMD_SET_MSTEN, (void *)& enable);
378
379 bit_dbg("[-ISR-]I2S_DEBUG: pcm_ctrl=0x%X,pcm_cn =0x%08X,pcm_stat =0x%X\r\n", REG_READ(PCM_CTRL), REG_READ(PCM_CN), REG_READ(PCM_STAT));
380
381 i2s_icu_configuration(1); //enable clock;
382 }
383
i2s_dma_master_enable(UINT32 enable)384 static void i2s_dma_master_enable(UINT32 enable)
385 {
386 UINT32 value, ultemp;
387
388 ultemp = 1;
389
390 value = REG_READ(PCM_CN);
391 value = value | (RX_INT_EN | TX_INT0_EN);
392 REG_WRITE(PCM_CN, value);
393
394 /* enable i2s unit */
395 i2s_ctrl(I2S_CMD_UNIT_ENABLE, (void *) &ultemp);
396
397 /* 1:MASTER 0:SLAVE */
398 if (enable)
399 i2s_ctrl(I2S_CMD_SET_MSTEN, (void *) &enable);
400 else
401 i2s_ctrl(I2S_CMD_SET_MSTEN, (void *)& enable);
402
403 bit_dbg("[-DMA-]I2S_DEBUG: pcm_ctrl=0x%X,pcm_cn =0x%08X,pcm_stat =0x%X\r\n", REG_READ(PCM_CTRL), REG_READ(PCM_CN), REG_READ(PCM_STAT));
404
405 {
406 UINT32 param = PWD_I2S_PCM_CLK_BIT;
407 sddev_control(DD_DEV_TYPE_ICU, CMD_CLK_PWR_UP, ¶m);
408 }
409 }
410
i2s_disable_i2s(void)411 static UINT8 i2s_disable_i2s(void)
412 {
413 UINT8 param;
414 UINT32 status;
415
416 param = 0;
417 i2s_ctrl(I2S_CMD_UNIT_ENABLE, (void *)¶m);
418
419 status = REG_READ(PCM_STAT);
420
421 REG_WRITE(PCM_CTRL, 0);
422 REG_WRITE(PCM_CN, 0);
423 REG_WRITE(PCM_STAT, status);
424
425 i2s_icu_configuration(0); //disable clock;
426 return 0;
427 }
428
429 __maybe_unused static UINT32 i2s_read_rxfifo(UINT8 *data);
i2s_read_rxfifo(UINT8 * data)430 static UINT32 i2s_read_rxfifo(UINT8 *data)
431 {
432 UINT32 value;
433
434 value = REG_READ(PCM_STAT);
435
436 if ((value & RX_FIFO0_EMPTY) == 0) {
437 value = REG_READ(PCM_STAT);
438 if (data)
439 *data = value;
440 return 1;
441 }
442 return 0;
443 }
444
445 __maybe_unused static void i2s_txfifo_fill(void);
i2s_txfifo_fill(void)446 static void i2s_txfifo_fill(void)
447 {
448 UINT32 value;
449
450 value = REG_READ(PCM_STAT);
451
452 while ((value & TX_FIFO0_FULL) == 0)
453 REG_WRITE(PCM_STAT, 0xff);
454 }
455
i2s_write_txfifo(UINT8 data)456 UINT32 i2s_write_txfifo(UINT8 data)
457 {
458 UINT32 value;
459
460 value = REG_READ(PCM_STAT);
461
462 if ((value & TX_FIFO0_FULL) == 0) {
463 REG_WRITE(PCM_STAT, data);
464 return 1;
465 }
466
467 return 0;
468 }
469
470
471
i2s_init(int register_isr)472 void i2s_init(int register_isr)
473 {
474 if (register_isr)
475 bk_int_isr_register(INT_SRC_I2S, i2s_isr, NULL);
476 sddev_register_dev(DD_DEV_TYPE_I2S, (DD_OPERATIONS *)&i2s_op);
477 }
478
479
i2s_exit(void)480 void i2s_exit(void)
481 {
482 sddev_unregister_dev(DD_DEV_TYPE_I2S);
483 }
484
i2s_enable_interrupt(void)485 static void i2s_enable_interrupt(void)
486 {
487 UINT32 param;
488 param = (IRQ_I2S_PCM_BIT);
489 // sddev_control(DD_DEV_TYPE_ICU, CMD_ICU_INT_ENABLE, ¶m);
490 (void)sys_drv_int_enable(param);
491 }
492
i2s_disable_interrupt(void)493 static void i2s_disable_interrupt(void)
494 {
495 UINT32 param;
496 param = (IRQ_I2S_PCM_BIT);
497 // sddev_control(DD_DEV_TYPE_ICU, CMD_ICU_INT_DISABLE, ¶m);
498 (void)sys_drv_int_disable(param);
499 }
500
501
502
i2s_ctrl(UINT32 cmd,void * param)503 static UINT32 i2s_ctrl(UINT32 cmd, void *param)
504 {
505 UINT8 ret = I2S_SUCCESS;
506
507 //peri_busy_count_add();
508
509
510 switch (cmd) {
511 case I2S_CMD_UNIT_ENABLE:
512 i2s_active(*(UINT8 *)param);
513 break;
514 case I2S_CMD_SET_MSTEN:
515 i2s_set_msten(*(UINT8 *)param);
516 break;
517 case I2S_CMD_SELECT_MODE:
518 i2s_select_mode(*(UINT8 *)param);
519 break;
520 case I2S_CMD_SET_LRCK:
521 i2s_set_lrck(*(UINT8 *)param);
522 break;
523 case I2S_CMD_SET_SCK_INV:
524 i2s_set_sck_inv(*(UINT8 *)param);
525 break;
526 case I2S_CMD_SET_SCK_LSB:
527 i2s_set_sck_lsb(*(UINT8 *)param);
528 break;
529 case I2S_CMD_SET_SCK_SYNCLEN:
530 i2s_set_sck_synclen(*(UINT8 *)param);
531 break;
532 case I2S_CMD_SET_PCM_DLEN:
533 i2s_set_pcm_dlen(*(UINT8 *)param);
534 break;
535 case I2S_CMD_SET_FREQ_DATAWIDTH:
536 i2s_set_freq_datawidth((i2s_rate_t *)param);
537 break;
538 case I2S_CMD_RXINT_EN:
539 i2s_rxint_enable(*(UINT8 *)param);
540 break;
541 case I2S_CMD_TXINT_EN:
542 i2s_txint_enable(*(UINT8 *)param);
543 break;
544 case I2S_CMD_RXOVR_EN:
545 i2s_rxovr_enable(*(UINT8 *)param);
546 break;
547 case I2S_CMD_TXOVR_EN:
548 i2s_txovr_enable(*(UINT8 *)param);
549 break;
550 case I2S_CMD_RXFIFO_CLR_EN:
551 i2s_rxfifo_clr_enable();
552 break;
553 case I2S_CMD_TXFIFO_CLR_EN:
554 i2s_txfifo_clr_enable();
555 break;
556 case I2S_CMD_RXINT_MODE:
557 i2s_rxint_mode(*(UINT8 *)param);
558 break;
559 case I2S_CMD_TXINT_MODE:
560 i2s_txint_mode(*(UINT8 *)param);
561 break;
562 case I2S_CMD_GET_BUSY:
563 i2s_get_busy();
564 break;
565 case I2S_CMD_ENABLE_INTERRUPT:
566 i2s_enable_interrupt();
567 break;
568 case I2S_CMD_DISABLE_INTERRUPT:
569 i2s_disable_interrupt();
570 break;
571 case I2S_CMD_MASTER_ENABLE:
572 i2s_master_enable(*(UINT32 *)param);
573 break;
574 case I2S_CMD_DISABLE_I2S:
575 i2s_disable_i2s();
576 break;
577 case I2S_CMD_DMA_MASTER_ENABLE:
578 i2s_dma_master_enable(*(UINT32 *)param);
579 break;
580 case I2S_CMD_DMA_ISR:
581 bk_int_isr_register(INT_SRC_I2S, (FUNCPTR)param, NULL);
582 break;
583
584 default:
585 ret = I2S_FAILURE;
586 break;
587 }
588
589 // peri_busy_count_dec();
590
591 return ret;
592 }
593
594
i2s_configure(UINT32 fifo_level,UINT32 sample_rate,UINT32 bits_per_sample,UINT32 mode)595 UINT32 i2s_configure(UINT32 fifo_level, UINT32 sample_rate, UINT32 bits_per_sample, UINT32 mode)
596 {
597 UINT32 param;
598 i2s_rate_t rate;
599 rate.datawidth = bits_per_sample;
600 rate.freq = sample_rate;
601 /*
602 mode:
603 bit0~2: mode & 0x7 000:I2S
604 001:Left Justified
605 010:Right Justified
606 011:reserve
607 100:Short Frame Sync
608 101:Long Frame Sync
609 110:Normal 2B+D
610 111:Delay 2B+D
611
612 bit3: mode & 0x08 0:LRCK no turn
613 1:LRCK turn
614
615 bit4: mode & 0x10 0:SCK no turn
616 1:SCK turn
617
618 bit5: mode & 0x20 0:MSB first send/receive
619 1:LSB first send/receive
620
621 bit8~10: mode & 0x700 0~7:Sync length only Long Frame Sync effective
622
623 bit12~14: mode & 0x7000 0~7: 2B+D PCM :D length
624
625 */
626 /* set work mode */
627 param = (mode & 0x7) ;
628 i2s_ctrl(I2S_CMD_SELECT_MODE, (void *)¶m); // i2s mode set
629
630 /* set lrckrp */
631 param = (mode & 0x8);
632 i2s_ctrl(I2S_CMD_SET_LRCK, (void *)¶m);
633
634 /* set sclkinv */
635 param = (mode & 0x10);
636 i2s_ctrl(I2S_CMD_SET_SCK_INV, (void *)¶m);
637
638 /* set lsbfirst */
639 param = (mode & 0x20);
640 i2s_ctrl(I2S_CMD_SET_SCK_LSB, (void *)¶m);
641
642 /* set synclen */
643 param = (mode & 0x700);
644 param = param >> 8;
645 i2s_ctrl(I2S_CMD_SET_SCK_SYNCLEN, (void *)¶m);
646
647 /* set pcm_dlen */
648 param = (mode & 0x7000);
649 param = param >> 12;
650 i2s_ctrl(I2S_CMD_SET_PCM_DLEN, (void *)¶m);
651
652 /* set txfifo level */
653 param = fifo_level;
654 i2s_ctrl(I2S_CMD_TXINT_MODE, (void *)¶m);
655
656 /* set rxfifo level */
657 param = fifo_level;
658 i2s_ctrl(I2S_CMD_RXINT_MODE, (void *)¶m);
659
660 /* enable txover int */
661 param = 1;
662 i2s_ctrl(I2S_CMD_TXOVR_EN, (void *)¶m);
663
664 /* enable rxover int */
665 param = 1;
666 i2s_ctrl(I2S_CMD_RXOVR_EN, (void *)¶m);
667
668 i2s_gpio_configuration(); //set gpio
669
670 param = REG_READ(SCTRL_BLOCK_EN_CFG);
671 param = (param & (~(0x0FFFUL << 20))) | (BLOCK_EN_WORD_PWD << 20) | (1 << 16) | (1 << 17);
672 REG_WRITE(SCTRL_BLOCK_EN_CFG, param); // audio pll audio enable
673
674 #if (CONFIG_SOC_BK7256XX)
675 //sys_drv_analog_reg6_set(param);// to do,need remove old interface after all adaption is finished
676 sys_drv_set_dpll_for_i2s();
677 #else
678 sddev_control(DD_DEV_TYPE_SCTRL, CMD_SCTRL_SET_ANALOG6, NULL);// DPLL AUDIO OPEN, DPLL divider
679 #endif
680
681 /* set freq_datawidth */
682 i2s_ctrl(I2S_CMD_SET_FREQ_DATAWIDTH, (void *)&rate);
683
684 /* clear state */
685 REG_WRITE(PCM_STAT, 0x0000FFFF);
686
687 bit_dbg("[---]I2S_CONF:PCM_CTRL = 0x%x\n", REG_READ(PCM_CTRL));
688 bit_dbg("[---]I2S_CONF:PCM_CN = 0x%x\n", REG_READ(PCM_CN));
689
690 return I2S_SUCCESS;
691 }
692
i2s_close(void)693 UINT32 i2s_close(void)
694 {
695 UINT32 param = 0;
696
697 i2s_icu_configuration(0); //close clock;
698
699 i2s_ctrl(I2S_CMD_DISABLE_INTERRUPT, (void *)¶m);
700 i2s_ctrl(I2S_CMD_UNIT_ENABLE, (void *)¶m);
701
702
703 return I2S_SUCCESS;
704 }
705
706
i2s_transfer(UINT32 * i2s_send_buf,UINT32 * i2s_recv_buf,UINT32 count,UINT32 param)707 UINT32 i2s_transfer(UINT32 *i2s_send_buf, UINT32 *i2s_recv_buf, UINT32 count, UINT32 param)
708 {
709 GLOBAL_INT_DECLARATION();
710
711 GLOBAL_INT_DISABLE();
712 i2s_trans.trans_done = 0;
713 i2s_trans.tx_remain_data_cnt = count;
714 i2s_trans.rx_remain_data_cnt = count;
715 i2s_trans.p_tx_buf = (UINT32 *) i2s_send_buf;
716 i2s_trans.p_rx_buf = (UINT32 *) i2s_recv_buf;
717 i2s_fifo_level.tx_level = FIFO_LEVEL_32;
718 i2s_fifo_level.rx_level = FIFO_LEVEL_32;
719 GLOBAL_INT_RESTORE();
720
721 if (param)
722 delay_ms(1000);
723
724 /* rxfifo clear enable*/
725 //i2s_ctrl(I2S_CMD_RXFIFO_CLR_EN, NULL);
726
727 /* enable */
728 i2s_ctrl(I2S_CMD_MASTER_ENABLE, (void *)¶m);
729
730 while (!i2s_trans.trans_done) {
731 }
732
733 delay_ms(1000);
734 i2s_trans.trans_done = 0;
735
736 i2s_ctrl(I2S_CMD_DISABLE_I2S, NULL);
737
738 return i2s_trans.trans_done;
739 }
740
i2s_isr(void)741 void i2s_isr(void)
742 {
743 uint16_t i, rxint, txint0, ultemp;
744 uint32_t i2s_status;
745 volatile uint16_t data_num ;
746
747 i2s_status = REG_READ(PCM_STAT);
748 rxint = i2s_status & 0x01;
749 txint0 = i2s_status & 0x02;
750
751 if (txint0) {
752 switch (i2s_fifo_level.tx_level) {
753 case 0 :
754 data_num = 8;
755 break;
756 case 1 :
757 data_num = 16;
758 break;
759 case 2 :
760 data_num = 32;
761 break;
762 default :
763 data_num = 48;
764 break;
765 }
766
767 if (i2s_trans.p_tx_buf == NULL) {
768 for (i = 0; i < data_num; i++)
769 REG_WRITE(PCM_DAT0, 0xEEEEEEEE);
770 } else {
771 for (i = 0; i < data_num; i ++) {
772 REG_WRITE(PCM_DAT0, *i2s_trans.p_tx_buf);
773 i2s_trans.p_tx_buf ++;
774 }
775 }
776 i2s_status |= 0x2;
777 }
778
779 if (rxint) {
780 switch (i2s_fifo_level.rx_level) {
781 case 0 :
782 data_num = 8;
783 break;
784 case 1 :
785 data_num = 16;
786 break;
787 case 2 :
788 data_num = 32;
789 break;
790 default :
791 data_num = 48;
792 break;
793 }
794
795 if (data_num > i2s_trans.rx_remain_data_cnt)
796 data_num = i2s_trans.rx_remain_data_cnt;
797
798 if ((i2s_trans.p_rx_buf == NULL) || (i2s_status & RX_FIFO0_EMPTY)) {
799 for (i = 0; i < data_num; i++) {
800 ultemp = REG_READ(PCM_DAT0);
801 (void) ultemp;
802 }
803 } else {
804 for (i = 0; i < data_num; i++) {
805 *i2s_trans.p_rx_buf = REG_READ(PCM_DAT0);
806 i2s_trans.p_rx_buf++;
807 }
808
809 i2s_trans.rx_remain_data_cnt -= data_num;
810
811 if (i2s_trans.rx_remain_data_cnt <= 0) {
812 i = 0;
813 i2s_trans.trans_done = 1;
814 i2s_ctrl(I2S_CMD_TXINT_EN, (void *)&i);
815 i2s_ctrl(I2S_CMD_RXINT_EN, (void *)&i);
816 }
817 }
818 i2s_status |= 0x1;
819 }
820
821 REG_WRITE(PCM_STAT, i2s_status);
822
823 }
824 #endif
825 #endif
826 // eof
827
828