1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 #include "mp_precomp.h"
27 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
28 #if RT_PLATFORM == PLATFORM_MACOSX
29 #include "phydm_precomp.h"
30 #else
31 #include "../phydm_precomp.h"
32 #endif
33 #else
34 #include "../../phydm_precomp.h"
35 #endif
36
37 #if (RTL8822C_SUPPORT == 1)
halrf_rf_lna_setting_8822c(struct dm_struct * dm_void,enum halrf_lna_set type)38 void halrf_rf_lna_setting_8822c(struct dm_struct *dm_void,
39 enum halrf_lna_set type)
40 {
41 struct dm_struct *dm = (struct dm_struct *)dm_void;
42 u8 path = 0x0;
43
44 for (path = 0x0; path < 2; path++)
45 if (type == HALRF_LNA_DISABLE) {
46 /*S0*/
47 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(19),
48 0x1);
49 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33,
50 RFREGOFFSETMASK, 0x00003);
51 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3e,
52 RFREGOFFSETMASK, 0x00064);
53 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3f,
54 RFREGOFFSETMASK, 0x0afce);
55 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(19),
56 0x0);
57 } else if (type == HALRF_LNA_ENABLE) {
58 /*S0*/
59 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(19),
60 0x1);
61 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33,
62 RFREGOFFSETMASK, 0x00003);
63 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3e,
64 RFREGOFFSETMASK, 0x00064);
65 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3f,
66 RFREGOFFSETMASK, 0x1afce);
67 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(19),
68 0x0);
69 }
70 }
71
odm_tx_pwr_track_set_pwr8822c(void * dm_void,enum pwrtrack_method method,u8 rf_path,u8 channel_mapped_index)72 void odm_tx_pwr_track_set_pwr8822c(void *dm_void, enum pwrtrack_method method,
73 u8 rf_path, u8 channel_mapped_index)
74 {
75 struct dm_struct *dm = (struct dm_struct *)dm_void;
76 struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
77 struct _hal_rf_ *rf = &dm->rf_table;
78 struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
79
80 u32 bitmask_6_0 = BIT(6) | BIT(5) | BIT(4) | BIT(3) |
81 BIT(2) | BIT(1) | BIT(0);
82
83 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
84 "pRF->absolute_ofdm_swing_idx=%d pRF->remnant_ofdm_swing_idx=%d pRF->absolute_cck_swing_idx=%d pRF->remnant_cck_swing_idx=%d rf_path=%d\n",
85 cali_info->absolute_ofdm_swing_idx[rf_path], cali_info->remnant_ofdm_swing_idx[rf_path], cali_info->absolute_cck_swing_idx[rf_path], cali_info->remnant_cck_swing_idx, rf_path);
86
87 if (method == CLEAN_MODE) { /*use for mp driver clean power tracking status*/
88 RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "===> %s method=%d clear power tracking rf_path=%d\n",
89 __func__, method, rf_path);
90 tssi->tssi_trk_txagc_offset[rf_path] = 0;
91
92 switch (rf_path) {
93 case RF_PATH_A:
94 odm_set_bb_reg(dm, R_0x18a0, bitmask_6_0, (cali_info->absolute_ofdm_swing_idx[rf_path] & 0x7f));
95 odm_set_rf_reg(dm, rf_path, RF_0x7f, 0x00002, 0x0);
96 odm_set_rf_reg(dm, rf_path, RF_0x7f, 0x00100, 0x0);
97 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
98 "Path-%d 0x%x=0x%x\n", rf_path, R_0x18a0,
99 odm_get_bb_reg(dm, R_0x18a0, bitmask_6_0));
100 break;
101 case RF_PATH_B:
102 odm_set_bb_reg(dm, R_0x41a0, bitmask_6_0, (cali_info->absolute_ofdm_swing_idx[rf_path] & 0x7f));
103 odm_set_rf_reg(dm, rf_path, RF_0x7f, 0x00002, 0x0);
104 odm_set_rf_reg(dm, rf_path, RF_0x7f, 0x00100, 0x0);
105 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
106 "Path-%d 0x%x=0x%x\n", rf_path, R_0x41a0,
107 odm_get_bb_reg(dm, R_0x41a0, bitmask_6_0));
108 break;
109 default:
110 break;
111 }
112 } else if (method == BBSWING) { /*use for mp driver clean power tracking status*/
113 switch (rf_path) {
114 case RF_PATH_A:
115 odm_set_bb_reg(dm, R_0x18a0, bitmask_6_0, (cali_info->absolute_ofdm_swing_idx[rf_path] & 0x7f));
116 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
117 "Path-%d 0x%x=0x%x\n", rf_path, R_0x18a0, odm_get_bb_reg(dm, R_0x18a0, bitmask_6_0));
118 break;
119 case RF_PATH_B:
120 odm_set_bb_reg(dm, R_0x41a0, bitmask_6_0, (cali_info->absolute_ofdm_swing_idx[rf_path] & 0x7f));
121 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
122 "Path-%d 0x%x=0x%x\n", rf_path, R_0x41a0, odm_get_bb_reg(dm, R_0x41a0, bitmask_6_0));
123 break;
124 default:
125 break;
126 }
127 } else if (method == MIX_MODE) {
128 switch (rf_path) {
129 case RF_PATH_A:
130 odm_set_bb_reg(dm, R_0x18a0, bitmask_6_0, (cali_info->absolute_ofdm_swing_idx[rf_path] & 0x7f));
131 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
132 "Path-%d 0x%x=0x%x\n", rf_path, R_0x18a0, odm_get_bb_reg(dm, R_0x18a0, bitmask_6_0));
133 break;
134 case RF_PATH_B:
135 odm_set_bb_reg(dm, R_0x41a0, bitmask_6_0, (cali_info->absolute_ofdm_swing_idx[rf_path] & 0x7f));
136 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
137 "Path-%d 0x%x=0x%x\n", rf_path, R_0x41a0, odm_get_bb_reg(dm, R_0x41a0, bitmask_6_0));
138 break;
139 default:
140 break;
141 }
142 }
143 }
144
get_delta_swing_table_8822c(void * dm_void,u8 ** temperature_up_a,u8 ** temperature_down_a,u8 ** temperature_up_b,u8 ** temperature_down_b)145 void get_delta_swing_table_8822c(void *dm_void,
146 u8 **temperature_up_a,
147 u8 **temperature_down_a,
148 u8 **temperature_up_b,
149 u8 **temperature_down_b)
150 {
151 struct dm_struct *dm = (struct dm_struct *)dm_void;
152 struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
153 u8 channel = *dm->channel;
154 u8 tx_rate = phydm_get_tx_rate(dm);
155
156 if (channel >= 1 && channel <= 14) {
157 if (IS_CCK_RATE(tx_rate)) {
158 *temperature_up_a = cali_info->delta_swing_table_idx_2g_cck_a_p;
159 *temperature_down_a = cali_info->delta_swing_table_idx_2g_cck_a_n;
160 *temperature_up_b = cali_info->delta_swing_table_idx_2g_cck_b_p;
161 *temperature_down_b = cali_info->delta_swing_table_idx_2g_cck_b_n;
162 } else {
163 *temperature_up_a = cali_info->delta_swing_table_idx_2ga_p;
164 *temperature_down_a = cali_info->delta_swing_table_idx_2ga_n;
165 *temperature_up_b = cali_info->delta_swing_table_idx_2gb_p;
166 *temperature_down_b = cali_info->delta_swing_table_idx_2gb_n;
167 }
168 }
169
170 if (channel >= 36 && channel <= 64) {
171 *temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[0];
172 *temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[0];
173 *temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[0];
174 *temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[0];
175 } else if (channel >= 100 && channel <= 144) {
176 *temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[1];
177 *temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[1];
178 *temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[1];
179 *temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[1];
180 } else if (channel >= 149 && channel <= 177) {
181 *temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[2];
182 *temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[2];
183 *temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[2];
184 *temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[2];
185 }
186 }
187
_phy_aac_calibrate_8822c(struct dm_struct * dm)188 void _phy_aac_calibrate_8822c(struct dm_struct *dm)
189 {
190 #if 1
191 u32 cnt = 0;
192
193 RF_DBG(dm, DBG_RF_LCK, "[AACK]AACK start!!!!!!!\n");
194 //odm_set_rf_reg(dm, RF_PATH_A, 0xbb, RFREGOFFSETMASK, 0x80010);
195 odm_set_rf_reg(dm, RF_PATH_A, 0xb0, RFREGOFFSETMASK, 0x1F0FA);
196 ODM_delay_ms(1);
197 odm_set_rf_reg(dm, RF_PATH_A, RF_0xca, RFREGOFFSETMASK, 0x80000);
198 odm_set_rf_reg(dm, RF_PATH_A, RF_0xc9, RFREGOFFSETMASK, 0x80001);
199 for (cnt = 0; cnt < 100; cnt++) {
200 ODM_delay_ms(1);
201 if (odm_get_rf_reg(dm, RF_PATH_A, RF_0xca, 0x1000) != 0x1)
202 break;
203 }
204
205 odm_set_rf_reg(dm, RF_PATH_A, RF_0xb0, RFREGOFFSETMASK, 0x1F0F8);
206 //odm_set_rf_reg(dm, RF_PATH_B, 0xbb, RFREGOFFSETMASK, 0x80010);
207
208 RF_DBG(dm, DBG_RF_IQK, "[AACK]AACK end!!!!!!!\n");
209 #endif
210 }
_phy_rt_calibrate_8822c(struct dm_struct * dm)211 void _phy_rt_calibrate_8822c(struct dm_struct *dm)
212 {
213 RF_DBG(dm, DBG_RF_IQK, "[RTK]RTK start!!!!!!!\n");
214 odm_set_rf_reg(dm, RF_PATH_A, 0xcc, RFREGOFFSETMASK, 0x0f000);
215 odm_set_rf_reg(dm, RF_PATH_A, 0xcc, RFREGOFFSETMASK, 0x4f000);
216 ODM_delay_ms(1);
217 odm_set_rf_reg(dm, RF_PATH_A, 0xcc, RFREGOFFSETMASK, 0x0f000);
218 RF_DBG(dm, DBG_RF_IQK, "[RTK]RTK end!!!!!!!\n");
219 }
220
halrf_reload_bp_8822c(struct dm_struct * dm,u32 * bp_reg,u32 * bp)221 void halrf_reload_bp_8822c(struct dm_struct *dm, u32 *bp_reg, u32 *bp)
222 {
223 u32 i;
224
225 for (i = 0; i < DACK_REG_8822C; i++)
226 odm_write_4byte(dm, bp_reg[i], bp[i]);
227 }
228
halrf_reload_bprf_8822c(struct dm_struct * dm,u32 * bp_reg,u32 bp[][2])229 void halrf_reload_bprf_8822c(struct dm_struct *dm, u32 *bp_reg, u32 bp[][2])
230 {
231 u32 i;
232
233 for (i = 0; i < DACK_RF_8822C; i++) {
234 odm_set_rf_reg(dm, RF_PATH_A, bp_reg[i], MASK20BITS,
235 bp[i][RF_PATH_A]);
236 odm_set_rf_reg(dm, RF_PATH_B, bp_reg[i], MASK20BITS,
237 bp[i][RF_PATH_B]);
238 }
239 }
240
halrf_bp_8822c(struct dm_struct * dm,u32 * bp_reg,u32 * bp)241 void halrf_bp_8822c(struct dm_struct *dm, u32 *bp_reg, u32 *bp)
242 {
243 u32 i;
244
245 for (i = 0; i < DACK_REG_8822C; i++)
246 bp[i] = odm_read_4byte(dm, bp_reg[i]);
247 }
248
halrf_bprf_8822c(struct dm_struct * dm,u32 * bp_reg,u32 bp[][2])249 void halrf_bprf_8822c(struct dm_struct *dm, u32 *bp_reg, u32 bp[][2])
250 {
251 u32 i;
252
253 for (i = 0; i < DACK_RF_8822C; i++) {
254 bp[i][RF_PATH_A] =
255 odm_get_rf_reg(dm, RF_PATH_A, bp_reg[i], MASK20BITS);
256 bp[i][RF_PATH_B] =
257 odm_get_rf_reg(dm, RF_PATH_B, bp_reg[i], MASK20BITS);
258 }
259 }
260
halrf_swap_8822c(struct dm_struct * dm,u32 * v1,u32 * v2)261 void halrf_swap_8822c(struct dm_struct *dm, u32 *v1, u32 *v2)
262 {
263 u32 temp;
264
265 temp = *v1;
266 *v1 = *v2;
267 *v2 = temp;
268 }
269
halrf_bubble_8822c(struct dm_struct * dm,u32 * v1,u32 * v2)270 void halrf_bubble_8822c(struct dm_struct *dm, u32 *v1, u32 *v2)
271 {
272 u32 temp;
273
274 if (*v1 >= 0x200 && *v2 >= 0x200) {
275 if (*v1 > *v2)
276 halrf_swap_8822c(dm, v1, v2);
277 } else if (*v1 < 0x200 && *v2 < 0x200) {
278 if (*v1 > *v2)
279 halrf_swap_8822c(dm, v1, v2);
280 } else if (*v1 < 0x200 && *v2 >= 0x200) {
281 halrf_swap_8822c(dm, v1, v2);
282 }
283 }
284
halrf_b_sort_8822c(struct dm_struct * dm,u32 * iv,u32 * qv)285 void halrf_b_sort_8822c(struct dm_struct *dm, u32 *iv, u32 *qv)
286 {
287 u32 temp;
288 u32 i, j;
289
290 RF_DBG(dm, DBG_RF_DACK, "[DACK]bubble!!!!!!!!!!!!");
291 for (i = 0; i < SN - 1; i++) {
292 for (j = 0; j < (SN - 1 - i) ; j++) {
293 halrf_bubble_8822c(dm, &iv[j], &iv[j + 1]);
294 halrf_bubble_8822c(dm, &qv[j], &qv[j + 1]);
295 }
296 }
297 }
298
halrf_minmax_compare_8822c(struct dm_struct * dm,u32 value,u32 * min,u32 * max)299 void halrf_minmax_compare_8822c(struct dm_struct *dm, u32 value, u32 *min,
300 u32 *max)
301 {
302 if (value >= 0x200) {
303 if (*min >= 0x200) {
304 if (*min > value)
305 *min = value;
306 } else {
307 *min = value;
308 }
309 if (*max >= 0x200) {
310 if (*max < value)
311 *max = value;
312 }
313 } else {
314 if (*min < 0x200) {
315 if (*min > value)
316 *min = value;
317 }
318
319 if (*max >= 0x200) {
320 *max = value;
321 } else {
322 if (*max < value)
323 *max = value;
324 }
325 }
326 }
327
halrf_compare_8822c(struct dm_struct * dm,u32 value)328 boolean halrf_compare_8822c(struct dm_struct *dm, u32 value)
329 {
330 boolean fail = false;
331
332 if (value >= 0x200 && (0x400 - value) > 0x64)
333 fail = true;
334 else if (value < 0x200 && value > 0x64)
335 fail = true;
336
337 if (fail)
338 RF_DBG(dm, DBG_RF_DACK, "[DACK]overflow!!!!!!!!!!!!!!!");
339 return fail;
340 }
341
halrf_mode_8822c(struct dm_struct * dm,u32 * i_value,u32 * q_value)342 void halrf_mode_8822c(struct dm_struct *dm, u32 *i_value, u32 *q_value)
343 {
344 u32 iv[SN], qv[SN], im[SN], qm[SN], temp, temp1, temp2;
345 u32 p, m, t;
346 u32 i_max = 0, q_max = 0, i_min = 0x0, q_min = 0x0, c = 0x0;
347 u32 i_delta, q_delta;
348 u8 i, j, ii = 0, qi = 0;
349 boolean fail = false;
350
351 // ODM_delay_ms(10);
352 RF_DBG(dm, DBG_RF_DACK, "[DACK]pathA RF0x0 = 0x%x",
353 odm_get_rf_reg(dm, 0x0, 0x0, 0xfffff));
354 RF_DBG(dm, DBG_RF_DACK, "[DACK]pathB RF0x0 = 0x%x",
355 odm_get_rf_reg(dm, 0x1, 0x0, 0xfffff));
356
357 for (i = 0; i < SN; i++) {
358 im[i] = 0;
359 qm[i] = 0;
360 }
361
362 i = 0;
363 c = 0;
364 while (i < SN && c < 10000) {
365 c++;
366 temp = odm_get_bb_reg(dm, 0x2dbc, 0x3fffff);
367 iv[i] = (temp & 0x3ff000) >> 12;
368 qv[i] = temp & 0x3ff;
369
370 fail = false;
371 if (halrf_compare_8822c(dm, iv[i]))
372 fail = true;
373 if (halrf_compare_8822c(dm, qv[i]))
374 fail = true;
375 if (!fail)
376 i++;
377 }
378
379 c = 0;
380 do {
381 i_min = iv[0];
382 i_max = iv[0];
383 q_min = qv[0];
384 q_max = qv[0];
385 for (i = 0; i < SN; i++) {
386 halrf_minmax_compare_8822c(dm, iv[i], &i_min, &i_max);
387 halrf_minmax_compare_8822c(dm, qv[i], &q_min, &q_max);
388 }
389
390 c++;
391 RF_DBG(dm, DBG_RF_DACK, "[DACK]i_min=0x%x, i_max=0x%x",
392 i_min, i_max);
393 RF_DBG(dm, DBG_RF_DACK, "[DACK]q_min=0x%x, q_max=0x%x",
394 q_min, q_max);
395
396 if (i_max < 0x200 && i_min < 0x200)
397 i_delta = i_max - i_min;
398 else if (i_max >= 0x200 && i_min >= 0x200)
399 i_delta = i_max - i_min;
400 else
401 i_delta = i_max + (0x400 - i_min);
402
403 if (q_max < 0x200 && q_min < 0x200)
404 q_delta = q_max - q_min;
405 else if (q_max >= 0x200 && q_min >= 0x200)
406 q_delta = q_max - q_min;
407 else
408 q_delta = q_max + (0x400 - q_min);
409 RF_DBG(dm, DBG_RF_DACK, "[DACK]i_delta=0x%x, q_delta=0x%x",
410 i_delta, q_delta);
411 halrf_b_sort_8822c(dm, iv, qv);
412 if (i_delta > 5 || q_delta > 5) {
413 // halrf_b_sort_8822c(dm, iv, qv);
414 temp = odm_get_bb_reg(dm, 0x2dbc, 0x3fffff);
415 iv[0] = (temp & 0x3ff000) >> 12;
416 qv[0] = temp & 0x3ff;
417 temp = odm_get_bb_reg(dm, 0x2dbc, 0x3fffff);
418 iv[SN - 1] = (temp & 0x3ff000) >> 12;
419 qv[SN - 1] = temp & 0x3ff;
420 } else {
421 break;
422 }
423 } while (c < 100);
424 #if 0
425 for (i = 0; i < SN; i++) {
426 for (j = 0; j < SN; j++) {
427 if (i != j) {
428 if (iv[i] == iv[j])
429 im[i]++;
430 if (qv[i] == qv[j])
431 qm[i]++;
432 }
433 }
434 }
435
436 for (i = 0; i < SN; i++)
437 RF_DBG(dm, DBG_RF_DACK, "[DACK]iv[%d] = 0x%x\n", i, iv[i]);
438
439 for (i = 0; i < SN; i++)
440 RF_DBG(dm, DBG_RF_DACK, "[DACK]qv[%d] = 0x%x\n", i, qv[i]);
441
442 for (i = 1; i < SN; i++) {
443 if (im[ii] < im[i])
444 ii = i;
445 if (qm[qi] < qm[i])
446 qi = i;
447 }
448
449 *i_value = iv[ii];
450 *q_value = qv[qi];
451 #endif
452 #if 1
453 #if 0
454 for (i = 0; i < SN; i++)
455 RF_DBG(dm, DBG_RF_DACK, "[DACK]iv[%d] = 0x%x\n", i, iv[i]);
456
457 for (i = 0; i < SN; i++)
458 RF_DBG(dm, DBG_RF_DACK, "[DACK]qv[%d] = 0x%x\n", i, qv[i]);
459 #endif
460 /*i*/
461 m = 0;
462 p = 0;
463 for (i = 10; i < SN - 10; i++) {
464 if (iv[i] > 0x200)
465 m = (0x400 - iv[i]) + m;
466 else
467 p = iv[i] + p;
468 }
469
470 if (p > m) {
471 t = p - m;
472 t = t / (SN - 20);
473 } else {
474 t = m - p;
475 t = t / (SN - 20);
476 if (t != 0x0)
477 t = 0x400 - t;
478 }
479 *i_value = t;
480 /*q*/
481 m = 0;
482 p = 0;
483 for (i = 10; i < SN - 10; i++) {
484 if (qv[i] > 0x200)
485 m = (0x400 - qv[i]) + m;
486 else
487 p = qv[i] + p;
488 }
489 if (p > m) {
490 t = p - m;
491 t = t / (SN - 20);
492 } else {
493 t = m - p;
494 t = t / (SN - 20);
495 if (t != 0x0)
496 t = 0x400 - t;
497 }
498 *q_value = t;
499 #endif
500 }
501
halrf_biask_backup_8822c(void * dm_void)502 void halrf_biask_backup_8822c(void *dm_void)
503 {
504 struct dm_struct *dm = (struct dm_struct *)dm_void;
505 struct dm_dack_info *dack = &dm->dack_info;
506
507 dack->biask_d[0][0]= (u8)odm_get_bb_reg(dm, 0x2810, 0x1ff8);
508 dack->biask_d[0][1]= (u8)odm_get_bb_reg(dm, 0x283c, 0x1ff8);
509 dack->biask_d[1][0]= (u8)odm_get_bb_reg(dm, 0x4510, 0x1ff8);
510 dack->biask_d[1][1]= (u8)odm_get_bb_reg(dm, 0x453c, 0x1ff8);
511 }
512
halrf_dck_backup_8822c(void * dm_void)513 void halrf_dck_backup_8822c(void *dm_void)
514 {
515 struct dm_struct *dm = (struct dm_struct *)dm_void;
516 struct dm_dack_info *dack = &dm->dack_info;
517
518 dack->dck_d[0][0][0] = (u8)odm_get_bb_reg(dm, 0x18bc, 0xf0000000);
519 dack->dck_d[0][0][1] = (u8)odm_get_bb_reg(dm, 0x18c0, 0xf);
520 dack->dck_d[0][1][0] = (u8)odm_get_bb_reg(dm, 0x18d8, 0xf0000000);
521 dack->dck_d[0][1][1] = (u8)odm_get_bb_reg(dm, 0x18dc, 0xf);
522
523 dack->dck_d[1][0][0] = (u8)odm_get_bb_reg(dm, 0x41bc, 0xf0000000);
524 dack->dck_d[1][0][1] = (u8)odm_get_bb_reg(dm, 0x41c0, 0xf);
525 dack->dck_d[1][1][0] = (u8)odm_get_bb_reg(dm, 0x41d8, 0xf0000000);
526 dack->dck_d[1][1][1] = (u8)odm_get_bb_reg(dm, 0x41dc, 0xf);
527 }
halrf_dack_backup_8822c(void * dm_void)528 void halrf_dack_backup_8822c(void *dm_void)
529 {
530 struct dm_struct *dm = (struct dm_struct *)dm_void;
531 struct dm_dack_info *dack = &dm->dack_info;
532
533 u8 i;
534 u32 temp1, temp2, temp3;
535
536 temp1 = odm_get_bb_reg(dm, 0x1860, MASKDWORD);
537 temp2 = odm_get_bb_reg(dm, 0x4160, MASKDWORD);
538 temp3 = odm_get_bb_reg(dm, 0x9b4, MASKDWORD);
539
540 odm_set_bb_reg(dm, 0x9b4, MASKDWORD, 0xdb66db00);
541
542 odm_set_bb_reg(dm, 0x1830, BIT(30), 0x0);
543 odm_set_bb_reg(dm, 0x1860, 0xfc000000, 0x3c);
544
545 for (i = 0; i < 0xf; i++) {
546 odm_set_bb_reg(dm, 0x18b0, 0xf0000000, i);
547 dack->msbk_d[0][0][i] = (u16)odm_get_bb_reg(dm, 0x2810,
548 0x7fc0000);
549 }
550
551 for (i = 0; i < 0xf; i++) {
552 odm_set_bb_reg(dm, 0x18cc, 0xf0000000, i);
553 dack->msbk_d[0][1][i] = (u16)odm_get_bb_reg(dm, 0x283c,
554 0x7fc0000);
555 }
556
557 odm_set_bb_reg(dm, 0x4130, BIT(30), 0x0);
558 odm_set_bb_reg(dm, 0x4160, 0xfc000000, 0x3c);
559
560 for (i = 0; i < 0xf; i++) {
561 odm_set_bb_reg(dm, 0x41b0, 0xf0000000, i);
562 dack->msbk_d[1][0][i] = (u16)odm_get_bb_reg(dm, 0x4510,
563 0x7fc0000);
564 }
565
566 for (i = 0; i < 0xf; i++) {
567 odm_set_bb_reg(dm, 0x41cc, 0xf0000000, i);
568 dack->msbk_d[1][1][i] = (u16)odm_get_bb_reg(dm, 0x453c,
569 0x7fc0000);
570 }
571 halrf_dck_backup_8822c(dm);
572 odm_set_bb_reg(dm, 0x1830, BIT(30), 0x1);
573 odm_set_bb_reg(dm, 0x4130, BIT(30), 0x1);
574 odm_set_bb_reg(dm, 0x1860, MASKDWORD, temp1);
575 odm_set_bb_reg(dm, 0x4160, MASKDWORD, temp2);
576 odm_set_bb_reg(dm, 0x9b4, MASKDWORD, temp3);
577 halrf_biask_backup_8822c(dm);
578 }
579
halrf_biask_restore_8822c(void * dm_void)580 void halrf_biask_restore_8822c(void *dm_void)
581 {
582 struct dm_struct *dm = (struct dm_struct *)dm_void;
583 struct dm_dack_info *dack = &dm->dack_info;
584
585 odm_set_bb_reg(dm, 0x18b0, 0x1ff8000, dack->biask_d[0][0]);
586 odm_set_bb_reg(dm, 0x18cc, 0x1ff8000, dack->biask_d[0][1]);
587 odm_set_bb_reg(dm, 0x41b0, 0x1ff8000, dack->biask_d[1][0]);
588 odm_set_bb_reg(dm, 0x41cc, 0x1ff8000, dack->biask_d[1][1]);
589 }
590
halrf_dck_restore_8822c(void * dm_void)591 void halrf_dck_restore_8822c(void *dm_void)
592 {
593 struct dm_struct *dm = (struct dm_struct *)dm_void;
594 struct dm_dack_info *dack = &dm->dack_info;
595
596 odm_set_bb_reg(dm, 0x18bc, BIT(19), 0x1);
597 odm_set_bb_reg(dm, 0x18bc, 0xf0000000, dack->dck_d[0][0][0]);
598 odm_set_bb_reg(dm, 0x18c0, 0xf, dack->dck_d[0][0][1]);
599 odm_set_bb_reg(dm, 0x18d8, BIT(19), 0x1);
600 odm_set_bb_reg(dm, 0x18d8, 0xf0000000, dack->dck_d[0][1][0]);
601 odm_set_bb_reg(dm, 0x18dc, 0xf, dack->dck_d[0][1][1]);
602
603 odm_set_bb_reg(dm, 0x41bc, BIT(19), 0x1);
604 odm_set_bb_reg(dm, 0x41bc, 0xf0000000, dack->dck_d[1][0][0]);
605 odm_set_bb_reg(dm, 0x41c0, 0xf, dack->dck_d[1][0][1]);
606 odm_set_bb_reg(dm, 0x41d8, BIT(19), 0x1);
607 odm_set_bb_reg(dm, 0x41d8, 0xf0000000, dack->dck_d[1][1][0]);
608 odm_set_bb_reg(dm, 0x41dc, 0xf, dack->dck_d[1][1][1]);
609 }
halrf_dack_restore_8822c(void * dm_void)610 void halrf_dack_restore_8822c(void *dm_void)
611 {
612 struct dm_struct *dm = (struct dm_struct *)dm_void;
613 struct dm_dack_info *dack = &dm->dack_info;
614 u8 i;
615 u32 c = 0x0;
616 u32 temp1, temp2, temp3;
617
618 if (dack->dack_en == false)
619 return;
620
621 temp1 = odm_get_bb_reg(dm, 0x1860, MASKDWORD);
622 temp2 = odm_get_bb_reg(dm, 0x4160, MASKDWORD);
623 temp3 = odm_get_bb_reg(dm, 0x9b4, MASKDWORD);
624
625 odm_set_bb_reg(dm, 0x9b4, MASKDWORD, 0xdb66db00);
626
627 odm_set_bb_reg(dm, 0x18b0, BIT(27), 0x0);
628 odm_set_bb_reg(dm, 0x18cc, BIT(27), 0x0);
629 odm_set_bb_reg(dm, 0x41b0, BIT(27), 0x0);
630 odm_set_bb_reg(dm, 0x41cc, BIT(27), 0x0);
631
632 odm_set_bb_reg(dm, 0x1830, BIT(30), 0x0);
633 odm_set_bb_reg(dm, 0x1860, 0xfc000000, 0x3c);
634 odm_set_bb_reg(dm, 0x18b4, BIT(0), 0x1);
635 odm_set_bb_reg(dm, 0x18d0, BIT(0), 0x1);
636
637 odm_set_bb_reg(dm, 0x4130, BIT(30), 0x0);
638 odm_set_bb_reg(dm, 0x4160, 0xfc000000, 0x3c);
639 odm_set_bb_reg(dm, 0x41b4, BIT(0), 0x1);
640 odm_set_bb_reg(dm, 0x41d0, BIT(0), 0x1);
641
642 odm_set_bb_reg(dm, 0x18b0, 0xf00, 0x0);
643 odm_set_bb_reg(dm, 0x18c0, BIT(14), 0x0);
644 odm_set_bb_reg(dm, 0x18cc, 0xf00, 0x0);
645 odm_set_bb_reg(dm, 0x18dc, BIT(14), 0x0);
646
647 odm_set_bb_reg(dm, 0x18b0, BIT(0), 0x0);
648 odm_set_bb_reg(dm, 0x18cc, BIT(0), 0x0);
649 odm_set_bb_reg(dm, 0x18b0, BIT(0), 0x1);
650 odm_set_bb_reg(dm, 0x18cc, BIT(0), 0x1);
651
652 halrf_dck_restore_8822c(dm);
653
654 odm_set_bb_reg(dm, 0x18c0, 0x38000, 0x7);
655 odm_set_bb_reg(dm, 0x18dc, 0x38000, 0x7);
656 odm_set_bb_reg(dm, 0x41c0, 0x38000, 0x7);
657 odm_set_bb_reg(dm, 0x41dc, 0x38000, 0x7);
658
659 odm_set_bb_reg(dm, 0x18b8, BIT(26) | BIT(25), 0x1);
660 odm_set_bb_reg(dm, 0x18d4, BIT(26) | BIT(25), 0x1);
661
662 odm_set_bb_reg(dm, 0x41b0, 0xf00, 0x0);
663 odm_set_bb_reg(dm, 0x41c0, BIT(14), 0x0);
664 odm_set_bb_reg(dm, 0x41cc, 0xf00, 0x0);
665 odm_set_bb_reg(dm, 0x41dc, BIT(14), 0x0);
666
667 odm_set_bb_reg(dm, 0x41b0, BIT(0), 0x0);
668 odm_set_bb_reg(dm, 0x41cc, BIT(0), 0x0);
669 odm_set_bb_reg(dm, 0x41b0, BIT(0), 0x1);
670 odm_set_bb_reg(dm, 0x41cc, BIT(0), 0x1);
671
672 odm_set_bb_reg(dm, 0x41b8, BIT(26) | BIT(25), 0x1);
673 odm_set_bb_reg(dm, 0x41d4, BIT(26) | BIT(25), 0x1);
674 #if 1
675 c = 0x0;
676 while (c < 10000) {
677 RF_DBG(dm, DBG_RF_DACK, "[DACK]0x2808=0x%x",
678 odm_get_bb_reg(dm, 0x2808, 0x7fff80));
679 c++;
680 if (odm_get_bb_reg(dm, 0x2808, 0x7fff80) == 0xffff)
681 break;
682 }
683 c = 0x0;
684 while (c < 10000) {
685 RF_DBG(dm, DBG_RF_DACK, "[DACK]0x2834=0x%x",
686 odm_get_bb_reg(dm, 0x2834, 0x7fff80));
687 c++;
688 if (odm_get_bb_reg(dm, 0x2834, 0x7fff80) == 0xffff)
689 break;
690 }
691 c = 0x0;
692 while (c < 10000) {
693 RF_DBG(dm, DBG_RF_DACK, "[DACK]0x4508=0x%x",
694 odm_get_bb_reg(dm, 0x4508, 0x7fff80));
695 c++;
696 if (odm_get_bb_reg(dm, 0x4508, 0x7fff80) == 0xffff)
697 break;
698 }
699 c = 0x0;
700 while (c < 10000) {
701 RF_DBG(dm, DBG_RF_DACK, "[DACK]0x4534=0x%x",
702 odm_get_bb_reg(dm, 0x4534, 0x7fff80));
703 c++;
704 if (odm_get_bb_reg(dm, 0x4534, 0x7fff80) == 0xffff)
705 break;
706 }
707 #endif
708 odm_set_bb_reg(dm, 0x18b8, BIT(26) | BIT(25), 0x0);
709 odm_set_bb_reg(dm, 0x18b8, BIT(26) | BIT(25), 0x2);
710 c = 0x0;
711 while (c < 10000) {
712 c++;
713 RF_DBG(dm, DBG_RF_DACK, "[DACK]0x2808=0x%x",
714 odm_get_bb_reg(dm, 0x2808, 0xff));
715 if (odm_get_bb_reg(dm, 0x2808, 0xf) == 0x6)
716 break;
717 odm_set_bb_reg(dm, 0x18b8, BIT(26) | BIT(25), 0x0);
718 odm_set_bb_reg(dm, 0x18b8, BIT(26) | BIT(25), 0x2);
719 }
720 for (i = 0; i < 0xf; i++) {
721 odm_set_bb_reg(dm, 0x18b4, BIT(2), 0x0);
722 odm_set_bb_reg(dm, 0x18b4, 0xff8, dack->msbk_d[0][0][i]);
723 odm_set_bb_reg(dm, 0x18b0, 0xf0000000, i);
724 odm_set_bb_reg(dm, 0x18b4, BIT(2), 0x1);
725 }
726 odm_set_bb_reg(dm, 0x18b4, BIT(2), 0x0);
727 odm_set_bb_reg(dm, 0x18d4, BIT(26) | BIT(25), 0x0);
728 odm_set_bb_reg(dm, 0x18d4, BIT(26) | BIT(25), 0x2);
729 c = 0x0;
730 while (c < 10000) {
731 c++;
732 RF_DBG(dm, DBG_RF_DACK, "[DACK]0x2834=0x%x",
733 odm_get_bb_reg(dm, 0x2834, 0xff));
734 if (odm_get_bb_reg(dm,0x2834,0xf) == 0x6)
735 break;
736 odm_set_bb_reg(dm, 0x18d4, BIT(26) | BIT(25), 0x0);
737 odm_set_bb_reg(dm, 0x18d4, BIT(26) | BIT(25), 0x2);
738 }
739
740 for (i = 0; i < 0xf; i++) {
741 odm_set_bb_reg(dm, 0x18d0, BIT(2), 0x0);
742 odm_set_bb_reg(dm, 0x18d0, 0xff8, dack->msbk_d[0][1][i]);
743 odm_set_bb_reg(dm, 0x18cc, 0xf0000000, i);
744 odm_set_bb_reg(dm, 0x18d0, BIT(2), 0x1);
745 }
746 odm_set_bb_reg(dm, 0x18d0, BIT(2), 0x0);
747 odm_set_bb_reg(dm, 0x18b8, BIT(26) | BIT(25), 0x0);
748 odm_set_bb_reg(dm, 0x18d4, BIT(26) | BIT(25), 0x0);
749 odm_set_bb_reg(dm, 0x18b4, BIT(0), 0x0);
750 odm_set_bb_reg(dm, 0x18d0, BIT(0), 0x0);
751 odm_set_bb_reg(dm, 0x41b8, BIT(26) | BIT(25), 0x0);
752 odm_set_bb_reg(dm, 0x41b8, BIT(26) | BIT(25), 0x2);
753 c = 0x0;
754 while (c < 10000) {
755 c++;
756 RF_DBG(dm, DBG_RF_DACK, "[DACK]0x4508=0x%x",
757 odm_get_bb_reg(dm, 0x4508, 0xff));
758 if (odm_get_bb_reg(dm,0x4508,0xf) == 0x6)
759 break;
760 odm_set_bb_reg(dm, 0x41b8, BIT(26) | BIT(25), 0x0);
761 odm_set_bb_reg(dm, 0x41b8, BIT(26) | BIT(25), 0x2);
762 }
763 for (i = 0; i < 0xf; i++) {
764 odm_set_bb_reg(dm, 0x41b4, BIT(2), 0x0);
765 odm_set_bb_reg(dm, 0x41b4, 0xff8, dack->msbk_d[1][0][i]);
766 odm_set_bb_reg(dm, 0x41b0, 0xf0000000, i);
767 odm_set_bb_reg(dm, 0x41b4, BIT(2), 0x1);
768 }
769 odm_set_bb_reg(dm, 0x41b4, BIT(2), 0x0);
770 odm_set_bb_reg(dm, 0x41d4, BIT(26) | BIT(25), 0x0);
771 odm_set_bb_reg(dm, 0x41d4, BIT(26) | BIT(25), 0x2);
772 c = 0x0;
773 while (c < 10000) {
774 c++;
775 RF_DBG(dm, DBG_RF_DACK, "[DACK]0x4534=0x%x",
776 odm_get_bb_reg(dm, 0x4534, 0xff));
777 if (odm_get_bb_reg(dm,0x4534,0xf) == 0x6)
778 break;
779 odm_set_bb_reg(dm, 0x41d4, BIT(26) | BIT(25), 0x0);
780 odm_set_bb_reg(dm, 0x41d4, BIT(26) | BIT(25), 0x2);
781 }
782 for (i = 0x0; i < 0xf; i++) {
783 odm_set_bb_reg(dm, 0x41d0, BIT(2), 0x0);
784 odm_set_bb_reg(dm, 0x41d0, 0xff8, dack->msbk_d[1][1][i]);
785 odm_set_bb_reg(dm, 0x41cc, 0xf0000000, i);
786 odm_set_bb_reg(dm, 0x41d0, BIT(2), 0x1);
787 }
788 odm_set_bb_reg(dm, 0x41d0, BIT(2), 0x0);
789 odm_set_bb_reg(dm, 0x41b8, BIT(26) | BIT(25), 0x0);
790 odm_set_bb_reg(dm, 0x41d4, BIT(26) | BIT(25), 0x0);
791 odm_set_bb_reg(dm, 0x41b4, BIT(0), 0x0);
792 odm_set_bb_reg(dm, 0x41d0, BIT(0), 0x0);
793
794 odm_set_bb_reg(dm, 0x1830, BIT(30), 0x1);
795 odm_set_bb_reg(dm, 0x4130, BIT(30), 0x1);
796 odm_set_bb_reg(dm, 0x1860, MASKDWORD, temp1);
797 odm_set_bb_reg(dm, 0x4160, MASKDWORD, temp2);
798 odm_set_bb_reg(dm, 0x18b0, BIT(27), 0x1);
799 odm_set_bb_reg(dm, 0x18cc, BIT(27), 0x1);
800 odm_set_bb_reg(dm, 0x41b0, BIT(27), 0x1);
801 odm_set_bb_reg(dm, 0x41cc, BIT(27), 0x1);
802 odm_set_bb_reg(dm, 0x9b4, MASKDWORD, temp3);
803
804 halrf_biask_restore_8822c(dm);
805 }
806
halrf_polling_check(void * dm_void,u32 add,u32 bmask,u32 data)807 void halrf_polling_check(void *dm_void, u32 add, u32 bmask, u32 data)
808 {
809 struct dm_struct *dm = (struct dm_struct *)dm_void;
810 u32 c = 0;
811
812 c = 0;
813 while (c < 100000) {
814 c++;
815 if (odm_get_bb_reg(dm, add, bmask) == data)
816 break;
817 }
818 RF_DBG(dm, DBG_RF_DACK, "[DACK]c=%d\n",c);
819 }
820
halrf_dac_cal_8822c(void * dm_void,boolean force)821 void halrf_dac_cal_8822c(void *dm_void, boolean force)
822 {
823 struct dm_struct *dm = (struct dm_struct *)dm_void;
824 struct dm_dack_info *dack = &dm->dack_info;
825 static u32 count = 1;
826 #if 1
827 u32 ic = 0, qc = 0, temp = 0, temp1 = 0, i = 0;
828 u32 bp[DACK_REG_8822C];
829 u32 bp_reg[DACK_REG_8822C] = {0x180c, 0x1810, 0x410c, 0x4110, 0x1c3c, 0x1c24,
830 0x1d70, 0x9b4, 0x1a00, 0x1a14, 0x1d58,
831 0x1c38, 0x1e24, 0x1e28, 0x1860, 0x4160};
832 u32 bp_rf[DACK_RF_8822C][2];
833 u32 bp_rfreg[DACK_RF_8822C] = {0x8f};
834 u32 i_a = 0x0, q_a = 0x0, i_b = 0x0, q_b = 0x0;
835 u32 ic_a = 0x0, qc_a = 0x0, ic_b = 0x0, qc_b = 0x0;
836 u32 adc_ic_a = 0x0, adc_qc_a = 0x0, adc_ic_b = 0x0, adc_qc_b = 0x0;
837 #if 1
838 if (dack->dack_en) {
839 if (!force) {
840 halrf_dack_restore_8822c(dm);
841 return;
842 }
843 } else {
844 dack->dack_en = true;
845 }
846 #endif
847 count++;
848 RF_DBG(dm, DBG_RF_DACK, "[DACK]count = %d", count);
849 RF_DBG(dm, DBG_RF_DACK, "[DACK]DACK start!!!!!!!");
850 halrf_bp_8822c(dm, bp_reg, bp);
851 halrf_bprf_8822c(dm, bp_rfreg, bp_rf);
852 /*BB setting*/
853 odm_set_bb_reg(dm, 0x1d58, 0xff8, 0x1ff);
854 odm_set_bb_reg(dm, 0x1a00, 0x3, 0x2);
855 odm_set_bb_reg(dm, 0x1a14, 0x300, 0x3);
856 odm_write_4byte(dm, 0x1d70, 0x7e7e7e7e);
857 odm_set_bb_reg(dm, 0x180c, 0x3, 0x0);
858 odm_set_bb_reg(dm, 0x410c, 0x3, 0x0);
859 odm_write_4byte(dm, 0x1b00, 0x00000008);
860 odm_write_1byte(dm, 0x1bcc, 0x3f);
861 odm_write_4byte(dm, 0x1b00, 0x0000000a);
862 odm_write_1byte(dm, 0x1bcc, 0x3f);
863 odm_set_bb_reg(dm, 0x1e24, BIT(31), 0x0);
864 odm_set_bb_reg(dm, 0x1e28, 0xf, 0x3);
865 /*path-A*/
866 RF_DBG(dm, DBG_RF_DACK, "[DACK]pathA DACK!!!!!!!!!!!!!!!!!!!!!!!!!!!");
867 /*1.ADCK step1*/
868 RF_DBG(dm, DBG_RF_DACK, "[DACK]step1 ADCK!!!!!!!!!!!!!!!!!!!!!!!!!!!");
869 odm_set_bb_reg(dm, 0x1830, BIT(30), 0x0);
870 odm_write_4byte(dm, 0x1860, 0xf0040ff0);
871 odm_write_4byte(dm, 0x180c, 0xdff00220);
872 odm_write_4byte(dm, 0x1810, 0x02dd08c4);
873 odm_write_4byte(dm, 0x180c, 0x10000260);
874 odm_set_rf_reg(dm, RF_PATH_A, 0x0, RFREGOFFSETMASK, 0x10000);
875 odm_set_rf_reg(dm, RF_PATH_B, 0x0, RFREGOFFSETMASK, 0x10000);
876
877 i = 0;
878 while (i < 10) {
879 i++;
880 RF_DBG(dm, DBG_RF_DACK, "[DACK]ADCK count=%d", i);
881 odm_write_4byte(dm, 0x1c3c, 0x00088003);
882 odm_write_4byte(dm, 0x1c24, 0x00010002);
883 halrf_mode_8822c(dm, &ic, &qc);
884 RF_DBG(dm, DBG_RF_DACK, "[DACK]before ADCK i=0x%x, q=0x%x",
885 ic, qc);
886 /*compensation value*/
887 if (ic != 0x0) {
888 ic = 0x400 - ic;
889 adc_ic_a = ic;
890 }
891 if (qc != 0x0) {
892 qc = 0x400 - qc;
893 adc_qc_a = qc;
894 }
895 temp = (ic & 0x3ff) | ((qc & 0x3ff) << 10);
896 odm_write_4byte(dm, 0x1868, temp);
897 RF_DBG(dm, DBG_RF_DACK, "[DACK]ADCK 0x1868 =0x%x\n", temp);
898 #if 1
899 /*check ADC DC offset*/
900 odm_write_4byte(dm, 0x1c3c, 0x00088103);
901 halrf_mode_8822c(dm, &ic, &qc);
902 RF_DBG(dm, DBG_RF_DACK, "[DACK]after ADCK i=0x%x, q=0x%x",
903 ic, qc);
904 #endif
905 if (ic >= 0x200)
906 ic = 0x400 - ic;
907 if (qc >= 0x200)
908 qc = 0x400 - qc;
909 if (ic < 5 && qc < 5)
910 break;
911 }
912 /*2.ADCK step2*/
913 odm_write_4byte(dm, 0x1c3c, 0x00000003);
914 odm_write_4byte(dm, 0x180c, 0x10000260);
915 odm_write_4byte(dm, 0x1810, 0x02d508c4);
916 /*3.release pull low switch on IQ path*/
917 odm_set_rf_reg(dm, RF_PATH_A, 0x8f, BIT(13), 0x1);
918
919 RF_DBG(dm, DBG_RF_DACK, "[DACK]step2 DACK!!!!!!!!!!!!!!!!!!!!!!!!!!!");
920 i = 0;
921 while (i < 10) {
922 odm_write_4byte(dm, 0x1868, temp);
923 /*DACK step1*/
924 i++;
925 RF_DBG(dm, DBG_RF_DACK, "[DACK]DACK count=%d\n", i);
926 odm_write_4byte(dm, 0x180c, 0xdff00220);
927 odm_write_4byte(dm, 0x1860, 0xf0040ff0);
928 odm_write_4byte(dm, 0x1c38, 0xffffffff);
929 odm_write_4byte(dm, 0x1810, 0x02d508c5);
930 odm_write_4byte(dm, 0x9b4, 0xdb66db00);
931 odm_write_4byte(dm, 0x18b0, 0x0a11fb88);
932 odm_write_4byte(dm, 0x18bc, 0x0008ff81);
933 odm_write_4byte(dm, 0x18c0, 0x0003d208);
934 odm_write_4byte(dm, 0x18cc, 0x0a11fb88);
935 odm_write_4byte(dm, 0x18d8, 0x0008ff81);
936 odm_write_4byte(dm, 0x18dc, 0x0003d208);
937
938 odm_write_4byte(dm, 0x18b8, 0x60000000);
939 ODM_delay_ms(2);
940 odm_write_4byte(dm, 0x18bc, 0x000aff8d);
941 ODM_delay_ms(2);
942 odm_write_4byte(dm, 0x18b0, 0x0a11fb89);
943 odm_write_4byte(dm, 0x18cc, 0x0a11fb89);
944 ODM_delay_ms(1);
945 odm_write_4byte(dm, 0x18b8, 0x62000000);
946 // ODM_delay_ms(20);
947 odm_write_4byte(dm, 0x18d4, 0x62000000);
948 ODM_delay_ms(1);
949 halrf_polling_check(dm, 0x2808, 0x7fff80, 0xffff);
950 halrf_polling_check(dm, 0x2834, 0x7fff80, 0xffff);
951 odm_write_4byte(dm, 0x18b8, 0x02000000);
952 ODM_delay_ms(1);
953 odm_write_4byte(dm, 0x18bc, 0x0008ff87);
954 odm_write_4byte(dm, 0x9b4, 0xdb6db600);
955
956 odm_write_4byte(dm, 0x1810, 0x02d508c5);
957 odm_write_4byte(dm, 0x18bc, 0x0008ff87);
958 odm_write_4byte(dm, 0x1860, 0xf0000000);
959 /*4.DACK step2*/
960 odm_set_bb_reg(dm, 0x18bc, 0xf0000000, 0x0);
961 odm_set_bb_reg(dm, 0x18c0, 0xf, 0x8);
962 odm_set_bb_reg(dm, 0x18d8, 0xf0000000, 0x0);
963 odm_set_bb_reg(dm, 0x18dc, 0xf, 0x8);
964
965 odm_write_4byte(dm, 0x1b00, 0x00000008);
966 odm_write_1byte(dm, 0x1bcc, 0x03f);
967 odm_write_4byte(dm, 0x180c, 0xdff00220);
968 odm_write_4byte(dm, 0x1810, 0x02d508c5);
969 odm_write_4byte(dm, 0x1c3c, 0x00088103);
970 halrf_mode_8822c(dm, &ic, &qc);
971 RF_DBG(dm, DBG_RF_DACK, "[DACK]before DACK i =0x%x, q = 0x%x",
972 ic, qc);
973 /*compensation value*/
974 if (ic != 0x0)
975 ic = 0x400 - ic;
976 if (qc != 0x0)
977 qc = 0x400 - qc;
978 if (ic < 0x300) {
979 ic = ic * 2 * 6 / 5;
980 ic = ic + 0x80;
981 } else {
982 ic = (0x400 - ic) * 2 * 6 / 5;
983 ic = 0x7f - ic;
984 }
985 if (qc < 0x300) {
986 qc = qc * 2 * 6 / 5;
987 qc = qc + 0x80;
988 } else {
989 qc = (0x400 - qc) * 2 * 6 / 5;
990 qc = 0x7f - qc;
991 }
992 RF_DBG(dm, DBG_RF_DACK, "[DACK]DACK ic =0x%x, qc = 0x%x\n",
993 ic, qc);
994 ic_a = ic;
995 qc_a = qc;
996 /*5.DACK step3*/
997 odm_write_4byte(dm, 0x180c, 0xdff00220);
998 odm_write_4byte(dm, 0x1810, 0x02d508c5);
999 odm_write_4byte(dm, 0x9b4, 0xdb66db00);
1000 odm_write_4byte(dm, 0x18b0, 0x0a11fb88);
1001 odm_write_4byte(dm, 0x18bc, 0xc008ff81);
1002 odm_write_4byte(dm, 0x18c0, 0x0003d208);
1003 odm_set_bb_reg(dm, 0x18bc, 0xf0000000, ic & 0xf);
1004 odm_set_bb_reg(dm, 0x18c0, 0xf, (ic & 0xf0) >> 4);
1005 odm_write_4byte(dm, 0x18cc, 0x0a11fb88);
1006 odm_write_4byte(dm, 0x18d8, 0xe008ff81);
1007 odm_write_4byte(dm, 0x18dc, 0x0003d208);
1008 odm_set_bb_reg(dm, 0x18d8, 0xf0000000, qc & 0xf);
1009 odm_set_bb_reg(dm, 0x18dc, 0xf, (qc & 0xf0) >> 4);
1010 odm_write_4byte(dm, 0x18b8, 0x60000000);
1011 ODM_delay_ms(2);
1012 odm_set_bb_reg(dm, 0x18bc, 0xe, 0x6);
1013 ODM_delay_ms(2);
1014 odm_write_4byte(dm, 0x18b0, 0x0a11fb89);
1015 odm_write_4byte(dm, 0x18cc, 0x0a11fb89);
1016 ODM_delay_ms(1);
1017 odm_write_4byte(dm, 0x18b8, 0x62000000);
1018 odm_write_4byte(dm, 0x18d4, 0x62000000);
1019 ODM_delay_ms(1);
1020 halrf_polling_check(dm, 0x2824, 0x07f80000, ic);
1021 halrf_polling_check(dm, 0x2850, 0x07f80000, qc);
1022 odm_write_4byte(dm, 0x18b8, 0x02000000);
1023 ODM_delay_ms(1);
1024 odm_set_bb_reg(dm, 0x18bc, 0xe, 0x3);
1025 odm_write_4byte(dm, 0x9b4, 0xdb6db600);
1026 RF_DBG(dm, DBG_RF_DACK, "[DACK]0x18bc =0x%x",
1027 odm_read_4byte(dm, 0x18bc));
1028 RF_DBG(dm, DBG_RF_DACK, "[DACK]0x18c0 =0x%x",
1029 odm_read_4byte(dm, 0x18c0));
1030 RF_DBG(dm, DBG_RF_DACK, "[DACK]0x18d8 =0x%x",
1031 odm_read_4byte(dm, 0x18d8));
1032 RF_DBG(dm, DBG_RF_DACK, "[DACK]0x18dc =0x%x",
1033 odm_read_4byte(dm, 0x18dc));
1034 #if 1
1035 /*check DAC DC offset*/
1036 temp1 = ((adc_ic_a + 0x10) & 0x3ff) |
1037 (((adc_qc_a + 0x10) & 0x3ff) << 10);
1038 odm_write_4byte(dm, 0x1868, temp1);
1039 RF_DBG(dm, DBG_RF_DACK, "[DACK]shift 0x1868 =0x%x",
1040 odm_read_4byte(dm, 0x1868));
1041 odm_write_4byte(dm, 0x1810, 0x02d508c5);
1042 odm_write_4byte(dm, 0x1860, 0xf0000000);
1043 halrf_mode_8822c(dm, &ic, &qc);
1044 if (ic >= 0x10)
1045 ic = ic - 0x10;
1046 else
1047 ic = 0x400 - (0x10 - ic);
1048
1049 if (qc >= 0x10)
1050 qc = qc - 0x10;
1051 else
1052 qc = 0x400 - (0x10 - qc);
1053 RF_DBG(dm, DBG_RF_DACK, "[DACK]after DACK i=0x%x, q=0x%x",
1054 ic, qc);
1055 i_a = ic;
1056 q_a = qc;
1057 if (ic >= 0x200)
1058 ic = 0x400 - ic;
1059 if (qc >= 0x200)
1060 qc = 0x400 - qc;
1061 if (ic < 5 && qc < 5)
1062 break;
1063 #endif
1064 }
1065 odm_write_4byte(dm, 0x1868, 0x0);
1066 odm_write_4byte(dm, 0x1810, 0x02d508c4);
1067 odm_set_bb_reg(dm, 0x18bc, 0x1, 0x0);
1068 odm_set_bb_reg(dm, 0x1830, BIT(30), 0x1);
1069 #if 1
1070 /*path-B*/
1071 RF_DBG(dm, DBG_RF_DACK, "[DACK]pathB DACK!!!!!!!!!!!!!!!!!!!!!!!!!!!");
1072 /*1.ADCK step1*/
1073 RF_DBG(dm, DBG_RF_DACK, "[DACK]step1 ADCK!!!!!!!!!!!!!!!!!!!!!!!!!!!");
1074 odm_set_bb_reg(dm, 0x4130, BIT(30), 0x0);
1075 odm_write_4byte(dm, 0x4130, 0x30db8041);
1076 odm_write_4byte(dm, 0x4160, 0xf0040ff0);
1077 odm_write_4byte(dm, 0x410c, 0xdff00220);
1078 odm_write_4byte(dm, 0x4110, 0x02dd08c4);
1079 odm_write_4byte(dm, 0x410c, 0x10000260);
1080 odm_set_rf_reg(dm, RF_PATH_A, 0x0, RFREGOFFSETMASK, 0x10000);
1081 odm_set_rf_reg(dm, RF_PATH_B, 0x0, RFREGOFFSETMASK, 0x10000);
1082 i = 0;
1083 while (i < 10) {
1084 i++;
1085 RF_DBG(dm, DBG_RF_DACK, "[DACK]ADCK count=%d\n", i);
1086 odm_write_4byte(dm, 0x1c3c, 0x000a8003);
1087 odm_write_4byte(dm, 0x1c24, 0x00010002);
1088 halrf_mode_8822c(dm, &ic, &qc);
1089 RF_DBG(dm, DBG_RF_DACK, "[DACK]before ADCK i=0x%x, q=0x%x",
1090 ic, qc);
1091 /*compensation value*/
1092 if (ic != 0x0) {
1093 ic = 0x400 - ic;
1094 adc_ic_b = ic;
1095 }
1096 if (qc != 0x0) {
1097 qc = 0x400 - qc;
1098 adc_qc_b = qc;
1099 }
1100 temp = (ic & 0x3ff) | ((qc & 0x3ff) << 10);
1101 odm_write_4byte(dm, 0x4168, temp);
1102 RF_DBG(dm, DBG_RF_DACK, "[DACK]ADCK 0x4168 =0x%x\n", temp);
1103 #if 1
1104 /*check ADC DC offset*/
1105 odm_write_4byte(dm, 0x1c3c, 0x000a8103);
1106 halrf_mode_8822c(dm, &ic, &qc);
1107 RF_DBG(dm, DBG_RF_DACK, "[DACK]after ADCK i=0x%x, q=0x%x",
1108 ic, qc);
1109 #endif
1110 if (ic >= 0x200)
1111 ic = 0x400 - ic;
1112 if (qc >= 0x200)
1113 qc = 0x400 - qc;
1114 if (ic < 5 && qc < 5)
1115 break;
1116 }
1117 /*2.ADCK step2*/
1118 odm_write_4byte(dm, 0x1c3c, 0x00000003);
1119 odm_write_4byte(dm, 0x410c, 0x10000260);
1120 odm_write_4byte(dm, 0x4110, 0x02d508c4);
1121
1122 /*3.release pull low switch on IQ path*/
1123 odm_set_rf_reg(dm, RF_PATH_B, 0x8f, BIT(13), 0x1);
1124 RF_DBG(dm, DBG_RF_DACK, "[DACK]step2 DACK!!!!!!!!!!!!!!!!!!!!!!!!!!!");
1125 i = 0;
1126 while (i < 10) {
1127 odm_write_4byte(dm, 0x4168, temp);
1128 /*DACK step1*/
1129 i++;
1130 RF_DBG(dm, DBG_RF_DACK, "[DACK]DACK count=%d\n", i);
1131 odm_write_4byte(dm, 0x410c, 0xdff00220);
1132 odm_write_4byte(dm, 0x4110, 0x02d508c5);
1133 odm_write_4byte(dm, 0x9b4, 0xdb66db00);
1134 odm_write_4byte(dm, 0x41b0, 0x0a11fb88);
1135 odm_write_4byte(dm, 0x41bc, 0x0008ff81);
1136 odm_write_4byte(dm, 0x41c0, 0x0003d208);
1137 odm_write_4byte(dm, 0x41cc, 0x0a11fb88);
1138 odm_write_4byte(dm, 0x41d8, 0x0008ff81);
1139 odm_write_4byte(dm, 0x41dc, 0x0003d208);
1140
1141 odm_write_4byte(dm, 0x41b8, 0x60000000);
1142 ODM_delay_ms(2);
1143 odm_write_4byte(dm, 0x41bc, 0x000aff8d);
1144 ODM_delay_ms(2);
1145 odm_write_4byte(dm, 0x41b0, 0x0a11fb89);
1146 odm_write_4byte(dm, 0x41cc, 0x0a11fb89);
1147 ODM_delay_ms(1);
1148 odm_write_4byte(dm, 0x41b8, 0x62000000);
1149 odm_write_4byte(dm, 0x41d4, 0x62000000);
1150 ODM_delay_ms(1);
1151 halrf_polling_check(dm, 0x4508, 0x7fff80, 0xffff);
1152 halrf_polling_check(dm, 0x4534, 0x7fff80, 0xffff);
1153 odm_write_4byte(dm, 0x41b8, 0x02000000);
1154 ODM_delay_ms(1);
1155 odm_write_4byte(dm, 0x41bc, 0x0008ff87);
1156 odm_write_4byte(dm, 0x9b4, 0xdb6db600);
1157
1158 odm_write_4byte(dm, 0x4110, 0x02d508c5);
1159 odm_write_4byte(dm, 0x41bc, 0x0008ff87);
1160 odm_write_4byte(dm, 0x4160, 0xf0000000);
1161 /*4.DACK step2*/
1162 odm_set_bb_reg(dm, 0x41bc, 0xf0000000, 0x0);
1163 odm_set_bb_reg(dm, 0x41c0, 0xf, 0x8);
1164 odm_set_bb_reg(dm, 0x41d8, 0xf0000000, 0x0);
1165 odm_set_bb_reg(dm, 0x41dc, 0xf, 0x8);
1166 odm_write_4byte(dm, 0x1b00, 0x0000000a);
1167 odm_write_1byte(dm, 0x1bcc, 0x3f);
1168 odm_write_4byte(dm, 0x410c, 0xdff00220);
1169 odm_write_4byte(dm, 0x4110, 0x02d508c5);
1170 odm_write_4byte(dm, 0x1c3c, 0x000a8103);
1171 halrf_mode_8822c(dm, &ic, &qc);
1172 RF_DBG(dm, DBG_RF_DACK, "[DACK]before DACK i=0x%x, q=0x%x",
1173 ic, qc);
1174 /*compensation value*/
1175 if (ic != 0x0)
1176 ic = 0x400 - ic;
1177 if (qc != 0x0)
1178 qc = 0x400 - qc;
1179 if (ic < 0x300) {
1180 ic = ic * 2 * 6 / 5;
1181 ic = ic + 0x80;
1182 } else {
1183 ic = (0x400 - ic) * 2 * 6 / 5;
1184 ic = 0x7f - ic;
1185 }
1186 if (qc < 0x300) {
1187 qc = qc * 2 * 6 / 5;
1188 qc = qc + 0x80;
1189 } else {
1190 qc = (0x400 - qc) * 2 * 6 / 5;
1191 qc = 0x7f - qc;
1192 }
1193 RF_DBG(dm, DBG_RF_DACK, "[DACK]DACK ic=0x%x, qc=0x%x",
1194 ic, qc);
1195 ic_b = ic;
1196 qc_b = qc;
1197 /*5.DACK step3*/
1198 odm_write_4byte(dm, 0x410c, 0xdff00220);
1199 odm_write_4byte(dm, 0x4110, 0x02d508c5);
1200 odm_write_4byte(dm, 0x9b4, 0xdb66db00);
1201 odm_write_4byte(dm, 0x41b0, 0x0a11fb88);
1202 odm_write_4byte(dm, 0x41bc, 0xc008ff81);
1203 odm_write_4byte(dm, 0x41c0, 0x0003d208);
1204 odm_set_bb_reg(dm, 0x41bc, 0xf0000000, ic & 0xf);
1205 odm_set_bb_reg(dm, 0x41c0, 0xf, (ic & 0xf0) >> 4);
1206 odm_write_4byte(dm, 0x41cc, 0x0a11fb88);
1207 odm_write_4byte(dm, 0x41d8, 0xe008ff81);
1208 odm_write_4byte(dm, 0x41dc, 0x0003d208);
1209 odm_set_bb_reg(dm, 0x41d8, 0xf0000000, qc & 0xf);
1210 odm_set_bb_reg(dm, 0x41dc, 0xf, (qc & 0xf0) >> 4);
1211 odm_write_4byte(dm, 0x41b8, 0x60000000);
1212 ODM_delay_ms(2);
1213 odm_set_bb_reg(dm, 0x41bc, 0xe, 0x6);
1214 ODM_delay_ms(2);
1215 odm_write_4byte(dm, 0x41b0, 0x0a11fb89);
1216 odm_write_4byte(dm, 0x41cc, 0x0a11fb89);
1217 ODM_delay_ms(1);
1218 odm_write_4byte(dm, 0x41b8, 0x62000000);
1219 odm_write_4byte(dm, 0x41d4, 0x62000000);
1220 ODM_delay_ms(1);
1221 halrf_polling_check(dm, 0x4524, 0x07f80000, ic);
1222 halrf_polling_check(dm, 0x4550, 0x07f80000, qc);
1223 odm_write_4byte(dm, 0x41b8, 0x02000000);
1224 ODM_delay_ms(1);
1225 odm_set_bb_reg(dm, 0x41bc, 0xe, 0x3);
1226 odm_write_4byte(dm, 0x9b4, 0xdb6db600);
1227 RF_DBG(dm, DBG_RF_DACK, "[DACK]0x41bc =0x%x",
1228 odm_read_4byte(dm, 0x41bc));
1229 RF_DBG(dm, DBG_RF_DACK, "[DACK]0x41c0 =0x%x",
1230 odm_read_4byte(dm, 0x41c0));
1231 RF_DBG(dm, DBG_RF_DACK, "[DACK]0x41d8 =0x%x",
1232 odm_read_4byte(dm, 0x41d8));
1233 RF_DBG(dm, DBG_RF_DACK, "[DACK]0x41dc =0x%x",
1234 odm_read_4byte(dm, 0x41dc));
1235 #if 1
1236 /*check DAC DC offset*/
1237 temp1 = ((adc_ic_b + 0x10) & 0x3ff) |
1238 (((adc_qc_b + 0x10) & 0x3ff) << 10);
1239 odm_write_4byte(dm, 0x4168, temp1);
1240 RF_DBG(dm, DBG_RF_DACK, "[DACK]shift 0x4168 =0x%x\n",
1241 odm_read_4byte(dm, 0x4168));
1242 odm_write_4byte(dm, 0x4110, 0x02d508c5);
1243 odm_write_4byte(dm, 0x4160, 0xf0000000);
1244 halrf_mode_8822c(dm, &ic, &qc);
1245 if (ic >= 0x10)
1246 ic = ic - 0x10;
1247 else
1248 ic = 0x400 - (0x10 - ic);
1249
1250 if (qc >= 0x10)
1251 qc = qc - 0x10;
1252 else
1253 qc = 0x400 - (0x10 - qc);
1254 RF_DBG(dm, DBG_RF_DACK, "[DACK]after DACK i=0x%x, q=0x%x",
1255 ic, qc);
1256 i_b = ic;
1257 q_b = qc;
1258 #endif
1259 if (ic >= 0x200)
1260 ic = 0x400 - ic;
1261 if (qc >= 0x200)
1262 qc = 0x400 - qc;
1263 if (ic < 5 && qc < 5)
1264 break;
1265 }
1266 #endif
1267 odm_write_4byte(dm, 0x4168, 0x0);
1268 odm_write_4byte(dm, 0x4110, 0x02d508c4);
1269 odm_set_bb_reg(dm, 0x41bc, 0x1, 0x0);
1270 odm_set_bb_reg(dm, 0x4130, BIT(30), 0x1);
1271 odm_write_4byte(dm, 0x1b00, 0x00000008);
1272 odm_set_bb_reg(dm, 0x4130, BIT(30), 0x1);
1273 odm_write_1byte(dm, 0x1bcc, 0x0);
1274 odm_write_4byte(dm, 0x1b00, 0x0000000a);
1275 odm_write_1byte(dm, 0x1bcc, 0x0);
1276 i_b = ic;
1277 q_b = qc;
1278 RF_DBG(dm, DBG_RF_DACK, "[DACK]PATH A:ic=0x%x, qc=0x%x", ic_a, qc_a);
1279 RF_DBG(dm, DBG_RF_DACK, "[DACK]PATH B:ic=0x%x, qc=0x%x", ic_b, qc_b);
1280 RF_DBG(dm, DBG_RF_DACK, "[DACK]PATH A:i=0x%x, q=0x%x", i_a, q_a);
1281 RF_DBG(dm, DBG_RF_DACK, "[DACK]PATH B:i=0x%x, q=0x%x", i_b, q_b);
1282 halrf_reload_bp_8822c(dm, bp_reg, bp);
1283 halrf_reload_bprf_8822c(dm, bp_rfreg, bp_rf);
1284 halrf_dack_backup_8822c(dm);
1285 RF_DBG(dm, DBG_RF_DACK, "[DACK]DACK end!!!!!!!\n");
1286 #endif
1287 }
1288
halrf_dack_dbg_8822c(void * dm_void)1289 void halrf_dack_dbg_8822c(void *dm_void)
1290 {
1291 struct dm_struct *dm = (struct dm_struct *)dm_void;
1292 u8 i;
1293 u32 temp1, temp2, temp3;
1294
1295 temp1 = odm_get_bb_reg(dm, 0x1860, MASKDWORD);
1296 temp2 = odm_get_bb_reg(dm, 0x4160, MASKDWORD);
1297 temp3 = odm_get_bb_reg(dm, 0x9b4, MASKDWORD);
1298
1299 odm_set_bb_reg(dm, 0x9b4, MASKDWORD, 0xdb66db00);
1300
1301 RF_DBG(dm, DBG_RF_DACK, "[DACK]MSBK result\n");
1302 RF_DBG(dm, DBG_RF_DACK, "[DACK]PATH A\n");
1303 //pathA
1304 odm_set_bb_reg(dm, 0x1830, BIT(30), 0x0);
1305 odm_set_bb_reg(dm, 0x1860, 0xfc000000, 0x3c);
1306 //i
1307 for (i = 0; i < 0xf; i++) {
1308 odm_set_bb_reg(dm, 0x18b0, 0xf0000000, i);
1309 RF_DBG(dm, DBG_RF_DACK, "[DACK]msbk_d[0][0][%d]=0x%x\n", i,
1310 odm_get_bb_reg(dm,0x2810,0x7fc0000));
1311 }
1312 //q
1313 for (i = 0; i < 0xf; i++) {
1314 odm_set_bb_reg(dm, 0x18cc, 0xf0000000, i);
1315 RF_DBG(dm, DBG_RF_DACK, "[DACK]msbk_d[0][1][%d]=0x%x\n", i,
1316 odm_get_bb_reg(dm,0x283c,0x7fc0000));
1317 }
1318 //pathB
1319 RF_DBG(dm, DBG_RF_DACK, "[DACK]PATH A\n");
1320 odm_set_bb_reg(dm, 0x4130, BIT(30), 0x0);
1321 odm_set_bb_reg(dm, 0x4160, 0xfc000000, 0x3c);
1322 //i
1323 for (i = 0; i < 0xf; i++) {
1324 odm_set_bb_reg(dm, 0x41b0, 0xf0000000, i);
1325 RF_DBG(dm, DBG_RF_DACK, "[DACK]msbk_d[1][0][%d]=0x%x\n", i,
1326 odm_get_bb_reg(dm,0x4510,0x7fc0000));
1327 }
1328 //q
1329 for (i = 0; i < 0xf; i++) {
1330 odm_set_bb_reg(dm, 0x41cc, 0xf0000000, i);
1331 RF_DBG(dm, DBG_RF_DACK, "[DACK]msbk_d[1][1][%d]=0x%x\n", i,
1332 odm_get_bb_reg(dm,0x453c,0x7fc0000));
1333 }
1334
1335 RF_DBG(dm, DBG_RF_DACK, "[DACK]DCK result\n");
1336 RF_DBG(dm, DBG_RF_DACK, "[DACK]PATH A\n");
1337 RF_DBG(dm, DBG_RF_DACK, "[DACK]0x18bc[31:28]=0x%x\n",
1338 odm_get_bb_reg(dm,0x18bc,0xf0000000));
1339 RF_DBG(dm, DBG_RF_DACK, "[DACK]0x18c0[3:0]=0x%x\n",
1340 odm_get_bb_reg(dm,0x18c0,0xf));
1341 RF_DBG(dm, DBG_RF_DACK, "[DACK]0x18d8[31:28]=0x%x\n",
1342 odm_get_bb_reg(dm,0x18d8,0xf0000000));
1343 RF_DBG(dm, DBG_RF_DACK, "[DACK]0x18dc[3:0]=0x%x\n",
1344 odm_get_bb_reg(dm,0x18dc,0xf));
1345 RF_DBG(dm, DBG_RF_DACK, "[DACK]PATH B\n");
1346 RF_DBG(dm, DBG_RF_DACK, "[DACK]0x41bc[31:28]=0x%x\n",
1347 odm_get_bb_reg(dm,0x41bc,0xf0000000));
1348 RF_DBG(dm, DBG_RF_DACK, "[DACK]0x41c0[3:0]=0x%x\n",
1349 odm_get_bb_reg(dm,0x41c0,0xf));
1350 RF_DBG(dm, DBG_RF_DACK, "[DACK]0x41d8[31:28]=0x%x\n",
1351 odm_get_bb_reg(dm,0x41d8,0xf0000000));
1352 RF_DBG(dm, DBG_RF_DACK, "[DACK]0x41dc[3:0]=0x%x\n",
1353 odm_get_bb_reg(dm,0x41dc,0xf));
1354
1355
1356 //restore to normal
1357 odm_set_bb_reg(dm, 0x1830, BIT(30), 0x1);
1358 odm_set_bb_reg(dm, 0x4130, BIT(30), 0x1);
1359 odm_set_bb_reg(dm, 0x1860, MASKDWORD, temp1);
1360 odm_set_bb_reg(dm, 0x4160, MASKDWORD, temp2);
1361 odm_set_bb_reg(dm, 0x9b4, MASKDWORD, temp3);
1362 }
1363
halrf_rxdck_8822c(void * dm_void)1364 void halrf_rxdck_8822c(void *dm_void)
1365 {
1366 struct dm_struct *dm = (struct dm_struct *)dm_void;
1367 u32 temp1, temp2;
1368
1369 temp1 = odm_get_bb_reg(dm, 0x180c, MASKDWORD);
1370 temp2 = odm_get_bb_reg(dm, 0x410c, MASKDWORD);
1371 odm_set_bb_reg(dm, 0x180c, 0x3, 0x0);
1372 odm_set_bb_reg(dm, 0x410c, 0x3, 0x0);
1373 odm_set_rf_reg(dm, RF_PATH_A, 0x0, RFREGOFFSETMASK, 0x30000);
1374 odm_set_rf_reg(dm, RF_PATH_B, 0x0, RFREGOFFSETMASK, 0x30000);
1375
1376 odm_set_rf_reg(dm, RF_PATH_A, 0x92, RFREGOFFSETMASK, 0x84800);
1377 odm_set_rf_reg(dm, RF_PATH_A, 0x92, RFREGOFFSETMASK, 0x84801);
1378 ODM_delay_ms(1);
1379 odm_set_rf_reg(dm, RF_PATH_A, 0x92, RFREGOFFSETMASK, 0x84800);
1380
1381 odm_set_rf_reg(dm, RF_PATH_B, 0x92, RFREGOFFSETMASK, 0x84800);
1382 odm_set_rf_reg(dm, RF_PATH_B, 0x92, RFREGOFFSETMASK, 0x84801);
1383 ODM_delay_ms(1);
1384 odm_set_rf_reg(dm, RF_PATH_B, 0x92, RFREGOFFSETMASK, 0x84800);
1385
1386 odm_set_bb_reg(dm, 0x180c, MASKDWORD, temp1);
1387 odm_set_bb_reg(dm, 0x410c, MASKDWORD, temp2);
1388 odm_set_rf_reg(dm, RF_PATH_A, 0x0, RFREGOFFSETMASK, 0x3ffff);
1389 odm_set_rf_reg(dm, RF_PATH_B, 0x0, RFREGOFFSETMASK, 0x3ffff);
1390 }
_phy_x2_calibrate_8822c(struct dm_struct * dm)1391 void _phy_x2_calibrate_8822c(struct dm_struct *dm)
1392 {
1393 RF_DBG(dm, DBG_RF_IQK, "[X2K]X2K start!!!!!!!\n");
1394 /*X2K*/
1395 //Path A
1396 odm_set_rf_reg(dm, RF_PATH_A, 0x18, RFREGOFFSETMASK, 0x13108);
1397 ODM_delay_ms(1);
1398 odm_set_rf_reg(dm, RF_PATH_A, 0xb8, RFREGOFFSETMASK, 0xC0440);
1399 odm_set_rf_reg(dm, RF_PATH_A, 0xba, RFREGOFFSETMASK, 0xE840D);
1400 ODM_delay_ms(1);
1401 odm_set_rf_reg(dm, RF_PATH_A, 0x18, RFREGOFFSETMASK, 0x13124);
1402 //Path B
1403 // SYN is in the path A
1404 RF_DBG(dm, DBG_RF_IQK, "[X2K]X2K end!!!!!!!\n");
1405 }
1406
phy_x2_check_8822c(void * dm_void)1407 void phy_x2_check_8822c(void *dm_void)
1408 {
1409 struct dm_struct *dm = (struct dm_struct *)dm_void;
1410 u32 X2K_BUSY;
1411
1412 RF_DBG(dm, DBG_RF_IQK, "[X2K]X2K check start!!!!!!!\n");
1413 /*X2K*/
1414 //Path A
1415 ODM_delay_ms(1);
1416 X2K_BUSY = (u8) odm_get_rf_reg(dm, RF_PATH_A, 0xb8, BIT(15));
1417 if (X2K_BUSY == 1) {
1418 odm_set_rf_reg(dm, RF_PATH_A, 0xb8, RFREGOFFSETMASK, 0xC4440);
1419 odm_set_rf_reg(dm, RF_PATH_A, 0xba, RFREGOFFSETMASK, 0x6840D);
1420 odm_set_rf_reg(dm, RF_PATH_A, 0xb8, RFREGOFFSETMASK, 0x80440);
1421 ODM_delay_ms(1);
1422 }
1423 //Path B
1424 // SYN is in the path A
1425 RF_DBG(dm, DBG_RF_IQK, "[X2K]X2K check end!!!!!!!\n");
1426 }
1427
1428 /*LCK VERSION:0x1*/
phy_lc_calibrate_8822c(void * dm_void)1429 void phy_lc_calibrate_8822c(void *dm_void)
1430 {
1431 struct dm_struct *dm = (struct dm_struct *)dm_void;
1432 #if 1
1433 _phy_aac_calibrate_8822c(dm);
1434 _phy_rt_calibrate_8822c(dm);
1435 #endif
1436 }
1437
configure_txpower_track_8822c(struct txpwrtrack_cfg * config)1438 void configure_txpower_track_8822c(struct txpwrtrack_cfg *config)
1439 {
1440 config->swing_table_size_cck = TXSCALE_TABLE_SIZE;
1441 config->swing_table_size_ofdm = TXSCALE_TABLE_SIZE;
1442 config->threshold_iqk = IQK_THRESHOLD;
1443 config->threshold_dpk = DPK_THRESHOLD;
1444 config->average_thermal_num = AVG_THERMAL_NUM_8822C;
1445 config->rf_path_count = MAX_PATH_NUM_8822C;
1446 config->thermal_reg_addr = RF_T_METER_8822C;
1447
1448 config->odm_tx_pwr_track_set_pwr = odm_tx_pwr_track_set_pwr8822c;
1449 config->do_iqk = do_iqk_8822c;
1450 config->phy_lc_calibrate = halrf_lck_trigger;
1451 config->do_tssi_dck = halrf_tssi_dck;
1452 config->get_delta_swing_table = get_delta_swing_table_8822c;
1453 }
1454
1455 #if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
phy_set_rf_path_switch_8822c(struct dm_struct * dm,boolean is_main)1456 void phy_set_rf_path_switch_8822c(struct dm_struct *dm, boolean is_main)
1457 #else
1458 void phy_set_rf_path_switch_8822c(void *adapter, boolean is_main)
1459 #endif
1460 {
1461 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1462 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1463 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
1464 struct dm_struct *dm = &hal_data->DM_OutSrc;
1465 #endif
1466 #endif
1467 /*BY mida Request */
1468 if (is_main) {
1469 /*WiFi*/
1470 odm_set_bb_reg(dm, R_0x70, BIT(26), 0x1);
1471 } else {
1472 /*BT*/
1473 odm_set_bb_reg(dm, R_0x70, BIT(26), 0x0);
1474 }
1475 }
1476
1477 #if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
_phy_query_rf_path_switch_8822c(struct dm_struct * dm)1478 boolean _phy_query_rf_path_switch_8822c(struct dm_struct *dm)
1479 #else
1480 boolean _phy_query_rf_path_switch_8822c(void *adapter)
1481 #endif
1482 {
1483 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1484 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1485 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
1486 struct dm_struct *dm = &hal_data->DM_OutSrc;
1487 #endif
1488 #endif
1489 if (odm_get_bb_reg(dm, R_0x70, BIT(26)) == 0x1)
1490 return true; /*WiFi*/
1491 else
1492 return false;
1493 }
1494
1495 #if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
phy_query_rf_path_switch_8822c(struct dm_struct * dm)1496 boolean phy_query_rf_path_switch_8822c(struct dm_struct *dm)
1497 #else
1498 boolean phy_query_rf_path_switch_8822c(void *adapter)
1499 #endif
1500 {
1501 #if DISABLE_BB_RF
1502 return true;
1503 #endif
1504 #if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
1505 return _phy_query_rf_path_switch_8822c(dm);
1506 #else
1507 return _phy_query_rf_path_switch_8822c(adapter);
1508 #endif
1509 }
1510
halrf_rxbb_dc_cal_8822c(void * dm_void)1511 void halrf_rxbb_dc_cal_8822c(void *dm_void)
1512 {
1513 struct dm_struct *dm = (struct dm_struct *)dm_void;
1514
1515 u8 path, i;
1516
1517 for (path = 0; path < 2; path++) {
1518 odm_set_rf_reg(dm, (enum rf_path)path, 0x92, RFREG_MASK, 0x84800);
1519 ODM_delay_us(5);
1520 odm_set_rf_reg(dm, (enum rf_path)path, 0x92, RFREG_MASK, 0x84801);
1521 for (i = 0; i < 30; i++) /*delay 600us*/
1522 ODM_delay_us(20);
1523 odm_set_rf_reg(dm, (enum rf_path)path, 0x92, RFREG_MASK, 0x84800);
1524 }
1525 }
1526
halrf_rfk_handshake_8822c(void * dm_void,boolean is_before_k)1527 void halrf_rfk_handshake_8822c(void *dm_void, boolean is_before_k)
1528 {
1529 struct dm_struct *dm = (struct dm_struct *)dm_void;
1530 struct _hal_rf_ *rf = &dm->rf_table;
1531
1532 u8 u1b_tmp, h2c_parameter;
1533 u16 count;
1534
1535 rf->is_rfk_h2c_timeout = false;
1536
1537 if (is_before_k) {
1538
1539 RF_DBG(dm, DBG_RF_IQK | DBG_RF_DPK | DBG_RF_TX_PWR_TRACK,
1540 "[RFK] WiFi / BT RFK handshake start!!\n");
1541
1542 if (!rf->is_bt_iqk_timeout) {
1543 /* Check if BT request to do IQK (0xaa[6]) or is doing IQK (0xaa[5]), 600ms timeout*/
1544 count = 0;
1545 u1b_tmp = (u8)odm_get_mac_reg(dm, 0xa8, BIT(22) | BIT(21));
1546 while (u1b_tmp != 0 && count < 30000) {
1547 ODM_delay_us(20);
1548 u1b_tmp = (u8)odm_get_mac_reg(dm, 0xa8, BIT(22) | BIT(21));
1549 count++;
1550 }
1551
1552 if (count >= 30000) {
1553 RF_DBG(dm, DBG_RF_IQK | DBG_RF_DPK | DBG_RF_TX_PWR_TRACK,
1554 "[RFK] Wait BT IQK finish timeout!!\n");
1555
1556 rf->is_bt_iqk_timeout = true;
1557 }
1558 }
1559
1560 /* Send RFK start H2C cmd*/
1561 h2c_parameter = 1;
1562 odm_fill_h2c_cmd(dm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter);
1563
1564 /* Check 0x49c[0] or 100ms timeout*/
1565 count = 0;
1566 u1b_tmp = (u8)odm_get_mac_reg(dm, 0x49c, BIT(0));
1567 while (u1b_tmp != 0x1 && count < 5000) {
1568 ODM_delay_us(20);
1569 u1b_tmp = (u8)odm_get_mac_reg(dm, 0x49c, BIT(0));
1570 count++;
1571 }
1572
1573 if (count >= 5000) {
1574 RF_DBG(dm, DBG_RF_IQK | DBG_RF_DPK | DBG_RF_TX_PWR_TRACK,
1575 "[RFK] Send WiFi RFK start H2C cmd FAIL!!\n");
1576
1577 rf->is_rfk_h2c_timeout = true;
1578 }
1579
1580 } else {
1581 /* Send RFK finish H2C cmd*/
1582 h2c_parameter = 0;
1583 odm_fill_h2c_cmd(dm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter);
1584 /* Check 0x49c[0] or 100ms timeout*/
1585 count = 0;
1586 u1b_tmp = (u8)odm_get_mac_reg(dm, 0x49c, BIT(0));
1587 while (u1b_tmp != 0 && count < 5000) {
1588 ODM_delay_us(20);
1589 u1b_tmp = (u8)odm_get_mac_reg(dm, 0x49c, BIT(0));
1590 count++;
1591 }
1592
1593 if (count >= 5000) {
1594 RF_DBG(dm, DBG_RF_IQK | DBG_RF_DPK | DBG_RF_TX_PWR_TRACK,
1595 "[RFK] Send WiFi RFK finish H2C cmd FAIL!!\n");
1596
1597 rf->is_rfk_h2c_timeout = true;
1598 }
1599
1600 RF_DBG(dm, DBG_RF_IQK | DBG_RF_DPK | DBG_RF_TX_PWR_TRACK,
1601 "[RFK] WiFi / BT RFK handshake finish!!\n");
1602 }
1603 }
halrf_rfk_power_save_8822c(void * dm_void,boolean is_power_save)1604 void halrf_rfk_power_save_8822c(
1605 void *dm_void,
1606 boolean is_power_save)
1607 {
1608 struct dm_struct *dm = (struct dm_struct *)dm_void;
1609 struct dm_iqk_info *iqk_info = &dm->IQK_info;
1610 u8 path = 0;
1611
1612 for(path = 0; path < SS_8822C; path++) {
1613 odm_set_bb_reg(dm, R_0x1b00, BIT(2)| BIT(1), path);
1614 if (is_power_save)
1615 odm_set_bb_reg(dm, R_0x1b08, BIT(7), 0x0);
1616 else
1617 odm_set_bb_reg(dm, R_0x1b08, BIT(7), 0x1);
1618 }
1619 }
1620
1621 #endif /*(RTL8822C_SUPPORT == 0)*/
1622