1 2 /* 3 * isp500_reg_cfg.h 4 * 5 * Copyright (c) 2007-2017 Allwinnertech Co., Ltd. 6 * 7 * This software is licensed under the terms of the GNU General Public 8 * License version 2, as published by the Free Software Foundation, and 9 * may be copied, distributed, and modified under those terms. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 */ 17 18 #ifndef _ISP500_REG_CFG_H_ 19 #define _ISP500_REG_CFG_H_ 20 21 #define ISP_ADDR_BIT_R_SHIFT 2 22 23 #define ISP_LOAD_DRAM_SIZE (0x400+0x5a00+0x1f00) 24 #define ISP_SAVE_DRAM_SIZE (0x400+0xab00) 25 26 /*ISP size configs*/ 27 #define ISP_REG_SIZE 0x400 28 #define ISP_LOAD_REG_SIZE 0x400 29 #define ISP_SAVED_REG_SIZE 0x400 30 31 /*stat size configs*/ 32 33 #define ISP_STAT_TOTAL_SIZE 0xAB00 34 35 #define ISP_STAT_HIST_MEM_SIZE 0x0200 36 #define ISP_STAT_AE_MEM_SIZE 0x4800 37 #define ISP_STAT_AF_MEM_SIZE 0x0500 38 #define ISP_STAT_AFS_MEM_SIZE 0x0200 39 #define ISP_STAT_AWB_RGB_MEM_SIZE 0x4800 40 #define ISP_STAT_AWB_CNT_MEM_SIZE 0x0C00 41 #define ISP_STAT_PLTM_LST_MEM_SIZE 0x0600 42 43 #define ISP_STAT_HIST_MEM_OFS 0x0000 44 #define ISP_STAT_AE_MEM_OFS 0x0200 45 #define ISP_STAT_AF_MEM_OFS 0x4a00 46 #define ISP_STAT_AFS_MEM_OFS 0x4f00 47 #define ISP_STAT_AWB_MEM_OFS 0x5100 48 #define ISP_STAT_PLTM_LST_MEM_OFS 0xa500 49 50 /*table size configs*/ 51 52 #define ISP_TABLE_MAPPING1_SIZE 0x5a00 53 #define ISP_LSC_MEM_SIZE (256*8) 54 #define ISP_GAMMA_MEM_SIZE (256*4) 55 #define ISP_LINEAR_MEM_SIZE (256*6) 56 #define ISP_WDR_GAMMA_FE_MEM_SIZE (4096*2) 57 #define ISP_WDR_GAMMA_BE_MEM_SIZE (4096*2) 58 #define ISP_TDNF_DIFF_MEM_SIZE (256*1) 59 #define ISP_PLTM_H_MEM_SIZE (256*1) 60 #define ISP_PLTM_V_MEM_SIZE (256*1) 61 #define ISP_PLTM_POW_MEM_SIZE (256*2) 62 #define ISP_PLTM_F_MEM_SIZE (256*2) 63 #define ISP_CONTRAST_PE_MEM_SIZE (128*2) 64 65 #define ISP_TABLE_MAPPING2_SIZE 0x1f00 66 #define ISP_DRC_MEM_SIZE (256*2) 67 #define ISP_SATURATION_MEM_SIZE (256*2) 68 #define ISP_CEM_MEM_SIZE (736*8) 69 70 #define ISP_LSC_MEM_OFS 0x0 71 #define ISP_GAMMA_MEM_OFS 0x0800 72 #define ISP_LINEAR_MEM_OFS 0x0c00 73 #define ISP_WDR_GAMMA_FE_MEM_OFS 0x1200 74 #define ISP_WDR_GAMMA_BE_MEM_OFS 0x3200 75 #define ISP_TDNF_DIFF_MEM_OFS 0x5200 76 #define ISP_PLTM_H_MEM_OFS 0x5300 77 #define ISP_PLTM_V_MEM_OFS 0x5400 78 #define ISP_PLTM_POW_MEM_OFS 0x5500 79 #define ISP_PLTM_F_MEM_OFS 0x5700 80 #define ISP_CONTRAST_PE_MEM_OFS 0x5900 81 82 #define ISP_DRC_MEM_OFS 0x0 83 #define ISP_SATURATION_MEM_OFS 0x0600 84 #define ISP_CEM_MEM_OFS 0x0800 85 86 /* 87 * update table 88 */ 89 #define LUT_UPDATE (1 << 3) 90 #define LINEAR_UPDATE (1 << 3) 91 #define LENS_UPDATE (1 << 4) 92 #define GAMMA_UPDATE (1 << 5) 93 #define DRC_UPDATE (1 << 6) 94 #define DISC_UPDATE (1 << 7) 95 #define D3D_UPDATE (1 << 7) 96 #define SATU_UPDATE (1 << 8) 97 #define WDR_UPDATE (1 << 9) 98 #define TDNF_UPDATE (1 << 10) 99 #define PLTM_UPDATE (1 << 11) 100 #define CEM_UPDATE (1 << 12) 101 #define CONTRAST_UPDATE (1 << 13) 102 103 #define TABLE_UPDATE_ALL 0xffffffff 104 105 /* 106 * ISP Module enable 107 */ 108 #define AE_EN (1 << 0) 109 #define LC_EN (1 << 1) 110 #define WDR_EN (1 << 2) 111 #define DPC_EN (1 << 3) 112 #define D2D_EN (1 << 4) 113 #define D3D_EN (1 << 5) 114 #define AWB_EN (1 << 6) 115 #define WB_EN (1 << 7) 116 #define LSC_EN (1 << 8) 117 #define BGC_EN (1 << 9) 118 #define SHARP_EN (1 << 10) 119 #define AF_EN (1 << 11) 120 #define RGB2RGB_EN (1 << 12) 121 #define RGB_DRC_EN (1 << 13) 122 #define PLTM_EN (1 << 14) 123 #define CEM_EN (1 << 15) 124 #define AFS_EN (1 << 16) 125 #define HIST_EN (1 << 17) 126 #define BLC_EN (1 << 18) 127 #define DG_EN (1 << 19) 128 #define SO_EN (1 << 20) 129 #define CTC_EN (1 << 21) 130 #define CONTRAST_EN (1 << 22) 131 #define CNR_EN (1 << 23) 132 #define SATU_EN (1 << 24) 133 #define SRC0_EN (1 << 31) 134 #define ISP_MODULE_EN_ALL (0xffffffff) 135 136 /* 137 * ISP interrupt enable 138 */ 139 #define FINISH_INT_EN (1 << 0) 140 #define START_INT_EN (1 << 1) 141 #define PARA_SAVE_INT_EN (1 << 2) 142 #define PARA_LOAD_INT_EN (1 << 3) 143 #define SRC0_FIFO_INT_EN (1 << 4) 144 #define N_LINE_START_INT_EN (1 << 7) 145 #define FRAME_ERROR_INT_EN (1 << 8) 146 #define FRAME_LOST_INT_EN (1 << 14) 147 148 #define ISP_IRQ_EN_ALL 0xffffffff 149 150 /* 151 * ISP interrupt status 152 */ 153 #define FINISH_PD (1 << 0) 154 #define START_PD (1 << 1) 155 #define PARA_SAVE_PD (1 << 2) 156 #define PARA_LOAD_PD (1 << 3) 157 #define SRC0_FIFO_OF_PD (1 << 4) 158 #define N_LINE_START_PD (1 << 7) 159 #define FRAME_ERROR_PD (1 << 8) 160 #define CIN_FIFO_OF_PD (1 << 9) 161 #define DPC_FIFO_OF_PD (1 << 10) 162 #define D2D_FIFO_OF_PD (1 << 11) 163 #define BIS_FIFO_OF_PD (1 << 12) 164 #define CNR_FIFO_OF_PD (1 << 13) 165 #define FRAME_LOST_PD (1 << 14) 166 #define HB_SHORT_PD (1 << 16) 167 #define D3D_HB_PD (1 << 24) 168 #define PLTM_FIFO_OF_PD (1 << 25) 169 #define D3D_WRITE_FIFO_OF_PD (1 << 26) 170 #define D3D_READ_FIFO_OF_PD (1 << 27) 171 #define D3D_WT2CMP_FIFO_OF_PD (1 << 28) 172 #define WDR_WRITE_FIFO_OF_PD (1 << 29) 173 #define WDR_WT2CMP_FIFO_OF_PD (1 << 30) 174 #define WDR_READ_FIFO_OF_PD (1 << 31) 175 176 #define ISP_IRQ_STATUS_ALL 0xffffffff 177 178 enum isp_channel { 179 ISP_CH0 = 0, 180 ISP_CH1 = 1, 181 ISP_CH2 = 2, 182 ISP_CH3 = 3, 183 ISP_MAX_CH_NUM, 184 }; 185 186 struct isp_size { 187 unsigned int width; 188 unsigned int height; 189 }; 190 191 struct coor { 192 unsigned int hor; 193 unsigned int ver; 194 }; 195 196 struct isp_size_settings { 197 struct coor ob_start; 198 struct isp_size ob_black; 199 struct isp_size ob_valid; 200 u32 set_cnt; 201 }; 202 203 enum ready_flag { 204 PARA_NOT_READY = 0, 205 PARA_READY = 1, 206 }; 207 208 enum enable_flag { 209 DISABLE = 0, 210 ENABLE = 1, 211 }; 212 213 enum isp_input_tables { 214 LENS_GAMMA_TABLE = 0, 215 DRC_TABLE = 1, 216 }; 217 218 enum isp_input_seq { 219 ISP_BGGR = 4, 220 ISP_RGGB = 5, 221 ISP_GBRG = 6, 222 ISP_GRBG = 7, 223 }; 224 225 enum isp_output_speed { 226 ISP_OUTPUT_SPEED_0 = 0, 227 ISP_OUTPUT_SPEED_1 = 1, 228 ISP_OUTPUT_SPEED_2 = 2, 229 ISP_OUTPUT_SPEED_3 = 3, 230 }; 231 232 enum isp_debug_sel { 233 ISP_DBG_OBC0_INPUT = 0, 234 ISP_DBG_OBC0_OUTPUT, 235 ISP_DBG_OBC1_OUTPUT, 236 ISP_DBG_WDR_OUTPUT, 237 ISP_DBG_DPC_OUTPUT, 238 ISP_DBG_D2D_OUTPUT, 239 ISP_DBG_D3D_OUTPUT, 240 ISP_DBG_D3D_Y_OUTPUT, 241 ISP_DBG_D3D_B_OUTPUT, 242 ISP_DBG_LSC_OUTPUT, 243 ISP_DBG_PLTM_OUTPUT, 244 ISP_DBG_CNR_R_OUTPUT, 245 ISP_DBG_CNR_G_OUTPUT, 246 ISP_DBG_CNR_B_OUTPUT, 247 ISP_DBG_BGC_R_OUTPUT, 248 ISP_DBG_BGC_G_OUTPUT, 249 ISP_DBG_BGC_B_OUTPUT, 250 }; 251 252 void bsp_isp_map_reg_addr(unsigned long id, unsigned long base); 253 void bsp_isp_map_load_dram_addr(unsigned long id, unsigned long base); 254 void bsp_isp_map_saved_dram_addr(unsigned long id, unsigned long base); 255 void bsp_isp_enable(unsigned long id, int enable); 256 void bsp_isp_ch_enable(unsigned long id, int ch, int enable); 257 void bsp_isp_wdr_ch_seq(unsigned long id, int seq); 258 void bsp_isp_set_para_ready(unsigned long id, enum ready_flag ready); 259 unsigned int bsp_isp_get_para_ready(unsigned long id); 260 void bsp_isp_update_table(unsigned long id, unsigned short table_update); 261 void bsp_isp_capture_start(unsigned long id); 262 void bsp_isp_capture_stop(unsigned long id); 263 void bsp_isp_irq_enable(unsigned long id, unsigned int irq_flag); 264 void bsp_isp_irq_disable(unsigned long id, unsigned int irq_flag); 265 int bsp_isp_int_get_enable(unsigned long id); 266 unsigned int bsp_isp_get_irq_status(unsigned long id, unsigned int irq_flag); 267 void bsp_isp_clr_irq_status(unsigned long id, unsigned int irq_flag); 268 void bsp_isp_debug_output_cfg(unsigned long id, int enable, int output_sel); 269 void bsp_isp_set_para_ready_mode(unsigned long id, int enable); 270 void bsp_isp_set_line_int_num(unsigned long id, unsigned int line_num); 271 void bsp_isp_set_last_blank_cycle(unsigned long id, unsigned int last_blank_cycle); 272 void bsp_isp_set_speed_mode(unsigned long id, unsigned int speed_mode); 273 void bsp_isp_set_load_addr(unsigned long id, unsigned long addr); 274 void bsp_isp_set_saved_addr(unsigned long id, unsigned long addr); 275 void bsp_isp_set_table_addr(unsigned long id, enum isp_input_tables table, unsigned long addr); 276 void bsp_isp_set_statistics_addr(unsigned long id, unsigned long addr); 277 unsigned int bsp_isp_get_isp_ver(unsigned long id, unsigned int *major, unsigned int *minor); 278 void bsp_isp_ver_read_en(unsigned long id, unsigned int en); 279 void bsp_isp_get_s0_ch_fmerr_cnt(unsigned long id, struct isp_size *size); 280 void bsp_isp_get_s0_ch_hb_cnt(unsigned long id, unsigned int *hb_max, unsigned int *hb_min); 281 void bsp_isp_module_enable(unsigned long id, unsigned int modules); 282 void bsp_isp_module_disable(unsigned long id, unsigned int modules); 283 void bsp_isp_set_wdr_mode(unsigned long id, unsigned int wdr_mode); 284 void bsp_isp_set_input_fmt(unsigned long id, unsigned int fmt); 285 void bsp_isp_set_size(unsigned long id, struct isp_size_settings *size); 286 unsigned int bsp_isp_load_update_flag(unsigned long id); 287 288 void bsp_isp_set_wdr_addr0(unsigned long id, dma_addr_t addr); 289 void bsp_isp_set_wdr_addr1(unsigned long id, dma_addr_t addr); 290 void bsp_isp_set_d3d_addr0(unsigned long id, dma_addr_t addr); 291 void bsp_isp_set_d3d_addr1(unsigned long id, dma_addr_t addr); 292 void bsp_isp_set_fifo_mode(unsigned long id, unsigned int mode); 293 void bsp_isp_min_ddr_size(unsigned long id, unsigned int size); 294 void bsp_isp_fifo_raw_write(unsigned long id, unsigned int depth); 295 void bsp_isp_k_min_ddr_size(unsigned long id, unsigned int size); 296 297 #endif /*_ISP500_REG_CFG_H_*/ 298