1 // Copyright (C) 2022 Beken Corporation
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 /***********************************************************************************************************************************
16 * This file is generated from BK7256_ADDR Mapping_20211224_format_change_highlight_20220113_update.xlsm automatically
17 * Modify it manually is not recommended
18 * CHIP ID:BK7256,GENARATE TIME:2022-01-26 14:14:13
19 ************************************************************************************************************************************/
20
21 #pragma once
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 #include <soc/soc.h>
28
29 #define LCD_DISP_LL_REG_BASE (SOC_LCD_DISP_REG_BASE) //REG_BASE:0x48060000
30
31 /* REG_0x00 */
32 #define LCD_DISP_DISPLAY_INT_ADDR (LCD_DISP_LL_REG_BASE + 0x0*4) //REG ADDR :0x48060000
33 #define LCD_DISP_DISPLAY_INT_RGB_INT_EN_POS (0)
34 #define LCD_DISP_DISPLAY_INT_RGB_INT_EN_MASK (0x3)
35
36 #define LCD_DISP_DISPLAY_INT_I8080_INT_EN_POS (2)
37 #define LCD_DISP_DISPLAY_INT_I8080_INT_EN_MASK (0x3)
38
39 #define LCD_DISP_DISPLAY_INT_RGB_SOF_POS (4)
40 #define LCD_DISP_DISPLAY_INT_RGB_SOF_MASK (0x1)
41
42 #define LCD_DISP_DISPLAY_INT_RGB_EOF_POS (5)
43 #define LCD_DISP_DISPLAY_INT_RGB_EOF_MASK (0x1)
44
45 #define LCD_DISP_DISPLAY_INT_I8080_SOF_POS (6)
46 #define LCD_DISP_DISPLAY_INT_I8080_SOF_MASK (0x1)
47
48 #define LCD_DISP_DISPLAY_INT_I8080_EOF_POS (7)
49 #define LCD_DISP_DISPLAY_INT_I8080_EOF_MASK (0x1)
50
51 #define LCD_DISP_DISPLAY_INT_WR_THRD_POS (8)
52 #define LCD_DISP_DISPLAY_INT_WR_THRD_MASK (0x3FF)
53
54 #define LCD_DISP_DISPLAY_INT_RD_THRD_POS (16)
55 #define LCD_DISP_DISPLAY_INT_RD_THRD_MASK (0xFFF)
56
57 #define LCD_DISP_DISPLAY_INT_DISCONTI_MODE_POS (28)
58 #define LCD_DISP_DISPLAY_INT_DISCONTI_MODE_MASK (0x1)
59
60 #define LCD_DISP_DISPLAY_INT_RESERVED_POS (29)
61 #define LCD_DISP_DISPLAY_INT_RESERVED_MASK (0x7)
62
lcd_disp_ll_get_display_int_value(void)63 static inline uint32_t lcd_disp_ll_get_display_int_value(void)
64 {
65 return REG_READ(LCD_DISP_DISPLAY_INT_ADDR);
66 }
67
lcd_disp_ll_set_display_int_value(uint32_t value)68 static inline void lcd_disp_ll_set_display_int_value(uint32_t value)
69 {
70 REG_WRITE(LCD_DISP_DISPLAY_INT_ADDR,value);
71 }
72
73 /* REG_0x00:display_int->rgb_int_en:0x0[ 1:0],rgb display interrupt enable,0x0,r/w*/
lcd_disp_ll_get_display_int_rgb_int_en(void)74 static inline uint32_t lcd_disp_ll_get_display_int_rgb_int_en(void)
75 {
76 uint32_t reg_value;
77 reg_value = REG_READ(LCD_DISP_DISPLAY_INT_ADDR);
78 reg_value = ((reg_value >> LCD_DISP_DISPLAY_INT_RGB_INT_EN_POS) & LCD_DISP_DISPLAY_INT_RGB_INT_EN_MASK);
79 return reg_value;
80 }
81
lcd_disp_ll_set_display_int_rgb_int_en(uint32_t value)82 static inline void lcd_disp_ll_set_display_int_rgb_int_en(uint32_t value)
83 {
84 uint32_t reg_value;
85 reg_value = REG_READ(LCD_DISP_DISPLAY_INT_ADDR);
86 reg_value &= ~(LCD_DISP_DISPLAY_INT_RGB_INT_EN_MASK << LCD_DISP_DISPLAY_INT_RGB_INT_EN_POS);
87 reg_value |= ((value & LCD_DISP_DISPLAY_INT_RGB_INT_EN_MASK) << LCD_DISP_DISPLAY_INT_RGB_INT_EN_POS);
88 REG_WRITE(LCD_DISP_DISPLAY_INT_ADDR,reg_value);
89 }
90
91 /* REG_0x00:display_int->i8080_int_en:0x0[ 3:2],i8080 display interrupt enable,0x0,r/w*/
lcd_disp_ll_get_display_int_i8080_int_en(void)92 static inline uint32_t lcd_disp_ll_get_display_int_i8080_int_en(void)
93 {
94 uint32_t reg_value;
95 reg_value = REG_READ(LCD_DISP_DISPLAY_INT_ADDR);
96 reg_value = ((reg_value >> LCD_DISP_DISPLAY_INT_I8080_INT_EN_POS) & LCD_DISP_DISPLAY_INT_I8080_INT_EN_MASK);
97 return reg_value;
98 }
99
lcd_disp_ll_set_display_int_i8080_int_en(uint32_t value)100 static inline void lcd_disp_ll_set_display_int_i8080_int_en(uint32_t value)
101 {
102 uint32_t reg_value;
103 reg_value = REG_READ(LCD_DISP_DISPLAY_INT_ADDR);
104 reg_value &= ~(LCD_DISP_DISPLAY_INT_I8080_INT_EN_MASK << LCD_DISP_DISPLAY_INT_I8080_INT_EN_POS);
105 reg_value |= ((value & LCD_DISP_DISPLAY_INT_I8080_INT_EN_MASK) << LCD_DISP_DISPLAY_INT_I8080_INT_EN_POS);
106 REG_WRITE(LCD_DISP_DISPLAY_INT_ADDR,reg_value);
107 }
108
109 /* REG_0x00:display_int->rgb_sof:0x0[ 4],rgb display output start of frame,0x0,r/w*/
lcd_disp_ll_get_display_int_rgb_sof(void)110 static inline uint32_t lcd_disp_ll_get_display_int_rgb_sof(void)
111 {
112 uint32_t reg_value;
113 reg_value = REG_READ(LCD_DISP_DISPLAY_INT_ADDR);
114 reg_value = ((reg_value >> LCD_DISP_DISPLAY_INT_RGB_SOF_POS) & LCD_DISP_DISPLAY_INT_RGB_SOF_MASK);
115 return reg_value;
116 }
117
lcd_disp_ll_set_display_int_rgb_sof(uint32_t value)118 static inline void lcd_disp_ll_set_display_int_rgb_sof(uint32_t value)
119 {
120 uint32_t reg_value;
121 reg_value = REG_READ(LCD_DISP_DISPLAY_INT_ADDR);
122 reg_value &= ~(LCD_DISP_DISPLAY_INT_RGB_SOF_MASK << LCD_DISP_DISPLAY_INT_RGB_SOF_POS);
123 reg_value |= ((value & LCD_DISP_DISPLAY_INT_RGB_SOF_MASK) << LCD_DISP_DISPLAY_INT_RGB_SOF_POS);
124 REG_WRITE(LCD_DISP_DISPLAY_INT_ADDR,reg_value);
125 }
126
127 /* REG_0x00:display_int->rgb_eof:0x0[ 5],rgb display output end of frame,0x0,r/w*/
lcd_disp_ll_get_display_int_rgb_eof(void)128 static inline uint32_t lcd_disp_ll_get_display_int_rgb_eof(void)
129 {
130 uint32_t reg_value;
131 reg_value = REG_READ(LCD_DISP_DISPLAY_INT_ADDR);
132 reg_value = ((reg_value >> LCD_DISP_DISPLAY_INT_RGB_EOF_POS) & LCD_DISP_DISPLAY_INT_RGB_EOF_MASK);
133 return reg_value;
134 }
135
lcd_disp_ll_set_display_int_rgb_eof(uint32_t value)136 static inline void lcd_disp_ll_set_display_int_rgb_eof(uint32_t value)
137 {
138 uint32_t reg_value;
139 reg_value = REG_READ(LCD_DISP_DISPLAY_INT_ADDR);
140 reg_value &= ~(LCD_DISP_DISPLAY_INT_RGB_EOF_MASK << LCD_DISP_DISPLAY_INT_RGB_EOF_POS);
141 reg_value |= ((value & LCD_DISP_DISPLAY_INT_RGB_EOF_MASK) << LCD_DISP_DISPLAY_INT_RGB_EOF_POS);
142 REG_WRITE(LCD_DISP_DISPLAY_INT_ADDR,reg_value);
143 }
144
145 /* REG_0x00:display_int->i8080_sof:0x0[ 6],8080 display output start of frame,0x0,r/w*/
lcd_disp_ll_get_display_int_i8080_sof(void)146 static inline uint32_t lcd_disp_ll_get_display_int_i8080_sof(void)
147 {
148 uint32_t reg_value;
149 reg_value = REG_READ(LCD_DISP_DISPLAY_INT_ADDR);
150 reg_value = ((reg_value >> LCD_DISP_DISPLAY_INT_I8080_SOF_POS) & LCD_DISP_DISPLAY_INT_I8080_SOF_MASK);
151 return reg_value;
152 }
153
lcd_disp_ll_set_display_int_i8080_sof(uint32_t value)154 static inline void lcd_disp_ll_set_display_int_i8080_sof(uint32_t value)
155 {
156 uint32_t reg_value;
157 reg_value = REG_READ(LCD_DISP_DISPLAY_INT_ADDR);
158 reg_value &= ~(LCD_DISP_DISPLAY_INT_I8080_SOF_MASK << LCD_DISP_DISPLAY_INT_I8080_SOF_POS);
159 reg_value |= ((value & LCD_DISP_DISPLAY_INT_I8080_SOF_MASK) << LCD_DISP_DISPLAY_INT_I8080_SOF_POS);
160 REG_WRITE(LCD_DISP_DISPLAY_INT_ADDR,reg_value);
161 }
162
163 /* REG_0x00:display_int->i8080_eof:0x0[ 7],8080 display output end of frame,0x0,r/w*/
lcd_disp_ll_get_display_int_i8080_eof(void)164 static inline uint32_t lcd_disp_ll_get_display_int_i8080_eof(void)
165 {
166 uint32_t reg_value;
167 reg_value = REG_READ(LCD_DISP_DISPLAY_INT_ADDR);
168 reg_value = ((reg_value >> LCD_DISP_DISPLAY_INT_I8080_EOF_POS) & LCD_DISP_DISPLAY_INT_I8080_EOF_MASK);
169 return reg_value;
170 }
171
lcd_disp_ll_set_display_int_i8080_eof(uint32_t value)172 static inline void lcd_disp_ll_set_display_int_i8080_eof(uint32_t value)
173 {
174 uint32_t reg_value;
175 reg_value = REG_READ(LCD_DISP_DISPLAY_INT_ADDR);
176 reg_value &= ~(LCD_DISP_DISPLAY_INT_I8080_EOF_MASK << LCD_DISP_DISPLAY_INT_I8080_EOF_POS);
177 reg_value |= ((value & LCD_DISP_DISPLAY_INT_I8080_EOF_MASK) << LCD_DISP_DISPLAY_INT_I8080_EOF_POS);
178 REG_WRITE(LCD_DISP_DISPLAY_INT_ADDR,reg_value);
179 }
180
181 /* REG_0x00:display_int->wr_thrd:0x0[17: 8],rgb fifo wr thrd,None,r/w*/
lcd_disp_ll_get_display_int_wr_thrd(void)182 static inline uint32_t lcd_disp_ll_get_display_int_wr_thrd(void)
183 {
184 uint32_t reg_value;
185 reg_value = REG_READ(LCD_DISP_DISPLAY_INT_ADDR);
186 reg_value = ((reg_value >> LCD_DISP_DISPLAY_INT_WR_THRD_POS) & LCD_DISP_DISPLAY_INT_WR_THRD_MASK);
187 return reg_value;
188 }
189
lcd_disp_ll_set_display_int_wr_thrd(uint32_t value)190 static inline void lcd_disp_ll_set_display_int_wr_thrd(uint32_t value)
191 {
192 uint32_t reg_value;
193 reg_value = REG_READ(LCD_DISP_DISPLAY_INT_ADDR);
194 reg_value &= ~(LCD_DISP_DISPLAY_INT_WR_THRD_MASK << LCD_DISP_DISPLAY_INT_WR_THRD_POS);
195 reg_value |= ((value & LCD_DISP_DISPLAY_INT_WR_THRD_MASK) << LCD_DISP_DISPLAY_INT_WR_THRD_POS);
196 REG_WRITE(LCD_DISP_DISPLAY_INT_ADDR,reg_value);
197 }
198
199 /* REG_0x00:display_int->rd_thrd:0x0[27:16],rgb fifo rd thrd,None,r/w*/
lcd_disp_ll_get_display_int_rd_thrd(void)200 static inline uint32_t lcd_disp_ll_get_display_int_rd_thrd(void)
201 {
202 uint32_t reg_value;
203 reg_value = REG_READ(LCD_DISP_DISPLAY_INT_ADDR);
204 reg_value = ((reg_value >> LCD_DISP_DISPLAY_INT_RD_THRD_POS) & LCD_DISP_DISPLAY_INT_RD_THRD_MASK);
205 return reg_value;
206 }
207
lcd_disp_ll_set_display_int_rd_thrd(uint32_t value)208 static inline void lcd_disp_ll_set_display_int_rd_thrd(uint32_t value)
209 {
210 uint32_t reg_value;
211 reg_value = REG_READ(LCD_DISP_DISPLAY_INT_ADDR);
212 reg_value &= ~(LCD_DISP_DISPLAY_INT_RD_THRD_MASK << LCD_DISP_DISPLAY_INT_RD_THRD_POS);
213 reg_value |= ((value & LCD_DISP_DISPLAY_INT_RD_THRD_MASK) << LCD_DISP_DISPLAY_INT_RD_THRD_POS);
214 REG_WRITE(LCD_DISP_DISPLAY_INT_ADDR,reg_value);
215 }
216
217 /* REG_0x00:display_int->disconti_mode:0x0[28],0：close，1：open,0x0,r/w*/
lcd_disp_ll_get_display_int_disconti_mode(void)218 static inline uint32_t lcd_disp_ll_get_display_int_disconti_mode(void)
219 {
220 uint32_t reg_value;
221 reg_value = REG_READ(LCD_DISP_DISPLAY_INT_ADDR);
222 reg_value = ((reg_value >> LCD_DISP_DISPLAY_INT_DISCONTI_MODE_POS) & LCD_DISP_DISPLAY_INT_DISCONTI_MODE_MASK);
223 return reg_value;
224 }
225
lcd_disp_ll_set_display_int_disconti_mode(uint32_t value)226 static inline void lcd_disp_ll_set_display_int_disconti_mode(uint32_t value)
227 {
228 uint32_t reg_value;
229 reg_value = REG_READ(LCD_DISP_DISPLAY_INT_ADDR);
230 reg_value &= ~(LCD_DISP_DISPLAY_INT_DISCONTI_MODE_MASK << LCD_DISP_DISPLAY_INT_DISCONTI_MODE_POS);
231 reg_value |= ((value & LCD_DISP_DISPLAY_INT_DISCONTI_MODE_MASK) << LCD_DISP_DISPLAY_INT_DISCONTI_MODE_POS);
232 REG_WRITE(LCD_DISP_DISPLAY_INT_ADDR,reg_value);
233 }
234
235 /* REG_0x01 */
236 #define LCD_DISP_STATUS_ADDR (LCD_DISP_LL_REG_BASE + 0x1*4) //REG ADDR :0x48060004
237 #define LCD_DISP_STATUS_X_PIXEL_POS (0)
238 #define LCD_DISP_STATUS_X_PIXEL_MASK (0x7FF)
239
240 #define LCD_DISP_STATUS_DCLK_REV_POS (11)
241 #define LCD_DISP_STATUS_DCLK_REV_MASK (0x1)
242
243 #define LCD_DISP_STATUS_Y_PIXEL_POS (12)
244 #define LCD_DISP_STATUS_Y_PIXEL_MASK (0x7FF)
245
246 #define LCD_DISP_STATUS_STR_FIFO_CLR_POS (23)
247 #define LCD_DISP_STATUS_STR_FIFO_CLR_MASK (0x1)
248
249 #define LCD_DISP_STATUS_RGB_DISP_ON_POS (24)
250 #define LCD_DISP_STATUS_RGB_DISP_ON_MASK (0x1)
251
252 #define LCD_DISP_STATUS_RGB_ON_POS (25)
253 #define LCD_DISP_STATUS_RGB_ON_MASK (0x1)
254
255 #define LCD_DISP_STATUS_LCD_DISPLAY_ON_POS (26)
256 #define LCD_DISP_STATUS_LCD_DISPLAY_ON_MASK (0x1)
257
258 #define LCD_DISP_STATUS_RGB_CLK_DIV_POS (27)
259 #define LCD_DISP_STATUS_RGB_CLK_DIV_MASK (0x1f)
260
lcd_disp_ll_get_status_value(void)261 static inline uint32_t lcd_disp_ll_get_status_value(void)
262 {
263 return REG_READ(LCD_DISP_STATUS_ADDR);
264 }
265
lcd_disp_ll_set_status_value(uint32_t value)266 static inline void lcd_disp_ll_set_status_value(uint32_t value)
267 {
268 REG_WRITE(LCD_DISP_STATUS_ADDR,value);
269 }
270
271 /* REG_0x01:status->x_pixel:0x1[10: 0], ,0x1E0,r/w*/
lcd_disp_ll_get_status_x_pixel(void)272 static inline uint32_t lcd_disp_ll_get_status_x_pixel(void)
273 {
274 uint32_t reg_value;
275 reg_value = REG_READ(LCD_DISP_STATUS_ADDR);
276 reg_value = ((reg_value >> LCD_DISP_STATUS_X_PIXEL_POS) & LCD_DISP_STATUS_X_PIXEL_MASK);
277 return reg_value;
278 }
279
lcd_disp_ll_set_status_x_pixel(uint32_t value)280 static inline void lcd_disp_ll_set_status_x_pixel(uint32_t value)
281 {
282 uint32_t reg_value;
283 reg_value = REG_READ(LCD_DISP_STATUS_ADDR);
284 reg_value &= ~(LCD_DISP_STATUS_X_PIXEL_MASK << LCD_DISP_STATUS_X_PIXEL_POS);
285 reg_value |= ((value & LCD_DISP_STATUS_X_PIXEL_MASK) << LCD_DISP_STATUS_X_PIXEL_POS);
286 REG_WRITE(LCD_DISP_STATUS_ADDR,reg_value);
287 }
288
289 /* REG_0x01:status->dclk_rev:0x1[ 11],rgb output edge sel：posedge；1：negedge。,0x0,r/w*/
lcd_disp_ll_get_status_dclk_rev(void)290 static inline uint32_t lcd_disp_ll_get_status_dclk_rev(void)
291 {
292 uint32_t reg_value;
293 reg_value = REG_READ(LCD_DISP_STATUS_ADDR);
294 reg_value = ((reg_value >> LCD_DISP_STATUS_DCLK_REV_POS) & LCD_DISP_STATUS_DCLK_REV_MASK);
295 return reg_value;
296 }
297
lcd_disp_ll_set_status_dclk_rev(uint32_t value)298 static inline void lcd_disp_ll_set_status_dclk_rev(uint32_t value)
299 {
300 uint32_t reg_value;
301 reg_value = REG_READ(LCD_DISP_STATUS_ADDR);
302 reg_value &= ~(LCD_DISP_STATUS_DCLK_REV_MASK << LCD_DISP_STATUS_DCLK_REV_POS);
303 reg_value |= ((value & LCD_DISP_STATUS_DCLK_REV_MASK) << LCD_DISP_STATUS_DCLK_REV_POS);
304 REG_WRITE(LCD_DISP_STATUS_ADDR,reg_value);
305 }
306
307 /* REG_0x01:status->y_pixel:0x1[22:12], ,0x110,r/w*/
lcd_disp_ll_get_status_y_pixel(void)308 static inline uint32_t lcd_disp_ll_get_status_y_pixel(void)
309 {
310 uint32_t reg_value;
311 reg_value = REG_READ(LCD_DISP_STATUS_ADDR);
312 reg_value = ((reg_value >> LCD_DISP_STATUS_Y_PIXEL_POS) & LCD_DISP_STATUS_Y_PIXEL_MASK);
313 return reg_value;
314 }
315
lcd_disp_ll_set_status_y_pixel(uint32_t value)316 static inline void lcd_disp_ll_set_status_y_pixel(uint32_t value)
317 {
318 uint32_t reg_value;
319 reg_value = REG_READ(LCD_DISP_STATUS_ADDR);
320 reg_value &= ~(LCD_DISP_STATUS_Y_PIXEL_MASK << LCD_DISP_STATUS_Y_PIXEL_POS);
321 reg_value |= ((value & LCD_DISP_STATUS_Y_PIXEL_MASK) << LCD_DISP_STATUS_Y_PIXEL_POS);
322 REG_WRITE(LCD_DISP_STATUS_ADDR,reg_value);
323 }
324
325 /* REG_0x01:status->str_fifo_clr:0x1[ 23],rgb stream_fifo rst,not used,0x0,r/w*/
lcd_disp_ll_get_status_str_fifo_clr(void)326 static inline uint32_t lcd_disp_ll_get_status_str_fifo_clr(void)
327 {
328 uint32_t reg_value;
329 reg_value = REG_READ(LCD_DISP_STATUS_ADDR);
330 reg_value = ((reg_value >> LCD_DISP_STATUS_STR_FIFO_CLR_POS) & LCD_DISP_STATUS_STR_FIFO_CLR_MASK);
331 return reg_value;
332 }
333
lcd_disp_ll_set_status_str_fifo_clr(uint32_t value)334 static inline void lcd_disp_ll_set_status_str_fifo_clr(uint32_t value)
335 {
336 uint32_t reg_value;
337 reg_value = REG_READ(LCD_DISP_STATUS_ADDR);
338 reg_value &= ~(LCD_DISP_STATUS_STR_FIFO_CLR_MASK << LCD_DISP_STATUS_STR_FIFO_CLR_POS);
339 reg_value |= ((value & LCD_DISP_STATUS_STR_FIFO_CLR_MASK) << LCD_DISP_STATUS_STR_FIFO_CLR_POS);
340 REG_WRITE(LCD_DISP_STATUS_ADDR,reg_value);
341 }
342
343 /* REG_0x01:status->rgb_disp_on:0x1[ 24],rgb display enable,0x0,r/w*/
lcd_disp_ll_get_status_rgb_disp_on(void)344 static inline uint32_t lcd_disp_ll_get_status_rgb_disp_on(void)
345 {
346 uint32_t reg_value;
347 reg_value = REG_READ(LCD_DISP_STATUS_ADDR);
348 reg_value = ((reg_value >> LCD_DISP_STATUS_RGB_DISP_ON_POS) & LCD_DISP_STATUS_RGB_DISP_ON_MASK);
349 return reg_value;
350 }
351
lcd_disp_ll_set_status_rgb_disp_on(uint32_t value)352 static inline void lcd_disp_ll_set_status_rgb_disp_on(uint32_t value)
353 {
354 uint32_t reg_value;
355 reg_value = REG_READ(LCD_DISP_STATUS_ADDR);
356 reg_value &= ~(LCD_DISP_STATUS_RGB_DISP_ON_MASK << LCD_DISP_STATUS_RGB_DISP_ON_POS);
357 reg_value |= ((value & LCD_DISP_STATUS_RGB_DISP_ON_MASK) << LCD_DISP_STATUS_RGB_DISP_ON_POS);
358 REG_WRITE(LCD_DISP_STATUS_ADDR,reg_value);
359 }
360
361 /* REG_0x01:status->rgb_on:0x1[ 25],Rgb module IO 1：rgb output。0：not rgb output,0x0,r/w*/
lcd_disp_ll_get_status_rgb_on(void)362 static inline uint32_t lcd_disp_ll_get_status_rgb_on(void)
363 {
364 uint32_t reg_value;
365 reg_value = REG_READ(LCD_DISP_STATUS_ADDR);
366 reg_value = ((reg_value >> LCD_DISP_STATUS_RGB_ON_POS) & LCD_DISP_STATUS_RGB_ON_MASK);
367 return reg_value;
368 }
369
lcd_disp_ll_set_status_rgb_on(uint32_t value)370 static inline void lcd_disp_ll_set_status_rgb_on(uint32_t value)
371 {
372 uint32_t reg_value;
373 reg_value = REG_READ(LCD_DISP_STATUS_ADDR);
374 reg_value &= ~(LCD_DISP_STATUS_RGB_ON_MASK << LCD_DISP_STATUS_RGB_ON_POS);
375 reg_value |= ((value & LCD_DISP_STATUS_RGB_ON_MASK) << LCD_DISP_STATUS_RGB_ON_POS);
376 REG_WRITE(LCD_DISP_STATUS_ADDR,reg_value);
377 }
378
379 /* REG_0x01:status->lcd_display_on:0x1[ 26],lcd,0x0,r/w*/
lcd_disp_ll_get_status_lcd_display_on(void)380 static inline uint32_t lcd_disp_ll_get_status_lcd_display_on(void)
381 {
382 uint32_t reg_value;
383 reg_value = REG_READ(LCD_DISP_STATUS_ADDR);
384 reg_value = ((reg_value >> LCD_DISP_STATUS_LCD_DISPLAY_ON_POS) & LCD_DISP_STATUS_LCD_DISPLAY_ON_MASK);
385 return reg_value;
386 }
387
lcd_disp_ll_set_status_lcd_display_on(uint32_t value)388 static inline void lcd_disp_ll_set_status_lcd_display_on(uint32_t value)
389 {
390 uint32_t reg_value;
391 reg_value = REG_READ(LCD_DISP_STATUS_ADDR);
392 reg_value &= ~(LCD_DISP_STATUS_LCD_DISPLAY_ON_MASK << LCD_DISP_STATUS_LCD_DISPLAY_ON_POS);
393 reg_value |= ((value & LCD_DISP_STATUS_LCD_DISPLAY_ON_MASK) << LCD_DISP_STATUS_LCD_DISPLAY_ON_POS);
394 REG_WRITE(LCD_DISP_STATUS_ADDR,reg_value);
395 }
396
397 /* REG_0x01:status->rgb_clk_div:0x1[29:27],00：9mhz， 01：5mhz，10：12mhz。11：nc,0x0,r/w */
lcd_disp_ll_get_status_rgb_clk_div(void)398 static inline uint32_t lcd_disp_ll_get_status_rgb_clk_div(void)
399 {
400 uint32_t reg_value;
401 reg_value = REG_READ(LCD_DISP_STATUS_ADDR);
402 reg_value = ((reg_value >> LCD_DISP_STATUS_RGB_CLK_DIV_POS) & LCD_DISP_STATUS_RGB_CLK_DIV_MASK);
403 return reg_value;
404 }
405
lcd_disp_ll_set_status_rgb_clk_div(uint32_t value)406 static inline void lcd_disp_ll_set_status_rgb_clk_div(uint32_t value)
407 {
408 uint32_t reg_value;
409 reg_value = REG_READ(LCD_DISP_STATUS_ADDR);
410 reg_value &= ~(LCD_DISP_STATUS_RGB_CLK_DIV_MASK << LCD_DISP_STATUS_RGB_CLK_DIV_POS);
411 reg_value |= ((value & LCD_DISP_STATUS_RGB_CLK_DIV_MASK) << LCD_DISP_STATUS_RGB_CLK_DIV_POS);
412 REG_WRITE(LCD_DISP_STATUS_ADDR,reg_value);
413 }
414
415
416 /* REG_0x02 */
417 #define LCD_DISP_RGB_FIFO_ADDR (LCD_DISP_LL_REG_BASE + 0x2*4) //REG ADDR :0x48060008
418 #define LCD_DISP_RGB_FIFO_RGB_DAT_POS (0)
419 #define LCD_DISP_RGB_FIFO_RGB_DAT_MASK (0xFFFF)
420
421 #define LCD_DISP_RGB_FIFO_RESERVED_POS (16)
422 #define LCD_DISP_RGB_FIFO_RESERVED_MASK (0xFFFF)
423
lcd_disp_ll_set_rgb_fifo_value(uint32_t value)424 static inline void lcd_disp_ll_set_rgb_fifo_value(uint32_t value)
425 {
426 REG_WRITE(LCD_DISP_RGB_FIFO_ADDR,value);
427 }
428
429 /* REG_0x02:rgb_fifo->rgb_dat:0x2[15: 0], rgb data move to this reg by dma,0x0,w*/
lcd_disp_ll_set_rgb_fifo_rgb_dat(uint32_t value)430 static inline void lcd_disp_ll_set_rgb_fifo_rgb_dat(uint32_t value)
431 {
432 uint32_t reg_value;
433 reg_value = REG_READ(LCD_DISP_RGB_FIFO_ADDR);
434 reg_value &= ~(LCD_DISP_RGB_FIFO_RGB_DAT_MASK << LCD_DISP_RGB_FIFO_RGB_DAT_POS);
435 reg_value |= ((value & LCD_DISP_RGB_FIFO_RGB_DAT_MASK) << LCD_DISP_RGB_FIFO_RGB_DAT_POS);
436 REG_WRITE(LCD_DISP_RGB_FIFO_ADDR,reg_value);
437 }
438
439 /* REG_0x03 */
440 #define LCD_DISP_HSYNC_VSYNC_CFG_ADDR (LCD_DISP_LL_REG_BASE + 0x3*4) //REG ADDR :0x4806000c
441 #define LCD_DISP_HSYNC_VSYNC_CFG_HSYNC_BACK_PORCH_POS (0)
442 #define LCD_DISP_HSYNC_VSYNC_CFG_HSYNC_BACK_PORCH_MASK (0xFF)
443
444 #define LCD_DISP_HSYNC_VSYNC_CFG_HSYNC_FRONT_PORCH_POS (8)
445 #define LCD_DISP_HSYNC_VSYNC_CFG_HSYNC_FRONT_PORCH_MASK (0x7F)
446
447 #define LCD_DISP_HSYNC_VSYNC_CFG_VSYNC_BACK_PORCH_POS (15)
448 #define LCD_DISP_HSYNC_VSYNC_CFG_VSYNC_BACK_PORCH_MASK (0x1F)
449
450 #define LCD_DISP_HSYNC_VSYNC_CFG_VSYNC_FRONT_PORCH_POS (20)
451 #define LCD_DISP_HSYNC_VSYNC_CFG_VSYNC_FRONT_PORCH_MASK (0x7F)
452
453 #define LCD_DISP_HSYNC_VSYNC_CFG_YUV_SEL_POS (28)
454 #define LCD_DISP_HSYNC_VSYNC_CFG_YUV_SEL_MASK (0x7)
455
456 #define LCD_DISP_HSYNC_VSYNC_CFG_RESERVED_POS (31)
457 #define LCD_DISP_HSYNC_VSYNC_CFG_RESERVED_MASK (0x1)
458
lcd_disp_ll_get_hsync_vsync_cfg_value(void)459 static inline uint32_t lcd_disp_ll_get_hsync_vsync_cfg_value(void)
460 {
461 return REG_READ(LCD_DISP_HSYNC_VSYNC_CFG_ADDR);
462 }
463
lcd_disp_ll_set_hsync_vsync_cfg_value(uint32_t value)464 static inline void lcd_disp_ll_set_hsync_vsync_cfg_value(uint32_t value)
465 {
466 REG_WRITE(LCD_DISP_HSYNC_VSYNC_CFG_ADDR,value);
467 }
468
469 /* REG_0x03:hsync_vsync_cfg->hsync_back_porch:0x3[ 7: 0], ,40,r/w*/
lcd_disp_ll_get_hsync_vsync_cfg_hsync_back_porch(void)470 static inline uint32_t lcd_disp_ll_get_hsync_vsync_cfg_hsync_back_porch(void)
471 {
472 uint32_t reg_value;
473 reg_value = REG_READ(LCD_DISP_HSYNC_VSYNC_CFG_ADDR);
474 reg_value = ((reg_value >> LCD_DISP_HSYNC_VSYNC_CFG_HSYNC_BACK_PORCH_POS) & LCD_DISP_HSYNC_VSYNC_CFG_HSYNC_BACK_PORCH_MASK);
475 return reg_value;
476 }
477
lcd_disp_ll_set_hsync_vsync_cfg_hsync_back_porch(uint32_t value)478 static inline void lcd_disp_ll_set_hsync_vsync_cfg_hsync_back_porch(uint32_t value)
479 {
480 uint32_t reg_value;
481 reg_value = REG_READ(LCD_DISP_HSYNC_VSYNC_CFG_ADDR);
482 reg_value &= ~(LCD_DISP_HSYNC_VSYNC_CFG_HSYNC_BACK_PORCH_MASK << LCD_DISP_HSYNC_VSYNC_CFG_HSYNC_BACK_PORCH_POS);
483 reg_value |= ((value & LCD_DISP_HSYNC_VSYNC_CFG_HSYNC_BACK_PORCH_MASK) << LCD_DISP_HSYNC_VSYNC_CFG_HSYNC_BACK_PORCH_POS);
484 REG_WRITE(LCD_DISP_HSYNC_VSYNC_CFG_ADDR,reg_value);
485 }
486
487 /* REG_0x03:hsync_vsync_cfg->hsync_front_porch:0x3[14: 8], ,5,r/w*/
lcd_disp_ll_get_hsync_vsync_cfg_hsync_front_porch(void)488 static inline uint32_t lcd_disp_ll_get_hsync_vsync_cfg_hsync_front_porch(void)
489 {
490 uint32_t reg_value;
491 reg_value = REG_READ(LCD_DISP_HSYNC_VSYNC_CFG_ADDR);
492 reg_value = ((reg_value >> LCD_DISP_HSYNC_VSYNC_CFG_HSYNC_FRONT_PORCH_POS) & LCD_DISP_HSYNC_VSYNC_CFG_HSYNC_FRONT_PORCH_MASK);
493 return reg_value;
494 }
495
lcd_disp_ll_set_hsync_vsync_cfg_hsync_front_porch(uint32_t value)496 static inline void lcd_disp_ll_set_hsync_vsync_cfg_hsync_front_porch(uint32_t value)
497 {
498 uint32_t reg_value;
499 reg_value = REG_READ(LCD_DISP_HSYNC_VSYNC_CFG_ADDR);
500 reg_value &= ~(LCD_DISP_HSYNC_VSYNC_CFG_HSYNC_FRONT_PORCH_MASK << LCD_DISP_HSYNC_VSYNC_CFG_HSYNC_FRONT_PORCH_POS);
501 reg_value |= ((value & LCD_DISP_HSYNC_VSYNC_CFG_HSYNC_FRONT_PORCH_MASK) << LCD_DISP_HSYNC_VSYNC_CFG_HSYNC_FRONT_PORCH_POS);
502 REG_WRITE(LCD_DISP_HSYNC_VSYNC_CFG_ADDR,reg_value);
503 }
504
505 /* REG_0x03:hsync_vsync_cfg->vsync_back_porch:0x3[19:15], ,8,r/w*/
lcd_disp_ll_get_hsync_vsync_cfg_vsync_back_porch(void)506 static inline uint32_t lcd_disp_ll_get_hsync_vsync_cfg_vsync_back_porch(void)
507 {
508 uint32_t reg_value;
509 reg_value = REG_READ(LCD_DISP_HSYNC_VSYNC_CFG_ADDR);
510 reg_value = ((reg_value >> LCD_DISP_HSYNC_VSYNC_CFG_VSYNC_BACK_PORCH_POS) & LCD_DISP_HSYNC_VSYNC_CFG_VSYNC_BACK_PORCH_MASK);
511 return reg_value;
512 }
513
lcd_disp_ll_set_hsync_vsync_cfg_vsync_back_porch(uint32_t value)514 static inline void lcd_disp_ll_set_hsync_vsync_cfg_vsync_back_porch(uint32_t value)
515 {
516 uint32_t reg_value;
517 reg_value = REG_READ(LCD_DISP_HSYNC_VSYNC_CFG_ADDR);
518 reg_value &= ~(LCD_DISP_HSYNC_VSYNC_CFG_VSYNC_BACK_PORCH_MASK << LCD_DISP_HSYNC_VSYNC_CFG_VSYNC_BACK_PORCH_POS);
519 reg_value |= ((value & LCD_DISP_HSYNC_VSYNC_CFG_VSYNC_BACK_PORCH_MASK) << LCD_DISP_HSYNC_VSYNC_CFG_VSYNC_BACK_PORCH_POS);
520 REG_WRITE(LCD_DISP_HSYNC_VSYNC_CFG_ADDR,reg_value);
521 }
522
523 /* REG_0x03:hsync_vsync_cfg->vsync_front_porch:0x3[26:20], ,8,r/w*/
lcd_disp_ll_get_hsync_vsync_cfg_vsync_front_porch(void)524 static inline uint32_t lcd_disp_ll_get_hsync_vsync_cfg_vsync_front_porch(void)
525 {
526 uint32_t reg_value;
527 reg_value = REG_READ(LCD_DISP_HSYNC_VSYNC_CFG_ADDR);
528 reg_value = ((reg_value >> LCD_DISP_HSYNC_VSYNC_CFG_VSYNC_FRONT_PORCH_POS) & LCD_DISP_HSYNC_VSYNC_CFG_VSYNC_FRONT_PORCH_MASK);
529 return reg_value;
530 }
531
lcd_disp_ll_set_hsync_vsync_cfg_vsync_front_porch(uint32_t value)532 static inline void lcd_disp_ll_set_hsync_vsync_cfg_vsync_front_porch(uint32_t value)
533 {
534 uint32_t reg_value;
535 reg_value = REG_READ(LCD_DISP_HSYNC_VSYNC_CFG_ADDR);
536 reg_value &= ~(LCD_DISP_HSYNC_VSYNC_CFG_VSYNC_FRONT_PORCH_MASK << LCD_DISP_HSYNC_VSYNC_CFG_VSYNC_FRONT_PORCH_POS);
537 reg_value |= ((value & LCD_DISP_HSYNC_VSYNC_CFG_VSYNC_FRONT_PORCH_MASK) << LCD_DISP_HSYNC_VSYNC_CFG_VSYNC_FRONT_PORCH_POS);
538 REG_WRITE(LCD_DISP_HSYNC_VSYNC_CFG_ADDR,reg_value);
539 }
540
541 /* REG_0x03:hsync_vsync_cfg->yuv_sel:0x3[30:28], ,0,r/w*/
lcd_disp_ll_get_hsync_vsync_cfg_yuv_sel(void)542 static inline uint32_t lcd_disp_ll_get_hsync_vsync_cfg_yuv_sel(void)
543 {
544 uint32_t reg_value;
545 reg_value = REG_READ(LCD_DISP_HSYNC_VSYNC_CFG_ADDR);
546 reg_value = ((reg_value >> LCD_DISP_HSYNC_VSYNC_CFG_YUV_SEL_POS) & LCD_DISP_HSYNC_VSYNC_CFG_YUV_SEL_MASK);
547 return reg_value;
548 }
549
lcd_disp_ll_set_hsync_vsync_cfg_yuv_sel(uint32_t value)550 static inline void lcd_disp_ll_set_hsync_vsync_cfg_yuv_sel(uint32_t value)
551 {
552 uint32_t reg_value;
553 reg_value = REG_READ(LCD_DISP_HSYNC_VSYNC_CFG_ADDR);
554 reg_value &= ~(LCD_DISP_HSYNC_VSYNC_CFG_YUV_SEL_MASK << LCD_DISP_HSYNC_VSYNC_CFG_YUV_SEL_POS);
555 reg_value |= ((value & LCD_DISP_HSYNC_VSYNC_CFG_YUV_SEL_MASK) << LCD_DISP_HSYNC_VSYNC_CFG_YUV_SEL_POS);
556 REG_WRITE(LCD_DISP_HSYNC_VSYNC_CFG_ADDR,reg_value);
557 }
558
559 /* REG_0x04 */
560 #define LCD_DISP_I8080_CONFIG_ADDR (LCD_DISP_LL_REG_BASE + 0x4*4) //REG ADDR :0x48060010
561 #define LCD_DISP_I8080_CONFIG_I8080_DISP_EN_POS (0)
562 #define LCD_DISP_I8080_CONFIG_I8080_DISP_EN_MASK (0x1)
563
564 #define LCD_DISP_I8080_CONFIG_I8080_DAT_ON_POS (1)
565 #define LCD_DISP_I8080_CONFIG_I8080_DAT_ON_MASK (0x1)
566
567 #define LCD_DISP_I8080_CONFIG_I8080_FIFO_MODE_POS (2)
568 #define LCD_DISP_I8080_CONFIG_I8080_FIFO_MODE_MASK (0x1)
569
570 #define LCD_DISP_I8080_CONFIG_I8080_FIFO_CLR_POS (3)
571 #define LCD_DISP_I8080_CONFIG_I8080_FIFO_CLR_MASK (0x1)
572
573 #define LCD_DISP_I8080_CONFIG_I8080_CMDFIFO_CLR_POS (4)
574 #define LCD_DISP_I8080_CONFIG_I8080_CMDFIFO_CLR_MASK (0x1)
575
576 #define LCD_DISP_I8080_CONFIG_RESET_SLEEP_IN_POS (5)
577 #define LCD_DISP_I8080_CONFIG_RESET_SLEEP_IN_MASK (0x1)
578
579 #define LCD_DISP_I8080_CONFIG_RESERVED1_POS (6)
580 #define LCD_DISP_I8080_CONFIG_RESERVED1_MASK (0x3)
581
582 #define LCD_DISP_I8080_CONFIG_TIK_CNT_POS (8)
583 #define LCD_DISP_I8080_CONFIG_TIK_CNT_MASK (0x3)
584
585 #define LCD_DISP_I8080_CONFIG_RESERVED2_POS (10)
586 #define LCD_DISP_I8080_CONFIG_RESERVED2_MASK (0x3)
587
588 #define LCD_DISP_I8080_CONFIG_I8080_1MS_COUNT_POS (12)
589 #define LCD_DISP_I8080_CONFIG_I8080_1MS_COUNT_MASK (0x1FF)
590
591 #define LCD_DISP_I8080_CONFIG_RESERVED3_POS (21)
592 #define LCD_DISP_I8080_CONFIG_RESERVED3_MASK (0x7FF)
593
lcd_disp_ll_get_i8080_config_value(void)594 static inline uint32_t lcd_disp_ll_get_i8080_config_value(void)
595 {
596 return REG_READ(LCD_DISP_I8080_CONFIG_ADDR);
597 }
598
lcd_disp_ll_set_i8080_config_value(uint32_t value)599 static inline void lcd_disp_ll_set_i8080_config_value(uint32_t value)
600 {
601 REG_WRITE(LCD_DISP_I8080_CONFIG_ADDR,value);
602 }
603
604 /* REG_0x04:i8080_config->i8080_disp_en:0x4[ 0],i8080 function enable,0x0,r/w*/
lcd_disp_ll_get_i8080_config_i8080_disp_en(void)605 static inline uint32_t lcd_disp_ll_get_i8080_config_i8080_disp_en(void)
606 {
607 uint32_t reg_value;
608 reg_value = REG_READ(LCD_DISP_I8080_CONFIG_ADDR);
609 reg_value = ((reg_value >> LCD_DISP_I8080_CONFIG_I8080_DISP_EN_POS) & LCD_DISP_I8080_CONFIG_I8080_DISP_EN_MASK);
610 return reg_value;
611 }
612
lcd_disp_ll_set_i8080_config_i8080_disp_en(uint32_t value)613 static inline void lcd_disp_ll_set_i8080_config_i8080_disp_en(uint32_t value)
614 {
615 uint32_t reg_value;
616 reg_value = REG_READ(LCD_DISP_I8080_CONFIG_ADDR);
617 reg_value &= ~(LCD_DISP_I8080_CONFIG_I8080_DISP_EN_MASK << LCD_DISP_I8080_CONFIG_I8080_DISP_EN_POS);
618 reg_value |= ((value & LCD_DISP_I8080_CONFIG_I8080_DISP_EN_MASK) << LCD_DISP_I8080_CONFIG_I8080_DISP_EN_POS);
619 REG_WRITE(LCD_DISP_I8080_CONFIG_ADDR,reg_value);
620 }
621
622 /* REG_0x04:i8080_config->i8080_dat_on:0x4[ 1],i8080 data start transfer,0x0,r/w*/
lcd_disp_ll_get_i8080_config_i8080_dat_on(void)623 static inline uint32_t lcd_disp_ll_get_i8080_config_i8080_dat_on(void)
624 {
625 uint32_t reg_value;
626 reg_value = REG_READ(LCD_DISP_I8080_CONFIG_ADDR);
627 reg_value = ((reg_value >> LCD_DISP_I8080_CONFIG_I8080_DAT_ON_POS) & LCD_DISP_I8080_CONFIG_I8080_DAT_ON_MASK);
628 return reg_value;
629 }
630
lcd_disp_ll_set_i8080_config_i8080_dat_on(uint32_t value)631 static inline void lcd_disp_ll_set_i8080_config_i8080_dat_on(uint32_t value)
632 {
633 uint32_t reg_value;
634 reg_value = REG_READ(LCD_DISP_I8080_CONFIG_ADDR);
635 reg_value &= ~(LCD_DISP_I8080_CONFIG_I8080_DAT_ON_MASK << LCD_DISP_I8080_CONFIG_I8080_DAT_ON_POS);
636 reg_value |= ((value & LCD_DISP_I8080_CONFIG_I8080_DAT_ON_MASK) << LCD_DISP_I8080_CONFIG_I8080_DAT_ON_POS);
637 REG_WRITE(LCD_DISP_I8080_CONFIG_ADDR,reg_value);
638 }
639
640 /* REG_0x04:i8080_config->i8080_fifo_mode:0x4[ 2], ,0x0,r/w*/
lcd_disp_ll_get_i8080_config_i8080_fifo_mode(void)641 static inline uint32_t lcd_disp_ll_get_i8080_config_i8080_fifo_mode(void)
642 {
643 uint32_t reg_value;
644 reg_value = REG_READ(LCD_DISP_I8080_CONFIG_ADDR);
645 reg_value = ((reg_value >> LCD_DISP_I8080_CONFIG_I8080_FIFO_MODE_POS) & LCD_DISP_I8080_CONFIG_I8080_FIFO_MODE_MASK);
646 return reg_value;
647 }
648
lcd_disp_ll_set_i8080_config_i8080_fifo_mode(uint32_t value)649 static inline void lcd_disp_ll_set_i8080_config_i8080_fifo_mode(uint32_t value)
650 {
651 uint32_t reg_value;
652 reg_value = REG_READ(LCD_DISP_I8080_CONFIG_ADDR);
653 reg_value &= ~(LCD_DISP_I8080_CONFIG_I8080_FIFO_MODE_MASK << LCD_DISP_I8080_CONFIG_I8080_FIFO_MODE_POS);
654 reg_value |= ((value & LCD_DISP_I8080_CONFIG_I8080_FIFO_MODE_MASK) << LCD_DISP_I8080_CONFIG_I8080_FIFO_MODE_POS);
655 REG_WRITE(LCD_DISP_I8080_CONFIG_ADDR,reg_value);
656 }
657
658 /* REG_0x04:i8080_config->i8080_fifo_clr:0x4[ 3],i8080 data_fifo rst,0x0,r/w*/
lcd_disp_ll_get_i8080_config_i8080_fifo_clr(void)659 static inline uint32_t lcd_disp_ll_get_i8080_config_i8080_fifo_clr(void)
660 {
661 uint32_t reg_value;
662 reg_value = REG_READ(LCD_DISP_I8080_CONFIG_ADDR);
663 reg_value = ((reg_value >> LCD_DISP_I8080_CONFIG_I8080_FIFO_CLR_POS) & LCD_DISP_I8080_CONFIG_I8080_FIFO_CLR_MASK);
664 return reg_value;
665 }
666
lcd_disp_ll_set_i8080_config_i8080_fifo_clr(uint32_t value)667 static inline void lcd_disp_ll_set_i8080_config_i8080_fifo_clr(uint32_t value)
668 {
669 uint32_t reg_value;
670 reg_value = REG_READ(LCD_DISP_I8080_CONFIG_ADDR);
671 reg_value &= ~(LCD_DISP_I8080_CONFIG_I8080_FIFO_CLR_MASK << LCD_DISP_I8080_CONFIG_I8080_FIFO_CLR_POS);
672 reg_value |= ((value & LCD_DISP_I8080_CONFIG_I8080_FIFO_CLR_MASK) << LCD_DISP_I8080_CONFIG_I8080_FIFO_CLR_POS);
673 REG_WRITE(LCD_DISP_I8080_CONFIG_ADDR,reg_value);
674 }
675
676 /* REG_0x04:i8080_config->i8080_cmdfifo_clr:0x4[ 4],i8080 cmd_fifo rst,0x0,r/w*/
lcd_disp_ll_get_i8080_config_i8080_cmdfifo_clr(void)677 static inline uint32_t lcd_disp_ll_get_i8080_config_i8080_cmdfifo_clr(void)
678 {
679 uint32_t reg_value;
680 reg_value = REG_READ(LCD_DISP_I8080_CONFIG_ADDR);
681 reg_value = ((reg_value >> LCD_DISP_I8080_CONFIG_I8080_CMDFIFO_CLR_POS) & LCD_DISP_I8080_CONFIG_I8080_CMDFIFO_CLR_MASK);
682 return reg_value;
683 }
684
lcd_disp_ll_set_i8080_config_i8080_cmdfifo_clr(uint32_t value)685 static inline void lcd_disp_ll_set_i8080_config_i8080_cmdfifo_clr(uint32_t value)
686 {
687 uint32_t reg_value;
688 reg_value = REG_READ(LCD_DISP_I8080_CONFIG_ADDR);
689 reg_value &= ~(LCD_DISP_I8080_CONFIG_I8080_CMDFIFO_CLR_MASK << LCD_DISP_I8080_CONFIG_I8080_CMDFIFO_CLR_POS);
690 reg_value |= ((value & LCD_DISP_I8080_CONFIG_I8080_CMDFIFO_CLR_MASK) << LCD_DISP_I8080_CONFIG_I8080_CMDFIFO_CLR_POS);
691 REG_WRITE(LCD_DISP_I8080_CONFIG_ADDR,reg_value);
692 }
693
694 /* REG_0x04:i8080_config->reset_sleep_in:0x4[ 5], ,0x0,r/w*/
lcd_disp_ll_get_i8080_config_reset_sleep_in(void)695 static inline uint32_t lcd_disp_ll_get_i8080_config_reset_sleep_in(void)
696 {
697 uint32_t reg_value;
698 reg_value = REG_READ(LCD_DISP_I8080_CONFIG_ADDR);
699 reg_value = ((reg_value >> LCD_DISP_I8080_CONFIG_RESET_SLEEP_IN_POS) & LCD_DISP_I8080_CONFIG_RESET_SLEEP_IN_MASK);
700 return reg_value;
701 }
702
lcd_disp_ll_set_i8080_config_reset_sleep_in(uint32_t value)703 static inline void lcd_disp_ll_set_i8080_config_reset_sleep_in(uint32_t value)
704 {
705 uint32_t reg_value;
706 reg_value = REG_READ(LCD_DISP_I8080_CONFIG_ADDR);
707 reg_value &= ~(LCD_DISP_I8080_CONFIG_RESET_SLEEP_IN_MASK << LCD_DISP_I8080_CONFIG_RESET_SLEEP_IN_POS);
708 reg_value |= ((value & LCD_DISP_I8080_CONFIG_RESET_SLEEP_IN_MASK) << LCD_DISP_I8080_CONFIG_RESET_SLEEP_IN_POS);
709 REG_WRITE(LCD_DISP_I8080_CONFIG_ADDR,reg_value);
710 }
711
712 /* REG_0x04:i8080_config->tik_cnt:0x4[ 9:8],。0：8clk；1：6clk；2：4clk；3：2clk。,0x0,r/w*/
lcd_disp_ll_get_i8080_config_tik_cnt(void)713 static inline uint32_t lcd_disp_ll_get_i8080_config_tik_cnt(void)
714 {
715 uint32_t reg_value;
716 reg_value = REG_READ(LCD_DISP_I8080_CONFIG_ADDR);
717 reg_value = ((reg_value >> LCD_DISP_I8080_CONFIG_TIK_CNT_POS) & LCD_DISP_I8080_CONFIG_TIK_CNT_MASK);
718 return reg_value;
719 }
720
lcd_disp_ll_set_i8080_config_tik_cnt(uint32_t value)721 static inline void lcd_disp_ll_set_i8080_config_tik_cnt(uint32_t value)
722 {
723 uint32_t reg_value;
724 reg_value = REG_READ(LCD_DISP_I8080_CONFIG_ADDR);
725 reg_value &= ~(LCD_DISP_I8080_CONFIG_TIK_CNT_MASK << LCD_DISP_I8080_CONFIG_TIK_CNT_POS);
726 reg_value |= ((value & LCD_DISP_I8080_CONFIG_TIK_CNT_MASK) << LCD_DISP_I8080_CONFIG_TIK_CNT_POS);
727 REG_WRITE(LCD_DISP_I8080_CONFIG_ADDR,reg_value);
728 }
729
730 /* REG_0x04:i8080_config->i8080_1ms_count:0x4[ 20:12], ,0x0,r/w*/
lcd_disp_ll_get_i8080_config_i8080_1ms_count(void)731 static inline uint32_t lcd_disp_ll_get_i8080_config_i8080_1ms_count(void)
732 {
733 uint32_t reg_value;
734 reg_value = REG_READ(LCD_DISP_I8080_CONFIG_ADDR);
735 reg_value = ((reg_value >> LCD_DISP_I8080_CONFIG_I8080_1MS_COUNT_POS) & LCD_DISP_I8080_CONFIG_I8080_1MS_COUNT_MASK);
736 return reg_value;
737 }
738
lcd_disp_ll_set_i8080_config_i8080_1ms_count(uint32_t value)739 static inline void lcd_disp_ll_set_i8080_config_i8080_1ms_count(uint32_t value)
740 {
741 uint32_t reg_value;
742 reg_value = REG_READ(LCD_DISP_I8080_CONFIG_ADDR);
743 reg_value &= ~(LCD_DISP_I8080_CONFIG_I8080_1MS_COUNT_MASK << LCD_DISP_I8080_CONFIG_I8080_1MS_COUNT_POS);
744 reg_value |= ((value & LCD_DISP_I8080_CONFIG_I8080_1MS_COUNT_MASK) << LCD_DISP_I8080_CONFIG_I8080_1MS_COUNT_POS);
745 REG_WRITE(LCD_DISP_I8080_CONFIG_ADDR,reg_value);
746 }
747
748 /* REG_0x05 */
749 #define LCD_DISP_I8080_CMD_FIFO_ADDR (LCD_DISP_LL_REG_BASE + 0x5*4) //REG ADDR :0x48060014
750 #define LCD_DISP_I8080_CMD_FIFO_I8080_CMD_FIFO_POS (0)
751 #define LCD_DISP_I8080_CMD_FIFO_I8080_CMD_FIFO_MASK (0xFFFF)
752
753 #define LCD_DISP_I8080_CMD_FIFO_RESERVED_POS (16)
754 #define LCD_DISP_I8080_CMD_FIFO_RESERVED_MASK (0xFFFF)
755
lcd_disp_ll_set_i8080_cmd_fifo_value(uint32_t value)756 static inline void lcd_disp_ll_set_i8080_cmd_fifo_value(uint32_t value)
757 {
758 REG_WRITE(LCD_DISP_I8080_CMD_FIFO_ADDR,value);
759 }
760
761 /* REG_0x05:i8080_cmd_fifo->i8080_cmd_fifo:0x5[15: 0],i8080 command fifo,0x0,w*/
lcd_disp_ll_set_i8080_cmd_fifo_i8080_cmd_fifo(uint32_t value)762 static inline void lcd_disp_ll_set_i8080_cmd_fifo_i8080_cmd_fifo(uint32_t value)
763 {
764 uint32_t reg_value;
765 reg_value = REG_READ(LCD_DISP_I8080_CMD_FIFO_ADDR);
766 reg_value &= ~(LCD_DISP_I8080_CMD_FIFO_I8080_CMD_FIFO_MASK << LCD_DISP_I8080_CMD_FIFO_I8080_CMD_FIFO_POS);
767 reg_value |= ((value & LCD_DISP_I8080_CMD_FIFO_I8080_CMD_FIFO_MASK) << LCD_DISP_I8080_CMD_FIFO_I8080_CMD_FIFO_POS);
768 REG_WRITE(LCD_DISP_I8080_CMD_FIFO_ADDR,reg_value);
769 }
770
771 /* REG_0x06 */
772 #define LCD_DISP_I8080_DAT_FIFO_ADDR (LCD_DISP_LL_REG_BASE + 0x6*4) //REG ADDR :0x48060018
773 #define LCD_DISP_I8080_DAT_FIFO_I8080_DAT_FIFO_POS (0)
774 #define LCD_DISP_I8080_DAT_FIFO_I8080_DAT_FIFO_MASK (0xFFFF)
775
776 #define LCD_DISP_I8080_DAT_FIFO_RESERVED_POS (16)
777 #define LCD_DISP_I8080_DAT_FIFO_RESERVED_MASK (0xFFFF)
778
lcd_disp_ll_set_i8080_dat_fifo_value(uint32_t value)779 static inline void lcd_disp_ll_set_i8080_dat_fifo_value(uint32_t value)
780 {
781 REG_WRITE(LCD_DISP_I8080_DAT_FIFO_ADDR,value);
782 }
783
784 /* REG_0x06:i8080_dat_fifo->i8080_dat_fifo:0x6[15 :0],i8080 data fifo,0x0,w*/
lcd_disp_ll_set_i8080_dat_fifo_i8080_dat_fifo(uint32_t value)785 static inline void lcd_disp_ll_set_i8080_dat_fifo_i8080_dat_fifo(uint32_t value)
786 {
787 uint32_t reg_value;
788 reg_value = REG_READ(LCD_DISP_I8080_DAT_FIFO_ADDR);
789 reg_value &= ~(LCD_DISP_I8080_DAT_FIFO_I8080_DAT_FIFO_MASK << LCD_DISP_I8080_DAT_FIFO_I8080_DAT_FIFO_POS);
790 reg_value |= ((value & LCD_DISP_I8080_DAT_FIFO_I8080_DAT_FIFO_MASK) << LCD_DISP_I8080_DAT_FIFO_I8080_DAT_FIFO_POS);
791 REG_WRITE(LCD_DISP_I8080_DAT_FIFO_ADDR,reg_value);
792 }
793
794 /* REG_0x07 */
795 #define LCD_DISP_I8080THRD_ADDR (LCD_DISP_LL_REG_BASE + 0x7*4) //REG ADDR :0x4806001c
796 #define LCD_DISP_I8080THRD_DAT_WR_THRD_POS (0)
797 #define LCD_DISP_I8080THRD_DAT_WR_THRD_MASK (0xFF)
798
799 #define LCD_DISP_I8080THRD_CMD_WR_THRD_POS (8)
800 #define LCD_DISP_I8080THRD_CMD_WR_THRD_MASK (0xFF)
801
802 #define LCD_DISP_I8080THRD_DAT_RD_THRD_POS (16)
803 #define LCD_DISP_I8080THRD_DAT_RD_THRD_MASK (0xFF)
804
805 #define LCD_DISP_I8080THRD_CMD_RD_THRD_POS (24)
806 #define LCD_DISP_I8080THRD_CMD_RD_THRD_MASK (0xFF)
807
lcd_disp_ll_get_i8080thrd_value(void)808 static inline uint32_t lcd_disp_ll_get_i8080thrd_value(void)
809 {
810 return REG_READ(LCD_DISP_I8080THRD_ADDR);
811 }
812
lcd_disp_ll_set_i8080thrd_value(uint32_t value)813 static inline void lcd_disp_ll_set_i8080thrd_value(uint32_t value)
814 {
815 REG_WRITE(LCD_DISP_I8080THRD_ADDR,value);
816 }
817
818 /* REG_0x07:i8080thrd->dat_wr_thrd:0x7[ 7 :0],i8080 rgb fifo wr thrd,0x0,r/w*/
lcd_disp_ll_get_i8080thrd_dat_wr_thrd(void)819 static inline uint32_t lcd_disp_ll_get_i8080thrd_dat_wr_thrd(void)
820 {
821 uint32_t reg_value;
822 reg_value = REG_READ(LCD_DISP_I8080THRD_ADDR);
823 reg_value = ((reg_value >> LCD_DISP_I8080THRD_DAT_WR_THRD_POS) & LCD_DISP_I8080THRD_DAT_WR_THRD_MASK);
824 return reg_value;
825 }
826
lcd_disp_ll_set_i8080thrd_dat_wr_thrd(uint32_t value)827 static inline void lcd_disp_ll_set_i8080thrd_dat_wr_thrd(uint32_t value)
828 {
829 uint32_t reg_value;
830 reg_value = REG_READ(LCD_DISP_I8080THRD_ADDR);
831 reg_value &= ~(LCD_DISP_I8080THRD_DAT_WR_THRD_MASK << LCD_DISP_I8080THRD_DAT_WR_THRD_POS);
832 reg_value |= ((value & LCD_DISP_I8080THRD_DAT_WR_THRD_MASK) << LCD_DISP_I8080THRD_DAT_WR_THRD_POS);
833 REG_WRITE(LCD_DISP_I8080THRD_ADDR,reg_value);
834 }
835
836 /* REG_0x07:i8080thrd->cmd_wr_thrd:0x7[15: 8],i8080 cmd fifo wr thrd,0x0,r/w*/
lcd_disp_ll_get_i8080thrd_cmd_wr_thrd(void)837 static inline uint32_t lcd_disp_ll_get_i8080thrd_cmd_wr_thrd(void)
838 {
839 uint32_t reg_value;
840 reg_value = REG_READ(LCD_DISP_I8080THRD_ADDR);
841 reg_value = ((reg_value >> LCD_DISP_I8080THRD_CMD_WR_THRD_POS) & LCD_DISP_I8080THRD_CMD_WR_THRD_MASK);
842 return reg_value;
843 }
844
lcd_disp_ll_set_i8080thrd_cmd_wr_thrd(uint32_t value)845 static inline void lcd_disp_ll_set_i8080thrd_cmd_wr_thrd(uint32_t value)
846 {
847 uint32_t reg_value;
848 reg_value = REG_READ(LCD_DISP_I8080THRD_ADDR);
849 reg_value &= ~(LCD_DISP_I8080THRD_CMD_WR_THRD_MASK << LCD_DISP_I8080THRD_CMD_WR_THRD_POS);
850 reg_value |= ((value & LCD_DISP_I8080THRD_CMD_WR_THRD_MASK) << LCD_DISP_I8080THRD_CMD_WR_THRD_POS);
851 REG_WRITE(LCD_DISP_I8080THRD_ADDR,reg_value);
852 }
853
854 /* REG_0x07:i8080thrd->dat_rd_thrd:0x7[23:16],i8080 dat fifo rd thrd,0x0,r/w*/
lcd_disp_ll_get_i8080thrd_dat_rd_thrd(void)855 static inline uint32_t lcd_disp_ll_get_i8080thrd_dat_rd_thrd(void)
856 {
857 uint32_t reg_value;
858 reg_value = REG_READ(LCD_DISP_I8080THRD_ADDR);
859 reg_value = ((reg_value >> LCD_DISP_I8080THRD_DAT_RD_THRD_POS) & LCD_DISP_I8080THRD_DAT_RD_THRD_MASK);
860 return reg_value;
861 }
862
lcd_disp_ll_set_i8080thrd_dat_rd_thrd(uint32_t value)863 static inline void lcd_disp_ll_set_i8080thrd_dat_rd_thrd(uint32_t value)
864 {
865 uint32_t reg_value;
866 reg_value = REG_READ(LCD_DISP_I8080THRD_ADDR);
867 reg_value &= ~(LCD_DISP_I8080THRD_DAT_RD_THRD_MASK << LCD_DISP_I8080THRD_DAT_RD_THRD_POS);
868 reg_value |= ((value & LCD_DISP_I8080THRD_DAT_RD_THRD_MASK) << LCD_DISP_I8080THRD_DAT_RD_THRD_POS);
869 REG_WRITE(LCD_DISP_I8080THRD_ADDR,reg_value);
870 }
871
872 /* REG_0x07:i8080thrd->cmd_rd_thrd:0x7[31:24],i8080 cmd fifo rd thrd,0x0,r/w*/
lcd_disp_ll_get_i8080thrd_cmd_rd_thrd(void)873 static inline uint32_t lcd_disp_ll_get_i8080thrd_cmd_rd_thrd(void)
874 {
875 uint32_t reg_value;
876 reg_value = REG_READ(LCD_DISP_I8080THRD_ADDR);
877 reg_value = ((reg_value >> LCD_DISP_I8080THRD_CMD_RD_THRD_POS) & LCD_DISP_I8080THRD_CMD_RD_THRD_MASK);
878 return reg_value;
879 }
880
lcd_disp_ll_set_i8080thrd_cmd_rd_thrd(uint32_t value)881 static inline void lcd_disp_ll_set_i8080thrd_cmd_rd_thrd(uint32_t value)
882 {
883 uint32_t reg_value;
884 reg_value = REG_READ(LCD_DISP_I8080THRD_ADDR);
885 reg_value &= ~(LCD_DISP_I8080THRD_CMD_RD_THRD_MASK << LCD_DISP_I8080THRD_CMD_RD_THRD_POS);
886 reg_value |= ((value & LCD_DISP_I8080THRD_CMD_RD_THRD_MASK) << LCD_DISP_I8080THRD_CMD_RD_THRD_POS);
887 REG_WRITE(LCD_DISP_I8080THRD_ADDR,reg_value);
888 }
889
890 #ifdef __cplusplus
891 }
892 #endif
893