1 /* 2 * Allwinner SoCs display driver. 3 * 4 * Copyright (C) 2016 Allwinner. 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11 #ifndef _DISP_INCLUDE_H_ 12 #define _DISP_INCLUDE_H_ 13 14 #define __LINUX_PLAT__ 15 /* #define __UBOOT_PLAT__ */ 16 17 #if defined(__LINUX_PLAT__) 18 #include <linux/module.h> 19 #include <linux/kernel.h> 20 #include <linux/mm.h> 21 #include <linux/uaccess.h> 22 /*#include <asm/memory.h>*/ 23 #include <asm/unistd.h> 24 #include "linux/semaphore.h" 25 #include "asm-generic/int-ll64.h" 26 #include <asm/div64.h> 27 #include <asm/barrier.h> 28 #include <sunxi-sid.h> 29 #include <linux/vmalloc.h> 30 #include <linux/fs.h> 31 #include <linux/dma-mapping.h> 32 #include <linux/fb.h> 33 #include <linux/sched.h> /* wake_up_process() */ 34 #include <linux/kthread.h> /* kthread_create()??kthread_run() */ 35 #include <linux/err.h> /* IS_ERR()??PTR_ERR() */ 36 #include <linux/delay.h> 37 #include <linux/platform_device.h> 38 #include <linux/errno.h> 39 #include <linux/slab.h> 40 #include <linux/delay.h> 41 #include <linux/init.h> 42 #include <linux/dma-mapping.h> 43 #include <linux/interrupt.h> 44 #include <linux/platform_device.h> 45 #include <linux/clk.h> 46 #include <linux/reset.h> 47 #include <linux/cdev.h> 48 #include <linux/types.h> 49 #include <linux/timer.h> 50 #include <linux/gpio.h> 51 #include <linux/regulator/consumer.h> 52 #include <linux/pwm.h> 53 #include <linux/of_irq.h> 54 #include <linux/of_address.h> 55 #include <linux/of_iommu.h> 56 #include <linux/of_device.h> 57 #include <linux/of_platform.h> 58 #include <linux/of_gpio.h> 59 #include <linux/compat.h> 60 #include <linux/dma-buf.h> 61 #include <linux/dma-heap.h> 62 #include <linux/dma-mapping.h> 63 #include <linux/clk-provider.h> 64 65 #include <video/sunxi_display2.h> 66 #include <video/sunxi_metadata.h> 67 #include "../disp_sys_intf.h" 68 #include "disp_features.h" 69 70 /* #include "disp_format_convert.h" */ 71 #define DISP2_DEBUG_LEVEL 0 72 73 #if DISP2_DEBUG_LEVEL == 1 74 #define __inf(msg...) do { \ 75 pr_warn("[DISP] %s,line:%d:", __func__, __LINE__); \ 76 pr_warn(msg); \ 77 } while (0) 78 #define __msg(msg...) do { \ 79 pr_warn("[DISP] %s,line:%d:", __func__, __LINE__); \ 80 pr_warn(msg); \ 81 } while (0) 82 #define __here__ 83 #define __debug(msg...) 84 #elif DISP2_DEBUG_LEVEL == 2 85 #define __inf(msg...) do { \ 86 pr_warn("[DISP] %s,line:%d:", __func__, __LINE__); \ 87 pr_warn(msg); \ 88 } while (0) 89 #define __here__ do { \ 90 pr_warn("[DISP] %s,line:%d\n", __func__, __LINE__);\ 91 } while (0) 92 #define __debug(msg...) do { \ 93 pr_warn("[DISP] %s,line:%d:", __func__, __LINE__); \ 94 pr_warn(msg); \ 95 } while (0) 96 #else 97 #define __inf(msg...) 98 #define __msg(msg...) 99 #define __here__ 100 #define __debug(msg...) 101 #endif 102 103 #define __wrn(msg...) do { \ 104 pr_warn("[DISP] %s,line:%d:", __func__, __LINE__); \ 105 pr_warn(msg); \ 106 } while (0) 107 108 #endif /* end of define __LINUX_PLAT__ */ 109 110 #ifdef __UBOOT_PLAT__ 111 #include <common.h> 112 #include <malloc.h> 113 #include <sunxi_display2.h> 114 #include <sys_config.h> 115 #include <asm/arch/intc.h> 116 #include <pwm.h> 117 #include <asm/arch/timer.h> 118 #include <asm/arch/platform.h> 119 #include <linux/list.h> 120 #include <asm/memory.h> 121 #include <div64.h> 122 #include <fdt_support.h> 123 #include <power/sunxi/pmu.h> 124 #include "asm/io.h" 125 #include "../disp_sys_intf.h" 126 127 #define OSAL_PRINTF 128 #define __inf(msg...) 129 #define __msg(msg...) 130 #define __wrn(msg...) printf(msg) 131 #define __here 132 #define __debug 133 134 #define false 0 135 #define true 1 136 #endif 137 138 #if defined(__LINUX_PLAT__) 139 #define DE_INF __inf 140 #define DE_MSG __msg 141 #define DE_WRN __wrn 142 #define DE_DBG __debug 143 #define DISP_IRQ_RETURN IRQ_HANDLED 144 #else 145 #define DE_INF(msg...) 146 #define DE_MSG __msg 147 #define DE_WRN __wrn 148 #define DE_DBG __debug 149 #ifndef DISP_IRQ_RETURN 150 #define DISP_IRQ_RETURN DIS_SUCCESS 151 #endif 152 #endif 153 154 #define DEFAULT_PRINT_LEVLE 0 155 #if defined(CONFIG_FPGA_V4_PLATFORM) \ 156 || defined(CONFIG_FPGA_V7_PLATFORM) \ 157 || defined(CONFIG_A67_FPGA) 158 #define __FPGA_DEBUG__ 159 #endif 160 161 #define SETMASK(width, shift) ((width?((-1U) >> (32-width)):0) << (shift)) 162 #define CLRMASK(width, shift) (~(SETMASK(width, shift))) 163 #define GET_BITS(shift, width, reg) \ 164 (((reg) & SETMASK(width, shift)) >> (shift)) 165 #define SET_BITS(shift, width, reg, val) \ 166 (((reg) & CLRMASK(width, shift)) | (val << (shift))) 167 168 #define DISPALIGN(value, align) ((align == 0) ? \ 169 value : \ 170 (((value) + ((align) - 1)) & ~((align) - 1))) 171 172 #ifndef abs 173 #define abs(x) (((x)&0x80000000) ? (0-(x)):(x)) 174 #endif 175 176 #define LCD_GAMMA_TABLE_SIZE (256 * sizeof(unsigned int)) 177 178 #define ONE_SEC 1000000000ull 179 struct panel_extend_para { 180 unsigned int lcd_gamma_en; 181 unsigned int lcd_gamma_tbl[256]; 182 unsigned int lcd_cmap_en; 183 unsigned int lcd_cmap_tbl[2][3][4]; 184 unsigned int lcd_bright_curve_tbl[256]; 185 }; 186 187 enum disp_return_value { 188 DIS_SUCCESS = 0, 189 DIS_FAIL = -1, 190 DIS_PARA_FAILED = -2, 191 DIS_PRIO_ERROR = -3, 192 DIS_OBJ_NOT_INITED = -4, 193 DIS_NOT_SUPPORT = -5, 194 DIS_NO_RES = -6, 195 DIS_OBJ_COLLISION = -7, 196 DIS_DEV_NOT_INITED = -8, 197 DIS_DEV_SRAM_COLLISION = -9, 198 DIS_TASK_ERROR = -10, 199 DIS_PRIO_COLLSION = -11 200 }; 201 202 /*basic data information definition*/ 203 enum disp_layer_feat { 204 DISP_LAYER_FEAT_GLOBAL_ALPHA = 1 << 0, 205 DISP_LAYER_FEAT_PIXEL_ALPHA = 1 << 1, 206 DISP_LAYER_FEAT_GLOBAL_PIXEL_ALPHA = 1 << 2, 207 DISP_LAYER_FEAT_PRE_MULT_ALPHA = 1 << 3, 208 DISP_LAYER_FEAT_COLOR_KEY = 1 << 4, 209 DISP_LAYER_FEAT_ZORDER = 1 << 5, 210 DISP_LAYER_FEAT_POS = 1 << 6, 211 DISP_LAYER_FEAT_3D = 1 << 7, 212 DISP_LAYER_FEAT_SCALE = 1 << 8, 213 DISP_LAYER_FEAT_DE_INTERLACE = 1 << 9, 214 DISP_LAYER_FEAT_COLOR_ENHANCE = 1 << 10, 215 DISP_LAYER_FEAT_DETAIL_ENHANCE = 1 << 11, 216 }; 217 218 enum disp_pixel_type { 219 DISP_PIXEL_TYPE_RGB = 0x0, 220 DISP_PIXEL_TYPE_YUV = 0x1, 221 }; 222 223 enum disp_layer_dirty_flags { 224 LAYER_ATTR_DIRTY = 0x00000001, 225 LAYER_VI_FC_DIRTY = 0x00000002, 226 LAYER_HADDR_DIRTY = 0x00000004, 227 LAYER_SIZE_DIRTY = 0x00000008, 228 BLEND_ENABLE_DIRTY = 0x00000010, 229 BLEND_ATTR_DIRTY = 0x00000020, 230 BLEND_CTL_DIRTY = 0x00000040, 231 BLEND_OUT_DIRTY = 0x00000080, 232 LAYER_ATW_DIRTY = 0x00000100, 233 LAYER_HDR_DIRTY = 0x00000200, 234 LAYER_ALL_DIRTY = 0x000003ff, 235 }; 236 237 enum disp_manager_dirty_flags { 238 MANAGER_ENABLE_DIRTY = 0x00000001, 239 MANAGER_CK_DIRTY = 0x00000002, 240 MANAGER_BACK_COLOR_DIRTY = 0x00000004, 241 MANAGER_SIZE_DIRTY = 0x00000008, 242 MANAGER_COLOR_RANGE_DIRTY = 0x00000010, 243 MANAGER_COLOR_SPACE_DIRTY = 0x00000020, 244 MANAGER_BLANK_DIRTY = 0x00000040, 245 MANAGER_KSC_DIRTY = 0x00000080, 246 MANAGER_PALETTE_DIRTY = 0x00000100, 247 MANAGER_ALL_DIRTY = 0x00000fff, 248 }; 249 250 /* disp_atw_info_inner - asynchronous time wrap infomation 251 * 252 * @used: indicate if the atw funtion is used 253 * @mode: atw mode 254 * @b_row: the row number of the micro block 255 * @b_col: the column number of the micro block 256 * @cof_fd: dma_buf fd for the buffer contaied coefficient for atw 257 */ 258 struct disp_atw_info_inner { 259 bool used; 260 enum disp_atw_mode mode; 261 unsigned int b_row; 262 unsigned int b_col; 263 int cof_fd; 264 unsigned long long cof_addr; 265 }; 266 267 /* disp_fb_info_inner - image buffer info on the inside 268 * 269 * @addr: buffer address for each plane 270 * @size: size<width,height> for each buffer, unit:pixels 271 * @align: align for each buffer, unit:bytes 272 * @format: pixel format 273 * @color_space: color space 274 * @trd_right_addr: the right-eye buffer address for each plane, 275 * valid when frame-packing 3d buffer input 276 * @pre_multiply: indicate the pixel use premultiplied alpha 277 * @crop: crop rectangle for buffer to be display 278 * @flag: indicate stereo/non-stereo buffer 279 * @scan: indicate interleave/progressive scan type, and the scan order 280 * @metadata_buf: the phy_address to the buffer contained metadata for fbc/hdr 281 * @metadata_size: the size of metadata buffer, unit:bytes 282 * @metadata_flag: the flag to indicate the type of metadata buffer 283 * 0 : no metadata 284 * 1 << 0: hdr static metadata 285 * 1 << 1: hdr dynamic metadata 286 * 1 << 4: frame buffer compress(fbc) metadata 287 * x : all type could be "or" together 288 */ 289 struct disp_fb_info_inner { 290 int fd; 291 struct dma_buf *dmabuf; 292 unsigned long long addr[3]; 293 struct disp_rectsz size[3]; 294 unsigned int align[3]; 295 enum disp_pixel_format format; 296 enum disp_color_space color_space; 297 int trd_right_fd; 298 unsigned int trd_right_addr[3]; 299 bool pre_multiply; 300 struct disp_rect64 crop; 301 enum disp_buffer_flags flags; 302 enum disp_scan_flags scan; 303 enum disp_eotf eotf; 304 int depth; 305 unsigned int fbd_en; 306 unsigned int lbc_en; 307 int metadata_fd; 308 unsigned long long metadata_buf; 309 unsigned int metadata_size; 310 unsigned int metadata_flag; 311 struct disp_lbc_info lbc_info; 312 struct dma_buf *metadata_dmabuf; 313 struct sunxi_metadata *p_metadata; 314 struct afbc_header *p_afbc_header; 315 }; 316 317 /** 318 * disp_snr_info 319 */ 320 struct disp_snr_info_inner { 321 unsigned char en; 322 unsigned char demo_en; 323 struct disp_rect demo_win; 324 unsigned char y_strength; 325 unsigned char u_strength; 326 unsigned char v_strength; 327 unsigned char th_ver_line; 328 unsigned char th_hor_line; 329 }; 330 331 /* disp_layer_info_inner - layer info on the inside 332 * 333 * @mode: buffer/clolor mode, when in color mode, the layer is widthout buffer 334 * @zorder: the zorder of layer, 0~max-layer-number 335 * @alpha_mode: 336 * 0: pixel alpha; 337 * 1: global alpha 338 * 2: mixed alpha, compositing width pixel alpha before global alpha 339 * @alpha_value: global alpha value, valid when alpha_mode is not pixel alpha 340 * @screen_win: the rectangle on the screen for fb to be display 341 * @b_trd_out: indicate if 3d display output 342 * @out_trd_mode: 3d output mode, valid when b_trd_out is true 343 * @color: the color value to be display, valid when layer is in color mode 344 * @fb: the framebuffer info related width the layer, valid when in buffer mode 345 * @id: frame id, the user could get the frame-id display currently by 346 * DISP_LAYER_GET_FRAME_ID ioctl 347 * @atw: asynchronous time wrap information 348 */ 349 struct disp_layer_info_inner { 350 enum disp_layer_mode mode; 351 unsigned char zorder; 352 unsigned char alpha_mode; 353 unsigned char alpha_value; 354 struct disp_rect screen_win; 355 bool b_trd_out; 356 enum disp_3d_out_mode out_trd_mode; 357 union { 358 unsigned int color; 359 struct disp_fb_info_inner fb; 360 }; 361 362 unsigned int id; 363 struct disp_atw_info_inner atw; 364 #if defined(DE_VERSION_V33X) 365 int transform; 366 struct disp_snr_info_inner snr; 367 #endif 368 }; 369 370 /* disp_layer_config_inner - layer config on the inside 371 * 372 * @info: layer info 373 * @enable: indicate to enable/disable the layer 374 * @channel: the channel index of the layer, 0~max-channel-number 375 * @layer_id: the layer index of the layer widthin it's channel 376 */ 377 struct disp_layer_config_inner { 378 struct disp_layer_info_inner info; 379 bool enable; 380 unsigned int channel; 381 unsigned int layer_id; 382 }; 383 384 /* disp_layer_config_ops - operations for layer config 385 * 386 * @vmap:vmap a block contigous phys memory into virtual space 387 * @vunmap: release virtual mapping obtained by vmap() 388 */ 389 struct disp_layer_config_ops { 390 void *(*vmap)(unsigned long phys_addr, unsigned long size); 391 void (*vunmap)(const void *vaddr); 392 }; 393 struct disp_layer_config_data { 394 struct disp_layer_config_inner config; 395 enum disp_layer_dirty_flags flag; 396 struct disp_layer_config_ops ops; 397 }; 398 399 struct disp_manager_info { 400 struct disp_color back_color; 401 struct disp_colorkey ck; 402 struct disp_rect size; 403 enum disp_csc_type cs; 404 enum disp_color_space color_space; 405 u32 color_range; 406 u32 interlace; 407 bool enable; 408 /* index of device */ 409 u32 disp_device; 410 /* indicate the index of timing controller */ 411 u32 hwdev_index; 412 /* true: disable all layer; false: enable layer if requested */ 413 bool blank; 414 u32 de_freq; 415 enum disp_eotf eotf; /* sdr/hdr10/hlg */ 416 enum disp_data_bits data_bits; 417 u32 device_fps; 418 struct disp_ksc_info ksc; 419 struct disp_palette_config palette; 420 #ifdef CONFIG_AW_DRM 421 enum disp_output_type conn_type; 422 #endif 423 }; 424 425 struct disp_manager_data { 426 struct disp_manager_info config; 427 enum disp_manager_dirty_flags flag; 428 }; 429 430 struct disp_clk_info { 431 u32 clk; 432 u32 clk_div; 433 u32 h_clk; 434 u32 clk_src; 435 u32 clk_div2; 436 437 u32 clk_p; 438 u32 clk_div_p; 439 u32 h_clk_p; 440 u32 clk_src_p; 441 442 u32 ahb_clk; 443 u32 h_ahb_clk; 444 u32 dram_clk; 445 u32 h_dram_clk; 446 447 bool enabled; 448 }; 449 450 struct disp_enhance_info { 451 /* basic adjust */ 452 /* 453 * enhance parameters : 0~10, bigger value, stronger enhance level 454 * mode : combination of enhance_mode and dev_type 455 * enhance_mode : bit31~bit16 of mode 456 * : 0-disable; 1-enable; 2-demo(enable half window) 457 * dev_type : bit15~bit0 of mode 458 * : 0-lcd; 1-tv(hdmi, cvbs, vga, ypbpr) 459 */ 460 u32 bright; 461 u32 contrast; 462 u32 saturation; 463 u32 hue; 464 u32 edge; 465 u32 detail; 466 u32 denoise; 467 u32 mode; 468 /* ehnance */ 469 u32 sharp; /* 0-off; 1~3-on. */ 470 u32 auto_contrast; /* 0-off; 1~3-on. */ 471 u32 auto_color; /* 0-off; 1-on. */ 472 u32 fancycolor_red; /* 0-Off; 1-2-on. */ 473 u32 fancycolor_green; /* 0-Off; 1-2-on. */ 474 u32 fancycolor_blue; /* 0-Off; 1-2-on. */ 475 struct disp_rect window; 476 u32 enable; 477 struct disp_rect size; 478 u32 demo_enable; /* 1: enable demo mode */ 479 }; 480 481 enum disp_enhance_dirty_flags { 482 ENH_NONE_DIRTY = 0x0, 483 ENH_ENABLE_DIRTY = 0x1 << 0, /* enable dirty */ 484 ENH_SIZE_DIRTY = 0x1 << 1, /* size dirty */ 485 ENH_FORMAT_DIRTY = 0x1 << 2, /* overlay format dirty */ 486 ENH_BYPASS_DIRTY = 0x1 << 3, /* bypass dirty */ 487 ENH_INIT_DIRTY = 0x1 << 8, /* initial parameters dirty */ 488 ENH_MODE_DIRTY = 0X1 << 9, /* enhance mode dirty */ 489 ENH_BRIGHT_DIRTY = 0x1 << 10, /* brightness level dirty */ 490 ENH_CONTRAST_DIRTY = 0x1 << 11, /* contrast level dirty */ 491 ENH_EDGE_DIRTY = 0x1 << 12, /* edge level dirty */ 492 ENH_DETAIL_DIRTY = 0x1 << 13, /* detail level dirty */ 493 ENH_SAT_DIRTY = 0x1 << 14, /* saturation level dirty */ 494 ENH_DNS_DIRTY = 0x1 << 15, /* de-noise level dirty */ 495 ENH_USER_DIRTY = 0xff00, /* dirty by user */ 496 ENH_ALL_DIRTY = 0xffff /* all dirty */ 497 498 }; 499 500 struct disp_enhance_config { 501 struct disp_enhance_info info; 502 enum disp_enhance_dirty_flags flags; 503 }; 504 505 enum disp_smbl_dirty_flags { 506 SMBL_DIRTY_NONE = 0x00000000, 507 SMBL_DIRTY_ENABLE = 0x00000001, 508 SMBL_DIRTY_WINDOW = 0x00000002, 509 SMBL_DIRTY_SIZE = 0x00000004, 510 SMBL_DIRTY_BL = 0x00000008, 511 SMBL_DIRTY_ALL = 0x0000000F, 512 }; 513 514 struct disp_smbl_info { 515 struct disp_rect window; 516 u32 enable; 517 struct disp_rect size; 518 u32 backlight; 519 u32 backlight_dimming; 520 enum disp_smbl_dirty_flags flags; 521 }; 522 523 struct disp_csc_config { 524 u32 in_fmt; 525 u32 in_mode; 526 u32 in_color_range; 527 u32 out_fmt; 528 u32 out_mode; 529 u32 out_color_range; 530 u32 brightness; 531 u32 contrast; 532 u32 saturation; 533 u32 hue; 534 u32 enhance_mode; 535 u32 color; 536 u32 in_eotf; 537 u32 out_eotf; 538 }; 539 540 enum { 541 DE_RGB = 0, 542 DE_YUV = 1, 543 }; 544 545 enum disp_capture_dirty_flags { 546 CAPTURE_DIRTY_ADDRESS = 0x00000001, 547 CAPTURE_DIRTY_WINDOW = 0x00000002, 548 CAPTURE_DIRTY_SIZE = 0x00000004, 549 CAPTURE_DIRTY_ALL = 0x00000007, 550 }; 551 /* disp_s_frame_inner - display simple frame buffer 552 * 553 * @format: pixel format of fb 554 * @size: size for each plane 555 * @crop: crop zone to be fill image data 556 * @fd: dma_buf fd 557 * @addr: buffer addr for each plane 558 */ 559 struct disp_s_frame_inner { 560 enum disp_pixel_format format; 561 struct disp_rectsz size[3]; 562 struct disp_rect crop; 563 unsigned long long addr[3]; 564 int fd; 565 }; 566 567 /* disp_capture_info_inner - display capture information 568 * 569 * @window: the rectange on the screen to be capture 570 * @out_frame: the framebuffer to be restore capture image data 571 */ 572 struct disp_capture_info_inner { 573 struct disp_rect window; 574 struct disp_s_frame_inner out_frame; 575 }; 576 /* disp_capture_config - configuration for capture function 577 * 578 * @in_frame: input frame information 579 * @out_frame: output framebuffer infomation 580 * @disp: indicate which disp channel to be capture 581 * @flags: caputre flags 582 */ 583 struct disp_capture_config { 584 struct disp_s_frame_inner in_frame; /* only format/size/crop valid */ 585 struct disp_s_frame_inner out_frame; 586 u32 disp; /* which disp channel to be capture */ 587 enum disp_capture_dirty_flags flags; 588 }; 589 590 enum disp_lcd_if { 591 LCD_IF_HV = 0, 592 LCD_IF_CPU = 1, 593 LCD_IF_LVDS = 3, 594 LCD_IF_DSI = 4, 595 LCD_IF_EDP = 5, 596 LCD_IF_EXT_DSI = 6, 597 LCD_IF_VDPO = 7, 598 }; 599 600 enum disp_lcd_hv_if { 601 LCD_HV_IF_PRGB_1CYC = 0, /* parallel hv */ 602 LCD_HV_IF_SRGB_3CYC = 8, /* serial hv */ 603 LCD_HV_IF_DRGB_4CYC = 10, /* Dummy RGB */ 604 LCD_HV_IF_RGBD_4CYC = 11, /* RGB Dummy */ 605 LCD_HV_IF_CCIR656_2CYC = 12, 606 }; 607 608 enum disp_lcd_hv_srgb_seq { 609 LCD_HV_SRGB_SEQ_RGB_RGB = 0, 610 LCD_HV_SRGB_SEQ_RGB_BRG = 1, 611 LCD_HV_SRGB_SEQ_RGB_GBR = 2, 612 LCD_HV_SRGB_SEQ_BRG_RGB = 4, 613 LCD_HV_SRGB_SEQ_BRG_BRG = 5, 614 LCD_HV_SRGB_SEQ_BRG_GBR = 6, 615 LCD_HV_SRGB_SEQ_GRB_RGB = 8, 616 LCD_HV_SRGB_SEQ_GRB_BRG = 9, 617 LCD_HV_SRGB_SEQ_GRB_GBR = 10, 618 }; 619 620 enum disp_lcd_hv_syuv_seq { 621 LCD_HV_SYUV_SEQ_YUYV = 0, 622 LCD_HV_SYUV_SEQ_YVYU = 1, 623 LCD_HV_SYUV_SEQ_UYUV = 2, 624 LCD_HV_SYUV_SEQ_VYUY = 3, 625 }; 626 627 enum disp_lcd_hv_syuv_fdly { 628 LCD_HV_SYUV_FDLY_0LINE = 0, 629 LCD_HV_SRGB_FDLY_2LINE = 1, /* ccir ntsc */ 630 LCD_HV_SRGB_FDLY_3LINE = 2, /* ccir pal */ 631 }; 632 633 enum disp_lcd_cpu_if { 634 LCD_CPU_IF_RGB666_18PIN = 0, 635 LCD_CPU_IF_RGB666_9PIN = 10, 636 LCD_CPU_IF_RGB666_6PIN = 12, 637 LCD_CPU_IF_RGB565_16PIN = 8, 638 LCD_CPU_IF_RGB565_8PIN = 14, 639 }; 640 641 enum disp_lcd_cpu_mode { 642 LCD_CPU_AUTO_MODE = 0, 643 LCD_CPU_TRIGGER_MODE = 1, 644 }; 645 646 enum disp_lcd_te { 647 LCD_TE_DISABLE = 0, 648 LCD_TE_RISING = 1, 649 LCD_TE_FALLING = 2, 650 }; 651 652 enum disp_lcd_lvds_if { 653 LCD_LVDS_IF_SINGLE_LINK = 0, 654 LCD_LVDS_IF_DUAL_LINK = 1, 655 LCD_LVDS_IF_DUAL_LINK_SAME_SRC = 2, 656 }; 657 658 enum disp_lcd_lvds_colordepth { 659 LCD_LVDS_8bit = 0, 660 LCD_LVDS_6bit = 1, 661 }; 662 663 enum disp_lcd_lvds_mode { 664 LCD_LVDS_MODE_NS = 0, 665 LCD_LVDS_MODE_JEIDA = 1, 666 }; 667 668 enum disp_lcd_dsi_if { 669 LCD_DSI_IF_VIDEO_MODE = 0, 670 LCD_DSI_IF_COMMAND_MODE = 1, 671 LCD_DSI_IF_BURST_MODE = 2, 672 }; 673 674 enum disp_lcd_dsi_lane { 675 LCD_DSI_1LANE = 1, 676 LCD_DSI_2LANE = 2, 677 LCD_DSI_3LANE = 3, 678 LCD_DSI_4LANE = 4, 679 }; 680 681 enum disp_lcd_dsi_format { 682 LCD_DSI_FORMAT_RGB888 = 0, 683 LCD_DSI_FORMAT_RGB666 = 1, 684 LCD_DSI_FORMAT_RGB666P = 2, 685 LCD_DSI_FORMAT_RGB565 = 3, 686 }; 687 688 enum disp_lcd_frm { 689 LCD_FRM_BYPASS = 0, 690 LCD_FRM_RGB666 = 1, 691 LCD_FRM_RGB565 = 2, 692 }; 693 694 enum disp_lcd_cmap_color { 695 LCD_CMAP_B0 = 0x0, 696 LCD_CMAP_G0 = 0x1, 697 LCD_CMAP_R0 = 0x2, 698 LCD_CMAP_B1 = 0x4, 699 LCD_CMAP_G1 = 0x5, 700 LCD_CMAP_R1 = 0x6, 701 LCD_CMAP_B2 = 0x8, 702 LCD_CMAP_G2 = 0x9, 703 LCD_CMAP_R2 = 0xa, 704 LCD_CMAP_B3 = 0xc, 705 LCD_CMAP_G3 = 0xd, 706 LCD_CMAP_R3 = 0xe, 707 }; 708 709 struct __disp_dsi_dphy_timing_t { 710 unsigned int lp_clk_div; 711 unsigned int hs_prepare; 712 unsigned int hs_trail; 713 unsigned int clk_prepare; 714 unsigned int clk_zero; 715 unsigned int clk_pre; 716 unsigned int clk_post; 717 unsigned int clk_trail; 718 unsigned int hs_dly_mode; 719 unsigned int hs_dly; 720 unsigned int lptx_ulps_exit; 721 unsigned int hstx_ana0; 722 unsigned int hstx_ana1; 723 }; 724 725 /** 726 * lcd tcon mode(dual tcon drive dual dsi) 727 */ 728 enum disp_lcd_tcon_mode { 729 DISP_TCON_NORMAL_MODE = 0, 730 DISP_TCON_MASTER_SYNC_AT_FIRST_TIME, 731 DISP_TCON_MASTER_SYNC_EVERY_FRAME, 732 DISP_TCON_SLAVE_MODE, 733 DISP_TCON_DUAL_DSI, 734 }; 735 736 enum disp_lcd_dsi_port { 737 DISP_LCD_DSI_SINGLE_PORT = 0, 738 DISP_LCD_DSI_DUAL_PORT, 739 }; 740 741 struct disp_lcd_esd_info { 742 /*1:reset all module include tcon; 0:reset panel only*/ 743 unsigned char level; 744 /*unit:frame*/ 745 unsigned short freq; 746 /*1:in disp isr; 0:in reflush work*/ 747 unsigned char esd_check_func_pos; 748 /*count*/ 749 unsigned int cnt; 750 /*reset count*/ 751 unsigned int rst_cnt; 752 }; 753 754 struct disp_panel_para { 755 enum disp_lcd_if lcd_if; 756 757 enum disp_lcd_hv_if lcd_hv_if; 758 enum disp_lcd_hv_srgb_seq lcd_hv_srgb_seq; 759 enum disp_lcd_hv_syuv_seq lcd_hv_syuv_seq; 760 enum disp_lcd_hv_syuv_fdly lcd_hv_syuv_fdly; 761 762 enum disp_lcd_lvds_if lcd_lvds_if; 763 enum disp_lcd_lvds_colordepth lcd_lvds_colordepth; 764 enum disp_lcd_lvds_mode lcd_lvds_mode; 765 unsigned int lcd_lvds_io_polarity; 766 unsigned int lcd_lvds_clk_polarity; 767 768 enum disp_lcd_cpu_if lcd_cpu_if; 769 enum disp_lcd_te lcd_cpu_te; 770 enum disp_lcd_dsi_port lcd_dsi_port_num; 771 enum disp_lcd_tcon_mode lcd_tcon_mode; 772 unsigned int lcd_slave_stop_pos; 773 unsigned int lcd_sync_pixel_num; 774 unsigned int lcd_sync_line_num; 775 unsigned int lcd_slave_tcon_num; 776 enum disp_lcd_cpu_mode lcd_cpu_mode; 777 778 enum disp_lcd_dsi_if lcd_dsi_if; 779 enum disp_lcd_dsi_lane lcd_dsi_lane; 780 enum disp_lcd_dsi_format lcd_dsi_format; 781 unsigned int lcd_dsi_eotp; 782 unsigned int lcd_dsi_vc; 783 enum disp_lcd_te lcd_dsi_te; 784 785 unsigned int lcd_tcon_en_odd_even; 786 787 unsigned int lcd_dsi_dphy_timing_en; 788 struct __disp_dsi_dphy_timing_t *lcd_dsi_dphy_timing_p; 789 790 unsigned int lcd_fsync_en; 791 unsigned int lcd_fsync_act_time; 792 unsigned int lcd_fsync_dis_time; 793 unsigned int lcd_fsync_pol; 794 795 unsigned int lcd_dclk_freq; 796 unsigned int lcd_x; /* horizontal resolution */ 797 unsigned int lcd_y; /* vertical resolution */ 798 unsigned int lcd_width; /* width of lcd in mm */ 799 unsigned int lcd_height; /* height of lcd in mm */ 800 unsigned int lcd_xtal_freq; 801 802 unsigned int lcd_pwm_used; 803 unsigned int lcd_pwm_ch; 804 unsigned int lcd_pwm_freq; 805 unsigned int lcd_pwm_pol; 806 807 unsigned int lcd_rb_swap; 808 unsigned int lcd_rgb_endian; 809 810 unsigned int lcd_vt; 811 unsigned int lcd_ht; 812 unsigned int lcd_vbp; 813 unsigned int lcd_hbp; 814 unsigned int lcd_vspw; 815 unsigned int lcd_hspw; 816 817 unsigned int lcd_interlace; 818 unsigned int lcd_hv_clk_phase; 819 unsigned int lcd_hv_sync_polarity; 820 821 unsigned int lcd_frm; 822 unsigned int lcd_gamma_en; 823 unsigned int lcd_cmap_en; 824 unsigned int lcd_bright_curve_en; 825 826 char lcd_size[8]; /* e.g. 7.9, 9.7 */ 827 char lcd_model_name[32]; 828 char lcd_driver_name[32]; 829 830 unsigned int tcon_index; /* not need to config for user */ 831 unsigned int lcd_fresh_mode; /* not need to config for user */ 832 unsigned int lcd_dclk_freq_original;/* not need to config for user */ 833 unsigned int ccir_clk_div;/*not need to config for user*/ 834 unsigned int input_csc;/*not need to config for user*/ 835 unsigned int lcd_gsensor_detect; 836 unsigned int lcd_hv_data_polarity; 837 838 }; 839 840 enum disp_mod_id { 841 DISP_MOD_DE = 0, 842 #if defined(CONFIG_INDEPENDENT_DE) 843 DISP_MOD_DE1, 844 #endif 845 DISP_MOD_DEVICE, /* for timing controller common module */ 846 #if defined(CONFIG_INDEPENDENT_DE) 847 DISP_MOD_DEVICE1, 848 #endif 849 DISP_MOD_LCD0, 850 DISP_MOD_LCD1, 851 DISP_MOD_LCD2, 852 DISP_MOD_LCD3, 853 DISP_MOD_DSI0, 854 DISP_MOD_DSI1, 855 DISP_MOD_DSI2, 856 DISP_MOD_DSI3, 857 DISP_MOD_HDMI, 858 DISP_MOD_LVDS, 859 DISP_MOD_LVDS1, 860 DISP_MOD_EINK, 861 DISP_MOD_EDMA, 862 DISP_MOD_VDPO, 863 #if defined(CONFIG_INDEPENDENT_DE) 864 DISP_MOD_DPSS0, 865 DISP_MOD_DPSS1, 866 #endif 867 DISP_MOD_NUM, 868 }; 869 870 typedef enum { 871 DISP_NOT_UPDATE = 0, 872 DISP_NORMAL_UPDATE = 1, 873 DISP_SMOOTH_UPDATE = 2, 874 } disp_config_update_t; 875 876 877 struct disp_bootloader_info { 878 int sync; /* 1: sync width bootloader */ 879 int disp; /* output disp at bootloader period */ 880 int type; /* output type at bootloader period */ 881 int mode; /* output mode at bootloader period */ 882 int format;/* YUV or RGB */ 883 int bits; /* color deep */ 884 int eotf; 885 int cs; /* color space */ 886 enum disp_dvi_hdmi dvi_hdmi; 887 enum disp_color_range range; 888 enum disp_scan_info scan; 889 unsigned int aspect_ratio; 890 891 }; 892 893 #define DEBUG_TIME_SIZE 100 894 struct disp_health_info { 895 unsigned long sync_time[DEBUG_TIME_SIZE]; /* for_debug */ 896 unsigned int sync_time_index; /* for_debug */ 897 unsigned int skip_cnt; 898 unsigned int skip_cnt_timeout; 899 unsigned int error_cnt; /* under flow .ect */ 900 unsigned long long irq_cnt; 901 unsigned int vsync_cnt; 902 unsigned int vsync_skip_cnt; 903 }; 904 905 struct disp_bsp_init_para { 906 uintptr_t reg_base[DISP_MOD_NUM]; 907 u32 irq_no[DISP_MOD_NUM]; 908 909 #ifdef CONFIG_AW_DRM 910 struct clk *mclk[DISP_MOD_NUM]; 911 #endif 912 struct clk *clk_de[DE_NUM]; 913 struct clk *clk_bus_de[DE_NUM]; 914 #if defined(HAVE_DEVICE_COMMON_MODULE) 915 struct clk *clk_bus_extra; 916 #endif 917 struct clk *clk_bus_dpss_top[DISP_DEVICE_NUM]; 918 struct clk *clk_tcon[DISP_DEVICE_NUM]; 919 struct clk *clk_bus_tcon[DISP_DEVICE_NUM]; 920 struct clk *clk_mipi_dsi[CLK_DSI_NUM]; 921 struct clk *clk_bus_mipi_dsi[CLK_DSI_NUM]; 922 923 struct reset_control *rst_bus_de[DE_NUM]; 924 #if defined(HAVE_DEVICE_COMMON_MODULE) 925 struct reset_control *rst_bus_extra; 926 #endif 927 struct reset_control *rst_bus_dpss_top[DISP_DEVICE_NUM]; 928 struct reset_control *rst_bus_mipi_dsi[DEVICE_DSI_NUM]; 929 struct reset_control *rst_bus_tcon[DISP_DEVICE_NUM]; 930 struct reset_control *rst_bus_lvds[DEVICE_LVDS_NUM]; 931 932 s32 (*disp_int_process)(u32 sel); 933 s32 (*vsync_event)(u32 sel); 934 s32 (*start_process)(void); 935 s32 (*capture_event)(u32 sel); 936 s32 (*shadow_protect)(u32 sel, bool protect); 937 struct disp_bootloader_info boot_info; 938 struct disp_feat_init feat_init; 939 }; 940 941 typedef void (*LCD_FUNC) (unsigned int sel); 942 struct disp_lcd_function { 943 LCD_FUNC func; 944 unsigned int delay; /* ms */ 945 }; 946 947 #define LCD_MAX_SEQUENCES 7 948 struct disp_lcd_flow { 949 struct disp_lcd_function func[LCD_MAX_SEQUENCES]; 950 unsigned int func_num; 951 unsigned int cur_step; 952 }; 953 954 struct disp_lcd_panel_fun { 955 void (*cfg_panel_info)(struct panel_extend_para *info); 956 int (*cfg_open_flow)(unsigned int sel); 957 int (*cfg_close_flow)(unsigned int sel); 958 int (*lcd_user_defined_func)(unsigned int sel, unsigned int para1, 959 unsigned int para2, unsigned int para3); 960 int (*set_bright)(unsigned int sel, unsigned int bright); 961 /*check if panel is ok.return 0 if ok*/ 962 int (*esd_check)(unsigned int sel); 963 /*reset panel flow*/ 964 int (*reset_panel)(unsigned int sel); 965 /*see the definition of struct disp_lcd_esd_info */ 966 int (*set_esd_info)(struct disp_lcd_esd_info *p_info); 967 }; 968 969 struct disp_enhance_para { 970 /* basic adjust */ 971 u32 bright; 972 u32 contrast; 973 u32 saturation; 974 u32 hue; 975 u32 mode; 976 /* ehnance */ 977 u32 sharp; /* 0-off; 1~3-on. */ 978 u32 auto_contrast; /* 0-off; 1~3-on. */ 979 u32 auto_color; /* 0-off; 1-on. */ 980 u32 fancycolor_red; /* 0-Off; 1-2-on. */ 981 u32 fancycolor_green; /* 0-Off; 1-2-on. */ 982 u32 fancycolor_blue; /* 0-Off; 1-2-on. */ 983 struct disp_rect window; 984 u32 enable; 985 }; 986 987 struct disp_device { 988 struct list_head list; 989 /* data fields */ 990 char name[32]; 991 u32 disp; 992 /* indicate the index of hw device(timing controller) */ 993 u32 hwdev_index; 994 u32 fix_timing; 995 enum disp_output_type type; 996 struct disp_manager *manager; 997 struct disp_video_timings timings; 998 struct work_struct close_eink_panel_work; 999 void *priv_data; 1000 1001 /* function fileds */ 1002 /* init: script init && clock init && pwm init && register irq 1003 * exit: clock exit && unregister irq 1004 */ 1005 s32 (*init)(struct disp_device *dispdev); 1006 s32 (*exit)(struct disp_device *dispdev); 1007 1008 s32 (*set_manager)(struct disp_device *dispdev, 1009 struct disp_manager *mgr); 1010 s32 (*unset_manager)(struct disp_device *dispdev); 1011 1012 s32 (*enable)(struct disp_device *dispdev); 1013 s32 (*fake_enable)(struct disp_device *dispdev); 1014 s32 (*sw_enable)(struct disp_device *dispdev); 1015 s32 (*disable)(struct disp_device *dispdev); 1016 s32 (*is_enabled)(struct disp_device *dispdev); 1017 s32 (*check_if_enabled)(struct disp_device *dispdev); 1018 s32 (*is_used)(struct disp_device *dispdev); 1019 s32 (*get_resolution)(struct disp_device *dispdev, u32 *xres, 1020 u32 *yres); 1021 s32 (*get_dimensions)(struct disp_device *dispdev, u32 *width, 1022 u32 *height); 1023 s32 (*set_timings)(struct disp_device *dispdev, 1024 struct disp_video_timings *timings); 1025 s32 (*get_timings)(struct disp_device *dispdev, 1026 struct disp_video_timings *timings); 1027 s32 (*check_timings)(struct disp_device *dispdev, 1028 struct disp_video_timings *timings); 1029 s32 (*smooth_enable)(struct disp_device *dispdev); 1030 s32 (*detect)(struct disp_device *dispdev); 1031 s32 (*set_detect)(struct disp_device *dispdev, bool hpd); 1032 s32 (*get_status)(struct disp_device *dispdev); 1033 s32 (*get_fps)(struct disp_device *dispdev); 1034 /* 1035 * check if be in the safe period now, 1036 * safe period means the current line is less than the start_delay 1037 */ 1038 bool (*is_in_safe_period)(struct disp_device *dispdev); 1039 u32 (*usec_before_vblank)(struct disp_device *dispdev); 1040 1041 s32 (*get_input_csc)(struct disp_device *dispdev); 1042 s32 (*get_input_color_range)(struct disp_device *dispdev); 1043 s32 (*is_interlace)(struct disp_device *dispdev); 1044 1045 /* power manager */ 1046 s32 (*early_suspend)(struct disp_device *dispdev); 1047 s32 (*late_resume)(struct disp_device *dispdev); 1048 s32 (*suspend)(struct disp_device *dispdev); 1049 s32 (*resume)(struct disp_device *dispdev); 1050 1051 s32 (*dump)(struct disp_device *dispdev, char *buf); 1052 1053 /* HDMI /TV */ 1054 s32 (*set_mode)(struct disp_device *dispdev, u32 mode); 1055 s32 (*get_mode)(struct disp_device *dispdev); 1056 s32 (*set_static_config)(struct disp_device *dispdev, 1057 struct disp_device_config *config); 1058 s32 (*get_static_config)(struct disp_device *dispdev, 1059 struct disp_device_config *config); 1060 s32 (*set_dynamic_config)(struct disp_device *dispdev, 1061 struct disp_device_dynamic_config *config); 1062 s32 (*get_dynamic_config)(struct disp_device *dispdev, 1063 struct disp_device_dynamic_config *config); 1064 1065 s32 (*cec_standby_request)(struct disp_device *dispdev); 1066 s32 (*cec_send_one_touch_play)(struct disp_device *dispdev); 1067 /* 1068 * check_config_dirty 1069 * check if the config is not the same with current one 1070 */ 1071 disp_config_update_t (*check_config_dirty)(struct disp_device *dispdev, 1072 struct disp_device_config *config); 1073 s32 (*check_support_mode)(struct disp_device *dispdev, u32 mode); 1074 s32 (*set_func)(struct disp_device *dispdev, 1075 struct disp_device_func *func); 1076 s32 (*set_tv_func)(struct disp_device *dispdev, 1077 struct disp_tv_func *func); 1078 s32 (*set_enhance_mode)(struct disp_device *dispdev, u32 mode); 1079 1080 /* LCD */ 1081 s32 (*set_bright)(struct disp_device *dispdev, u32 bright); 1082 s32 (*get_bright)(struct disp_device *dispdev); 1083 s32 (*backlight_enable)(struct disp_device *dispdev); 1084 s32 (*backlight_disable)(struct disp_device *dispdev); 1085 s32 (*pwm_enable)(struct disp_device *dispdev); 1086 s32 (*pwm_disable)(struct disp_device *dispdev); 1087 s32 (*power_enable)(struct disp_device *dispdev, u32 power_id); 1088 s32 (*power_disable)(struct disp_device *dispdev, u32 power_id); 1089 s32 (*tcon_enable)(struct disp_device *dispdev); 1090 s32 (*tcon_disable)(struct disp_device *dispdev); 1091 s32 (*set_bright_dimming)(struct disp_device *dispdev, u32 dimming); 1092 1093 struct disp_lcd_flow *(*get_open_flow)(struct disp_device *dispdev); 1094 struct disp_lcd_flow *(*get_close_flow)(struct disp_device *dispdev); 1095 s32 (*pin_cfg)(struct disp_device *dispdev, u32 bon); 1096 s32 (*set_gamma_tbl)(struct disp_device *dispdev, u32 *tbl, 1097 u32 size); 1098 s32 (*enable_gamma)(struct disp_device *dispdev); 1099 s32 (*disable_gamma)(struct disp_device *dispdev); 1100 s32 (*set_color_temperature)(struct disp_device *dispdev, s32 color_temperature); 1101 s32 (*get_color_temperature)(struct disp_device *dispdev); 1102 s32 (*set_panel_func)(struct disp_device *lcd, char *name, 1103 struct disp_lcd_panel_fun *lcd_cfg); 1104 s32 (*set_open_func)(struct disp_device *lcd, LCD_FUNC func, 1105 u32 delay); 1106 s32 (*set_close_func)(struct disp_device *lcd, LCD_FUNC func, 1107 u32 delay); 1108 int (*gpio_set_value)(struct disp_device *dispdev, 1109 unsigned int io_index, u32 value); 1110 int (*gpio_set_direction)(struct disp_device *dispdev, 1111 unsigned int io_index, u32 direction); 1112 int (*get_panel_info)(struct disp_device *dispdev, 1113 struct disp_panel_para *info); 1114 void (*show_builtin_patten)(struct disp_device *dispdev, u32 patten); 1115 #if defined(CONFIG_DISP2_LCD_ESD_DETECT) 1116 s32 (*get_esd_info)(struct disp_device *dispdev, struct disp_lcd_esd_info *p_esd_info); 1117 #endif 1118 }; 1119 1120 /* manager */ 1121 struct disp_manager { 1122 /* data fields */ 1123 char name[32]; 1124 u32 disp; 1125 u32 num_chns; 1126 u32 num_layers; 1127 struct disp_device *device; 1128 struct disp_smbl *smbl; 1129 struct disp_enhance *enhance; 1130 struct disp_capture *cptr; 1131 1132 struct list_head lyr_list; 1133 #if defined(CONFIG_AW_DISP2_FB_ROTATION_SUPPORT) 1134 struct disp_rotation_sw *rot_sw; 1135 #endif 1136 1137 #ifdef SUPPORT_WB 1138 wait_queue_head_t write_back_queue; 1139 u32 write_back_finish; 1140 #endif 1141 1142 /* function fields */ 1143 s32 (*enable)(struct disp_manager *mgr); 1144 s32 (*sw_enable)(struct disp_manager *mgr); 1145 s32 (*disable)(struct disp_manager *mgr); 1146 s32 (*is_enabled)(struct disp_manager *mgr); 1147 s32 (*blank)(struct disp_manager *mgr, bool blank); 1148 1149 /* init: clock init && reg init && register irq 1150 * exit: clock exit && unregister irq 1151 */ 1152 s32 (*init)(struct disp_manager *mgr); 1153 s32 (*exit)(struct disp_manager *mgr); 1154 1155 s32 (*set_back_color)(struct disp_manager *mgr, 1156 struct disp_color *bk_color); 1157 s32 (*get_back_color)(struct disp_manager *mgr, 1158 struct disp_color *bk_color); 1159 s32 (*set_color_key)(struct disp_manager *mgr, 1160 struct disp_colorkey *ck); 1161 s32 (*get_color_key)(struct disp_manager *mgr, 1162 struct disp_colorkey *ck); 1163 1164 s32 (*get_screen_size)(struct disp_manager *mgr, u32 *width, 1165 u32 *height); 1166 s32 (*set_screen_size)(struct disp_manager *mgr, u32 width, 1167 u32 height); 1168 s32 (*get_clk_rate)(struct disp_manager *mgr); 1169 1170 /* layer mamage */ 1171 s32 (*check_layer_zorder)(struct disp_manager *mgr, 1172 struct disp_layer_config *config, 1173 u32 layer_num); 1174 s32 (*set_layer_config)(struct disp_manager *mgr, 1175 struct disp_layer_config *config, 1176 unsigned int layer_num); 1177 s32 (*get_layer_config)(struct disp_manager *mgr, 1178 struct disp_layer_config *config, 1179 unsigned int layer_num); 1180 s32 (*set_layer_config2)(struct disp_manager *mgr, 1181 struct disp_layer_config2 *config, 1182 unsigned int layer_num); 1183 s32 (*get_layer_config2)(struct disp_manager *mgr, 1184 struct disp_layer_config2 *config, 1185 unsigned int layer_num); 1186 s32 (*force_set_layer_config)(struct disp_manager *mgr, struct disp_layer_config *config, unsigned int layer_num); 1187 s32 (*force_set_layer_config_exit)(struct disp_manager *mgr); 1188 s32 (*extend_layer_config)(struct disp_manager *mgr, 1189 struct disp_layer_config *info, 1190 unsigned int layer_num); 1191 s32 (*set_output_color_range)(struct disp_manager *mgr, 1192 u32 color_range); 1193 s32 (*get_output_color_range)(struct disp_manager *mgr); 1194 s32 (*update_color_space)(struct disp_manager *mgr); 1195 s32 (*smooth_switch)(struct disp_manager *mgr); 1196 s32 (*set_palette)(struct disp_manager *mgr, struct disp_palette_config *config); 1197 1198 s32 (*apply)(struct disp_manager *mgr); 1199 s32 (*force_apply)(struct disp_manager *mgr); 1200 s32 (*update_regs)(struct disp_manager *mgr); 1201 s32 (*sync)(struct disp_manager *mgr, bool sync); 1202 s32 (*tasklet)(struct disp_manager *mgr); 1203 1204 /* debug interface, dump manager info */ 1205 s32 (*dump)(struct disp_manager *mgr, char *buf); 1206 s32 (*reg_protect)(struct disp_manager *mgr, bool protect); 1207 s32 (*set_ksc_para)(struct disp_manager *mgr, 1208 struct disp_ksc_info *pinfo); 1209 s32 (*enable_iommu)(struct disp_manager *mgr, bool en); 1210 }; 1211 1212 struct disp_layer { 1213 /* data fields */ 1214 char name[32]; 1215 u32 disp; 1216 u32 chn; 1217 u32 id; 1218 1219 /* enum disp_layer_feat caps; */ 1220 struct disp_manager *manager; 1221 struct list_head list; 1222 void *data; 1223 1224 /* function fileds */ 1225 s32 (*is_support_format)(struct disp_layer *layer, 1226 enum disp_pixel_format fmt); 1227 s32 (*set_manager)(struct disp_layer *layer, 1228 struct disp_manager *mgr); 1229 s32 (*unset_manager)(struct disp_layer *layer); 1230 s32 (*check)(struct disp_layer *layer, 1231 struct disp_layer_config *config); 1232 s32 (*check2)(struct disp_layer *layer, 1233 struct disp_layer_config2 *config); 1234 s32 (*save_and_dirty_check)(struct disp_layer *layer, 1235 struct disp_layer_config *config); 1236 s32 (*save_and_dirty_check2)(struct disp_layer *layer, 1237 struct disp_layer_config2 *config); 1238 s32 (*get_config)(struct disp_layer *layer, 1239 struct disp_layer_config *config); 1240 s32 (*get_config2)(struct disp_layer *layer, 1241 struct disp_layer_config2 *config); 1242 s32 (*apply)(struct disp_layer *layer); 1243 s32 (*force_apply)(struct disp_layer *layer); 1244 s32 (*is_dirty)(struct disp_layer *layer); 1245 s32 (*dirty_clear)(struct disp_layer *layer); 1246 /* init: NULL 1247 * exit: NULL 1248 */ 1249 s32 (*init)(struct disp_layer *layer); 1250 s32 (*exit)(struct disp_layer *layer); 1251 s32 (*get_frame_id)(struct disp_layer *layer); 1252 s32 (*dump)(struct disp_layer *layer, char *buf); 1253 }; 1254 1255 struct disp_smbl { 1256 /* static fields */ 1257 char *name; 1258 u32 disp; 1259 u32 backlight; 1260 struct disp_manager *manager; 1261 1262 /* 1263 * The following functions do not block: 1264 * 1265 * is_enabled 1266 * set_layer_info 1267 * get_layer_info 1268 * 1269 * The rest of the functions may block and cannot be called from 1270 * interrupt context 1271 */ 1272 1273 s32 (*enable)(struct disp_smbl *smbl); 1274 s32 (*disable)(struct disp_smbl *smbl); 1275 bool (*is_enabled)(struct disp_smbl *smbl); 1276 s32 (*set_manager)(struct disp_smbl *smbl, struct disp_manager *mgr); 1277 s32 (*unset_manager)(struct disp_smbl *smbl); 1278 s32 (*update_backlight)(struct disp_smbl *smbl, unsigned int bl); 1279 1280 /* init: NULL 1281 * exit: NULL 1282 */ 1283 s32 (*init)(struct disp_smbl *smbl); 1284 s32 (*exit)(struct disp_smbl *smbl); 1285 1286 s32 (*apply)(struct disp_smbl *smbl); 1287 s32 (*update_regs)(struct disp_smbl *smbl); 1288 s32 (*force_apply)(struct disp_smbl *smbl); 1289 s32 (*sync)(struct disp_smbl *smbl); 1290 s32 (*tasklet)(struct disp_smbl *smbl); 1291 1292 s32 (*set_window)(struct disp_smbl *smbl, struct disp_rect *window); 1293 s32 (*get_window)(struct disp_smbl *smbl, struct disp_rect *window); 1294 s32 (*dump)(struct disp_smbl *smbl, char *buf); 1295 }; 1296 1297 struct disp_enhance { 1298 /* static fields */ 1299 char *name; 1300 u32 disp; 1301 struct disp_manager *manager; 1302 1303 /* 1304 * The following functions do not block: 1305 * 1306 * is_enabled 1307 * set_layer_info 1308 * get_layer_info 1309 * 1310 * The rest of the functions may block and cannot be called from 1311 * interrupt context 1312 */ 1313 1314 s32 (*enable)(struct disp_enhance *enhance); 1315 s32 (*disable)(struct disp_enhance *enhance); 1316 bool (*is_enabled)(struct disp_enhance *enhance); 1317 s32 (*set_manager)(struct disp_enhance *enhance, 1318 struct disp_manager *mgr); 1319 s32 (*unset_manager)(struct disp_enhance *enhance); 1320 1321 /* init: NULL 1322 * exit: NULL 1323 */ 1324 s32 (*init)(struct disp_enhance *enhance); 1325 s32 (*exit)(struct disp_enhance *enhance); 1326 1327 s32 (*apply)(struct disp_enhance *enhance); 1328 s32 (*update_regs)(struct disp_enhance *enhance); 1329 s32 (*force_apply)(struct disp_enhance *enhance); 1330 s32 (*sync)(struct disp_enhance *enhance); 1331 s32 (*tasklet)(struct disp_enhance *enhance); 1332 1333 /* power manager */ 1334 s32 (*early_suspend)(struct disp_enhance *enhance); 1335 s32 (*late_resume)(struct disp_enhance *enhance); 1336 s32 (*suspend)(struct disp_enhance *enhance); 1337 s32 (*resume)(struct disp_enhance *enhance); 1338 1339 s32 (*set_bright)(struct disp_enhance *enhance, u32 val); 1340 s32 (*set_saturation)(struct disp_enhance *enhance, u32 val); 1341 s32 (*set_contrast)(struct disp_enhance *enhance, u32 val); 1342 s32 (*set_hue)(struct disp_enhance *enhance, u32 val); 1343 s32 (*set_edge)(struct disp_enhance *enhance, u32 val); 1344 s32 (*set_detail)(struct disp_enhance *enhance, u32 val); 1345 s32 (*set_denoise)(struct disp_enhance *enhance, u32 val); 1346 s32 (*set_mode)(struct disp_enhance *enhance, u32 val); 1347 s32 (*set_window)(struct disp_enhance *enhance, 1348 struct disp_rect *window); 1349 s32 (*get_bright)(struct disp_enhance *enhance); 1350 s32 (*get_saturation)(struct disp_enhance *enhance); 1351 s32 (*get_contrast)(struct disp_enhance *enhance); 1352 s32 (*get_hue)(struct disp_enhance *enhance); 1353 s32 (*get_edge)(struct disp_enhance *enhance); 1354 s32 (*get_detail)(struct disp_enhance *enhance); 1355 s32 (*get_denoise)(struct disp_enhance *enhance); 1356 s32 (*get_mode)(struct disp_enhance *enhance); 1357 s32 (*get_window)(struct disp_enhance *enhance, 1358 struct disp_rect *window); 1359 s32 (*set_para)(struct disp_enhance *enhance, 1360 struct disp_enhance_para *para); 1361 s32 (*demo_enable)(struct disp_enhance *enhance); 1362 s32 (*demo_disable)(struct disp_enhance *enhance); 1363 s32 (*dump)(struct disp_enhance *enhance, char *buf); 1364 }; 1365 1366 struct disp_capture { 1367 char name[16]; 1368 u32 disp; 1369 struct disp_manager *manager; 1370 1371 s32 (*set_manager)(struct disp_capture *cptr, 1372 struct disp_manager *mgr); 1373 s32 (*unset_manager)(struct disp_capture *cptr); 1374 s32 (*start)(struct disp_capture *cptr); 1375 s32 (*commmit)(struct disp_capture *cptr, 1376 struct disp_capture_info *info); 1377 s32 (*commmit2)(struct disp_capture *cptr, 1378 struct disp_capture_info2 *info); 1379 s32 (*stop)(struct disp_capture *cptr); 1380 s32 (*sync)(struct disp_capture *cptr); 1381 s32 (*tasklet)(struct disp_capture *cptr); 1382 s32 (*init)(struct disp_capture *cptr); 1383 s32 (*exit)(struct disp_capture *cptr); 1384 /* 0: finish, other: fail/err */ 1385 s32 (*query)(struct disp_capture *cptr); 1386 1387 /* debug interface, dump capture info */ 1388 s32 (*dump)(struct disp_capture *cptr, char *buf); 1389 /* inner interface */ 1390 s32 (*apply)(struct disp_capture *cptr); 1391 }; 1392 1393 #if defined(CONFIG_AW_DISP2_FB_ROTATION_SUPPORT) 1394 struct disp_rotation_sw { 1395 u32 disp; 1396 u32 degree; 1397 struct disp_rectsz screen_size; /* virtual screen_size */ 1398 1399 struct disp_manager *manager; 1400 1401 s32 (*init)(struct disp_rotation_sw *rot_sw); 1402 s32 (*exit)(struct disp_rotation_sw *rot_sw); 1403 s32 (*set_layer_degree)(struct disp_rotation_sw *rot_sw, u32 chn, 1404 u32 lyr_id, u32 degree); 1405 s32 (*get_layer_degree)(struct disp_rotation_sw *rot_sw, u32 chn, 1406 u32 lyr_id); 1407 s32 (*set_manager)(struct disp_rotation_sw *rot_sw, 1408 struct disp_manager *mgr); 1409 s32 (*unset_manager)(struct disp_rotation_sw *rot_sw); 1410 s32 (*apply)(struct disp_rotation_sw *rot_sw, 1411 struct disp_layer_config *lyr_config, 1412 struct disp_rect src_dirty_rect); 1413 s32 (*checkout)(struct disp_rotation_sw *rot_sw, 1414 struct disp_layer_config *lyr_config); 1415 }; 1416 #endif 1417 1418 struct ee_img { 1419 unsigned long addr; 1420 unsigned int pitch; 1421 unsigned int w; /* image width */ 1422 unsigned int h; /* image height */ 1423 }; 1424 1425 struct rect_size { 1426 u32 width; 1427 u32 height; 1428 u32 align; 1429 }; 1430 1431 #if defined(CONFIG_EINK_PANEL_USED) 1432 struct area_info { 1433 unsigned int x_top; 1434 unsigned int y_top; 1435 unsigned int x_bottom; 1436 unsigned int y_bottom; 1437 }; 1438 1439 struct eink_timing_param { 1440 unsigned int lbl; /* */ 1441 unsigned int lel; /* */ 1442 unsigned int lsl; 1443 unsigned int fbl; /* */ 1444 unsigned int fel; /* */ 1445 unsigned int fsl; /* */ 1446 unsigned int width; /* image width */ 1447 unsigned int height; /* image height */ 1448 }; 1449 1450 enum eink_flash_mode { 1451 LOCAL, 1452 GLOBAL, 1453 INIT 1454 }; 1455 1456 enum buf_use_state { 1457 FREE, 1458 USED 1459 }; 1460 1461 enum eink_update_mode { 1462 /* GLOBAL */ 1463 EINK_INIT_MODE = 0x01, 1464 EINK_DU_MODE = 0x02, 1465 EINK_GC16_MODE = 0x04, 1466 EINK_A2_MODE = 0x10, 1467 EINK_GC16_LOCAL_MODE = 0x84, 1468 1469 /* LOCAL */ 1470 EINK_DU_RECT_MODE = 0x402, 1471 EINK_GC16_RECT_MODE = 0x404, 1472 EINK_A2_RECT_MODE = 0x410, 1473 EINK_GC16_LOCAL_RECT_MODE = 0x484, 1474 }; 1475 1476 struct eink_8bpp_image { 1477 enum eink_update_mode update_mode; 1478 enum eink_flash_mode flash_mode; 1479 enum buf_use_state state; 1480 void *vaddr; 1481 void *paddr; 1482 bool window_calc_enable; 1483 struct rect_size size; 1484 struct area_info update_area; 1485 }; 1486 1487 struct eink_init_param { 1488 bool used; 1489 u8 eink_moudule_type; 1490 u8 eink_version_type; 1491 u8 eink_ctrl_data_type; 1492 u8 eink_bits; /*0->3bits,1->4bits,2->5bits */ 1493 u8 eink_mode; /*0->8data,1->16data */ 1494 struct eink_timing_param timing; 1495 char wavefile_path[32]; 1496 }; 1497 1498 enum eink_bit_num { 1499 EINK_BIT_1 = 0x01, 1500 EINK_BIT_2 = 0x02, 1501 EINK_BIT_3 = 0x03, 1502 EINK_BIT_4 = 0x04, 1503 EINK_BIT_5 = 0x05 1504 }; 1505 1506 /* #define EINK_FLUSH_TIME_TEST */ 1507 1508 struct disp_eink_manager { 1509 unsigned int disp; 1510 unsigned int test; 1511 int tcon_flag; 1512 int eink_panel_temperature; 1513 1514 unsigned int flush_continue_flag; 1515 struct tasklet_struct sync_tasklet; 1516 struct tasklet_struct decode_tasklet; 1517 wait_queue_head_t decode_taske_queue; 1518 struct work_struct decode_work; 1519 struct eink_private *private_data; 1520 struct disp_manager *mgr; 1521 struct eink_buffer_manager *buffer_mgr; 1522 struct pipeline_manager *pipeline_mgr; 1523 struct format_manager *convert_mgr; 1524 struct task_struct *detect_fresh_task; 1525 struct task_struct *debug_task; 1526 struct mutex standby_lock; 1527 int (*eink_update)(struct disp_eink_manager *manager, 1528 struct disp_layer_config_inner *config, 1529 unsigned int layer_num, 1530 enum eink_update_mode mode, 1531 struct area_info update_area); 1532 int (*enable)(struct disp_eink_manager *); 1533 int (*disable)(struct disp_eink_manager *); 1534 int (*op_skip)(struct disp_eink_manager *manager, u32 skip); 1535 int (*suspend)(struct disp_eink_manager *); 1536 int (*resume)(struct disp_eink_manager *); 1537 void (*clearwd)(struct disp_eink_manager *, int); 1538 /*for debug */ 1539 int (*decode)(struct disp_eink_manager *, int); 1540 int (*set_temperature)(struct disp_eink_manager *manager, 1541 unsigned int temp); 1542 unsigned int (*get_temperature)(struct disp_eink_manager *manager); 1543 }; 1544 1545 struct image_format { 1546 enum disp_pixel_format format; 1547 unsigned int width; 1548 unsigned int height; 1549 unsigned long addr1; 1550 unsigned long addr2; 1551 unsigned long addr3; 1552 }; 1553 1554 struct format_manager { 1555 unsigned int disp; 1556 unsigned int irq_num; 1557 unsigned int write_back_finish; 1558 wait_queue_head_t write_back_queue; 1559 1560 struct clk *clk; 1561 struct clk *clk_bus; 1562 1563 struct reset_control *rst; 1564 1565 int (*enable)(unsigned int id); 1566 int (*disable)(unsigned int id); 1567 int (*start_convert)(unsigned int id, 1568 struct disp_layer_config_inner *config, 1569 unsigned int layer_num, 1570 struct image_format *dest); 1571 }; 1572 #endif 1573 #endif 1574