1 /*
2 * Copyright (c) 2022 Unionman Technology Co., Ltd.
3 *
4 * HDF is dual licensed: you can use it either under the terms of
5 * the GPL, or the BSD license, at your option.
6 * See the LICENSE file in the root of this repository for complete details.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/of_irq.h>
11 #include <linux/of_platform.h>
12 #include <linux/module.h>
13 #include <linux/reset.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/interrupt.h>
16
17 #include "securec.h"
18 #include "axg_common.h"
19 #include "axg_fifo.h"
20
21 #define DMA_SIZE_MAX (1*1024*1024)
22 #define FIFO_DEPTH_DEFAULT (256)
23
24 // FRDDR definition
25 #define CTRL0_FRDDR_PP_MODE BIT(30)
26 #define CTRL0_SEL1_EN_SHIFT 3
27 #define CTRL0_SEL2_SHIFT 4
28 #define CTRL0_SEL2_EN_SHIFT 7
29 #define CTRL0_SEL3_SHIFT 8
30 #define CTRL0_SEL3_EN_SHIFT 11
31 #define CTRL1_FRDDR_FORCE_FINISH BIT(12)
32 #define CTRL2_SEL1_SHIFT 0
33 #define CTRL2_SEL1_EN_SHIFT 4
34 #define CTRL2_SEL2_SHIFT 8
35 #define CTRL2_SEL2_EN_SHIFT 12
36 #define CTRL2_SEL3_SHIFT 16
37 #define CTRL2_SEL3_EN_SHIFT 20
38
39 // TODDR definition
40 #define CTRL0_TODDR_SEL_RESAMPLE BIT(30)
41 #define CTRL0_TODDR_EXT_SIGNED BIT(29)
42 #define CTRL0_TODDR_PP_MODE BIT(28)
43 #define CTRL0_TODDR_SYNC_CH BIT(27)
44 #define CTRL0_TODDR_TYPE_MASK GENMASK(15, 13)
45 #define CTRL0_TODDR_TYPE(x) ((x) << 13)
46 #define CTRL0_TODDR_MSB_POS_MASK GENMASK(12, 8)
47 #define CTRL0_TODDR_MSB_POS(x) ((x) << 8)
48 #define CTRL0_TODDR_LSB_POS_MASK GENMASK(7, 3)
49 #define CTRL0_TODDR_LSB_POS(x) ((x) << 3)
50 #define CTRL1_TODDR_FORCE_FINISH BIT(25)
51 #define CTRL1_SEL_SHIFT 28
52 #define TODDR_MSB_POS 31
53
54 static LIST_HEAD(axg_fifo_list);
55
dma_enable(struct axg_fifo * fifo,bool enable)56 static void dma_enable(struct axg_fifo *fifo, bool enable)
57 {
58 regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_DMA_EN,
59 enable ? CTRL0_DMA_EN : 0);
60 }
61
62 /* allocate the coherent DMA pages */
fifo_pages_alloc(struct axg_fifo * fifo,size_t size)63 static int fifo_pages_alloc(struct axg_fifo *fifo, size_t size)
64 {
65 gfp_t gfp_flags;
66
67 gfp_flags = GFP_KERNEL | __GFP_COMP /* compound page lets parts be mapped */
68 | __GFP_NORETRY /* don't trigger OOM-killer */
69 | __GFP_NOWARN; /* no stack trace print - this call is non-critical */
70 fifo->dma_vaddr = dma_alloc_coherent(fifo->dev, size, &fifo->dma_addr,
71 gfp_flags);
72
73 if (!fifo->dma_vaddr) {
74 return -1;
75 }
76
77 fifo->dma_area = size;
78
79 dev_info(fifo->dev, "%s: alloc dma success, size=%lu", fifo->name_prefix, size);
80
81 return 0;
82 }
83
fifo_update_bits(struct axg_fifo * fifo,unsigned int reg,unsigned int mask,unsigned int val)84 static int fifo_update_bits(struct axg_fifo *fifo,
85 unsigned int reg, unsigned int mask, unsigned int val)
86 {
87 int ret;
88
89 ret = regmap_update_bits(fifo->map, reg, mask, val);
90
91 dev_info(fifo->dev, "%s(name=%s, reg=0x%x, mask=0x%x, val=0x%x): %d\n",
92 __FUNCTION__, fifo->name_prefix, reg, mask, val, ret);
93
94 return ret;
95 }
96
fifo_register(struct axg_fifo * fifo)97 static int fifo_register(struct axg_fifo *fifo)
98 {
99 struct axg_fifo *f;
100 list_for_each_entry(f, &axg_fifo_list, list) {
101 if (!strcmp(f->name_prefix, fifo->name_prefix)) {
102 dev_err(fifo->dev, "duplicated dev[%s], no need to register\n",
103 fifo->name_prefix);
104 return -1;
105 }
106 }
107
108 list_add_tail(&fifo->list, &axg_fifo_list);
109
110 dev_info(fifo->dev, "Register Snd FIFO SUCCESS: %s\n", fifo->name_prefix);
111
112 return 0;
113 }
114
fifo_find(const char * name_prefix)115 static struct axg_fifo *fifo_find(const char *name_prefix)
116 {
117 struct axg_fifo *f;
118 list_for_each_entry(f, &axg_fifo_list, list) {
119 if (!strcmp(f->name_prefix, name_prefix)) {
120 return f;
121 }
122 }
123
124 return NULL;
125 }
126
frddr_pointer_reset(struct axg_fifo * fifo)127 static int frddr_pointer_reset(struct axg_fifo *fifo)
128 {
129 if (!fifo->is_g12a) {
130 return 0; // do nothing for axg
131 }
132
133 /* Reset the read pointer to the FIFO_INIT_ADDR */
134 regmap_update_bits(fifo->map, FIFO_CTRL1,
135 CTRL1_FRDDR_FORCE_FINISH, 0);
136 regmap_update_bits(fifo->map, FIFO_CTRL1,
137 CTRL1_FRDDR_FORCE_FINISH, CTRL1_FRDDR_FORCE_FINISH);
138 regmap_update_bits(fifo->map, FIFO_CTRL1,
139 CTRL1_FRDDR_FORCE_FINISH, 0);
140
141 return 0;
142 }
143
toddr_pointer_reset(struct axg_fifo * fifo)144 static int toddr_pointer_reset(struct axg_fifo *fifo)
145 {
146 if (!fifo->is_g12a) {
147 return 0; // do nothing for axg
148 }
149
150 /* Reset the write pointer to the FIFO_INIT_ADDR */
151 regmap_update_bits(fifo->map, FIFO_CTRL1,
152 CTRL1_TODDR_FORCE_FINISH, 0);
153 regmap_update_bits(fifo->map, FIFO_CTRL1,
154 CTRL1_TODDR_FORCE_FINISH, CTRL1_TODDR_FORCE_FINISH);
155 regmap_update_bits(fifo->map, FIFO_CTRL1,
156 CTRL1_TODDR_FORCE_FINISH, 0);
157
158 return 0;
159 }
160
frddr_dai_startup(struct axg_fifo * fifo)161 static int frddr_dai_startup(struct axg_fifo *fifo)
162 {
163 unsigned int val;
164
165 /* Apply single buffer mode to the interface */
166 regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_FRDDR_PP_MODE, 0);
167
168 /* Use all fifo depth */
169 val = (fifo->depth / AXG_FIFO_BURST) - 1;
170 regmap_update_bits(fifo->map, FIFO_CTRL1, CTRL1_FRDDR_DEPTH_MASK,
171 CTRL1_FRDDR_DEPTH(val));
172
173 return 0;
174 }
175
toddr_dai_startup(struct axg_fifo * fifo)176 static int toddr_dai_startup(struct axg_fifo *fifo)
177 {
178 /* Select orginal data - resampling not supported ATM */
179 regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_TODDR_SEL_RESAMPLE, 0);
180
181 /* Only signed format are supported ATM */
182 regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_TODDR_EXT_SIGNED,
183 CTRL0_TODDR_EXT_SIGNED);
184
185 /* Apply single buffer mode to the interface */
186 regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_TODDR_PP_MODE, 0);
187
188 if (fifo->is_g12a) {
189 /*
190 * Make sure the first channel ends up in the at beginning of the output
191 * As weird as it looks, without this the first channel may be misplaced
192 * in memory, with a random shift of 2 channels.
193 */
194 regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_TODDR_SYNC_CH,
195 CTRL0_TODDR_SYNC_CH);
196 }
197
198 return 0;
199 }
200
toddr_dai_hw_params(struct axg_fifo * fifo,unsigned int bit_width,unsigned int phys_width)201 static int toddr_dai_hw_params(struct axg_fifo *fifo,
202 unsigned int bit_width, unsigned int phys_width)
203 {
204 unsigned int type, width;
205
206 switch (phys_width) {
207 case AXG_BIT_WIDTH8:
208 type = 0; /* 8 samples of 8 bits */
209 break;
210 case AXG_BIT_WIDTH16:
211 type = 2U; /* 4 samples of 16 bits - right justified */
212 break;
213 case AXG_BIT_WIDTH32:
214 type = 4U; /* 2 samples of 32 bits - right justified */
215 break;
216 default:
217 return -EINVAL;
218 }
219
220 width = bit_width;
221
222 regmap_update_bits(fifo->map, FIFO_CTRL0,
223 CTRL0_TODDR_TYPE_MASK |
224 CTRL0_TODDR_MSB_POS_MASK |
225 CTRL0_TODDR_LSB_POS_MASK,
226 CTRL0_TODDR_TYPE(type) |
227 CTRL0_TODDR_MSB_POS(TODDR_MSB_POS) |
228 CTRL0_TODDR_LSB_POS(TODDR_MSB_POS - (width - 1)));
229
230 return 0;
231 }
232
meson_axg_fifo_pcm_pointer(struct axg_fifo * fifo)233 uint32_t meson_axg_fifo_pcm_pointer(struct axg_fifo *fifo)
234 {
235 if (!fifo->pcm_opened) {
236 return 0;
237 }
238
239 unsigned int addr;
240
241 regmap_read(fifo->map, FIFO_STATUS2, &addr);
242
243 if (addr > fifo->dma_addr) {
244 return (uint32_t)(addr - fifo->dma_addr);
245 } else {
246 return 0;
247 }
248 }
249
meson_axg_fifo_pcm_hw_params(struct axg_fifo * fifo,unsigned int period,unsigned int cir_buf_size)250 int meson_axg_fifo_pcm_hw_params(struct axg_fifo *fifo,
251 unsigned int period, unsigned int cir_buf_size)
252 {
253 unsigned int burst_num, threshold;
254 dma_addr_t end_ptr;
255
256 if (!fifo->pcm_opened) {
257 return -1;
258 }
259
260 if (cir_buf_size > fifo->dma_area) {
261 dev_err(fifo->dev, "invalid param: cir_buf_size(%d) > dma_area(%d)",
262 cir_buf_size, fifo->dma_area);
263 return -EINVAL;
264 }
265
266 /* Setup dma memory pointers */
267 end_ptr = fifo->dma_addr + cir_buf_size - AXG_FIFO_BURST;
268 regmap_write(fifo->map, FIFO_START_ADDR, fifo->dma_addr);
269 regmap_write(fifo->map, FIFO_FINISH_ADDR, end_ptr);
270
271 /* Setup interrupt periodicity */
272 burst_num = period / AXG_FIFO_BURST;
273 regmap_write(fifo->map, FIFO_INT_ADDR, burst_num);
274
275 /*
276 * Start the fifo request on the smallest of the following:
277 * - Half the fifo size
278 * - Half the period size
279 */
280 threshold = min(period / 2U, fifo->depth / 2U);
281
282 /*
283 * With the threshold in bytes, register value is:
284 * V = (threshold / burst) - 1
285 */
286 threshold /= AXG_FIFO_BURST;
287 regmap_field_write(fifo->field_threshold,
288 threshold ? threshold - 1 : 0);
289
290 /* Enable block count irq */
291 regmap_update_bits(fifo->map, FIFO_CTRL0,
292 CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT),
293 CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT));
294
295 if (fifo->is_g12a) {
296 /* Set the initial memory address of the DMA */
297 regmap_write(fifo->map, FIFO_INIT_ADDR, fifo->dma_addr);
298 }
299
300 fifo->dma_cir_size = cir_buf_size;
301
302 dev_info(fifo->dev, "%s: %s(period=%u, cir_buf_size=%u) SUCCESS.\n ",
303 fifo->name_prefix, __FUNCTION__, period, cir_buf_size);
304
305 return 0;
306 }
307
meson_axg_fifo_pcm_hw_free(struct axg_fifo * fifo)308 int meson_axg_fifo_pcm_hw_free(struct axg_fifo *fifo)
309 {
310 /* Disable the block count irq */
311 regmap_update_bits(fifo->map, FIFO_CTRL0,
312 CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT), 0);
313
314 return 0;
315 }
316
meson_axg_fifo_pcm_prepare(struct axg_fifo * fifo)317 int meson_axg_fifo_pcm_prepare(struct axg_fifo *fifo)
318 {
319 int ret = 0;
320
321 if (!fifo->pcm_opened) {
322 return -1;
323 }
324
325 /* reset FIFO pointer */
326 if (fifo->is_frddr) {
327 ret = frddr_pointer_reset(fifo);
328 } else {
329 ret = toddr_pointer_reset(fifo);
330 }
331
332 /* clear dma buffer */
333 if (fifo->dma_cir_size) {
334 (void)memset_s(fifo->dma_vaddr, fifo->dma_area, 0, fifo->dma_cir_size);
335 }
336
337 return ret;
338 }
339
axg_fifo_ack_irq(struct axg_fifo * fifo,u8 mask)340 static void axg_fifo_ack_irq(struct axg_fifo *fifo, u8 mask)
341 {
342 regmap_update_bits(fifo->map, FIFO_CTRL1,
343 CTRL1_INT_CLR(FIFO_INT_MASK),
344 CTRL1_INT_CLR(mask));
345
346 /* Clear must also be cleared */
347 regmap_update_bits(fifo->map, FIFO_CTRL1,
348 CTRL1_INT_CLR(FIFO_INT_MASK),
349 0);
350 }
351
axg_fifo_pcm_irq_block(int irq,struct axg_fifo * fifo)352 static irqreturn_t axg_fifo_pcm_irq_block(int irq, struct axg_fifo *fifo)
353 {
354 unsigned int status;
355
356 regmap_read(fifo->map, FIFO_STATUS1, &status);
357
358 status = STATUS1_INT_STS(status) & FIFO_INT_MASK;
359 if (status & FIFO_INT_COUNT_REPEAT) {
360 ; /* DO nothing here */
361 } else {
362 dev_dbg(fifo->dev, "unexpected irq - STS 0x%02x\n",
363 status);
364 }
365
366 /* Ack irqs */
367 axg_fifo_ack_irq(fifo, status);
368
369 return IRQ_RETVAL(status);
370 }
371
meson_axg_fifo_dai_hw_params(struct axg_fifo * fifo,unsigned int bit_width,unsigned int phys_width)372 int meson_axg_fifo_dai_hw_params(struct axg_fifo *fifo,
373 unsigned int bit_width, unsigned int phys_width)
374 {
375 if (!fifo->pcm_opened) {
376 return -1;
377 }
378
379 /* Do nothing with FRDDR */
380 if (fifo->is_frddr) {
381 return 0;
382 }
383
384 return toddr_dai_hw_params(fifo, bit_width, phys_width);
385 }
386
meson_axg_fifo_get(const char * name_prefix)387 struct axg_fifo *meson_axg_fifo_get(const char *name_prefix)
388 {
389 return fifo_find(name_prefix);
390 }
391
meson_axg_fifo_update_bits(struct axg_fifo * fifo,unsigned int reg,unsigned int mask,unsigned int val)392 int meson_axg_fifo_update_bits(struct axg_fifo *fifo,
393 unsigned int reg, unsigned int mask, unsigned int val)
394 {
395 return fifo_update_bits(fifo, reg, mask, val);
396 }
397
meson_axg_fifo_pcm_open(struct axg_fifo * fifo)398 int meson_axg_fifo_pcm_open(struct axg_fifo *fifo)
399 {
400 int ret;
401
402 if (fifo->pcm_opened) {
403 return 0;
404 }
405
406 ret = request_irq(fifo->irq, (irqreturn_t(*)(int, void *))axg_fifo_pcm_irq_block, 0,
407 dev_name(fifo->dev), fifo);
408 if (ret) {
409 return ret;
410 }
411
412 /* Enable pclk to access registers and clock the fifo ip */
413 ret = clk_prepare_enable(fifo->pclk);
414 if (ret) {
415 free_irq(fifo->irq, fifo);
416 return ret;
417 }
418
419 /* Setup status2 so it reports the memory pointer */
420 regmap_update_bits(fifo->map, FIFO_CTRL1,
421 CTRL1_STATUS2_SEL_MASK,
422 CTRL1_STATUS2_SEL(STATUS2_SEL_DDR_READ));
423
424 /* Make sure the dma is initially disabled */
425 dma_enable(fifo, false);
426
427 /* Disable irqs until params are ready */
428 regmap_update_bits(fifo->map, FIFO_CTRL0,
429 CTRL0_INT_EN(FIFO_INT_MASK), 0);
430
431 /* Clear any pending interrupt */
432 axg_fifo_ack_irq(fifo, FIFO_INT_MASK);
433
434 /* Take memory arbitror out of reset */
435 ret = reset_control_deassert(fifo->arb);
436 if (ret) {
437 clk_disable_unprepare(fifo->pclk);
438 free_irq(fifo->irq, fifo);
439 return ret;
440 }
441
442 if (fifo->is_frddr) {
443 ret = frddr_dai_startup(fifo);
444 } else {
445 ret = toddr_dai_startup(fifo);
446 }
447
448 if (ret) {
449 clk_disable_unprepare(fifo->pclk);
450 free_irq(fifo->irq, fifo);
451 return ret;
452 }
453
454 fifo->pcm_opened = true;
455 return 0;
456 }
457
meson_axg_fifo_pcm_close(struct axg_fifo * fifo)458 int meson_axg_fifo_pcm_close(struct axg_fifo *fifo)
459 {
460 int ret;
461
462 if (!fifo->pcm_opened) {
463 return 0;
464 }
465
466 /* Put the memory arbitror back in reset */
467 ret = reset_control_assert(fifo->arb);
468
469 /* Disable fifo ip and register access */
470 clk_disable_unprepare(fifo->pclk);
471
472 /* remove IRQ */
473 free_irq(fifo->irq, fifo);
474
475 fifo->pcm_opened = false;
476 return ret;
477 }
478
meson_axg_fifo_pcm_enable(struct axg_fifo * fifo,bool enable)479 int meson_axg_fifo_pcm_enable(struct axg_fifo *fifo, bool enable)
480 {
481 if (!fifo->pcm_opened) {
482 return -1;
483 }
484
485 dma_enable(fifo, enable);
486 return 0;
487 }
488
489 static const struct regmap_config axg_fifo_regmap_cfg = {
490 .reg_bits = 32,
491 .val_bits = 32,
492 .reg_stride = 4,
493 .max_register = FIFO_CTRL2,
494 };
495
axg_fifo_of_parse(struct axg_fifo * fifo)496 static int axg_fifo_of_parse(struct axg_fifo *fifo)
497 {
498 struct device *dev = fifo->dev;
499 int ret;
500
501 ret = of_property_read_string(dev->of_node, "sound-name-prefix", &fifo->name_prefix);
502 if (ret) {
503 dev_err(dev, "failed to get sound-name-prefix\n");
504 return ret;
505 }
506
507 ret = of_property_read_u32(dev->of_node, "amlogic,fifo-depth", &fifo->depth);
508 if (ret) {
509 /* Error out for anything but a missing property */
510 if (ret != -EINVAL) {
511 return ret;
512 }
513
514 /*
515 * If the property is missing, it might be because of an old
516 * DT. In such case, assume the smallest known fifo depth
517 */
518 fifo->depth = FIFO_DEPTH_DEFAULT;
519 dev_warn(dev, "fifo depth not found, assume %u bytes\n", fifo->depth);
520 }
521
522 fifo->pclk = devm_clk_get(dev, NULL);
523 if (IS_ERR(fifo->pclk)) {
524 if (PTR_ERR(fifo->pclk) != -EPROBE_DEFER) {
525 dev_err(dev, "failed to get pclk: %ld\n", PTR_ERR(fifo->pclk));
526 }
527 return PTR_ERR(fifo->pclk);
528 }
529
530 fifo->arb = devm_reset_control_get_exclusive(dev, NULL);
531 if (IS_ERR(fifo->arb)) {
532 if (PTR_ERR(fifo->arb) != -EPROBE_DEFER) {
533 dev_err(dev, "failed to get arb reset: %ld\n", PTR_ERR(fifo->arb));
534 }
535 return PTR_ERR(fifo->arb);
536 }
537
538 fifo->irq = of_irq_get(dev->of_node, 0);
539 if (fifo->irq <= 0) {
540 dev_err(dev, "failed to get irq: %d\n", fifo->irq);
541 return fifo->irq;
542 }
543
544 return 0;
545 }
546
meson_axg_fifo_probe(struct platform_device * pdev)547 int meson_axg_fifo_probe(struct platform_device *pdev)
548 {
549 struct device *dev = &pdev->dev;
550 const struct axg_fifo_match_data *data;
551 struct axg_fifo *fifo;
552 int ret;
553
554 data = of_device_get_match_data(dev);
555 if (!data) {
556 dev_err(dev, "failed to match device\n");
557 return -ENODEV;
558 }
559
560 fifo = devm_kzalloc(dev, sizeof(*fifo), GFP_KERNEL);
561 if (!fifo) {
562 return -ENOMEM;
563 }
564
565 platform_set_drvdata(pdev, fifo);
566
567 fifo->is_frddr = data->is_frddr;
568 fifo->is_g12a = data->is_g12a;
569 fifo->dev = dev;
570
571 ret = axg_fifo_of_parse(fifo);
572 if (ret) {
573 dev_err(dev, "axg_fifo_of_parse failed: %d\n", ret);
574 return ret;
575 }
576
577 fifo->map = devm_regmap_init_mmio(dev, devm_platform_ioremap_resource(pdev, 0),
578 &axg_fifo_regmap_cfg);
579 if (IS_ERR(fifo->map)) {
580 dev_err(dev, "failed to init regmap: %ld\n", PTR_ERR(fifo->map));
581 return PTR_ERR(fifo->map);
582 }
583
584 fifo->field_threshold = devm_regmap_field_alloc(dev, fifo->map, data->field_threshold);
585 if (IS_ERR(fifo->field_threshold)) {
586 return PTR_ERR(fifo->field_threshold);
587 }
588
589 ret = fifo_pages_alloc(fifo, DMA_SIZE_MAX);
590 if (ret) {
591 dev_err(dev, "failed to alloc dma for %s\n", fifo->name_prefix);
592 return ret;
593 }
594
595 if (fifo->is_frddr) {
596 /* clear "FRDDR_x SRC x EN" */
597 fifo_update_bits(fifo, FIFO_CTRL0, 0x888, 0);
598 }
599
600 fifo_register(fifo);
601
602 dev_info(dev, "meson_axg_fifo_probe(%s, is_frddr=%d, is_g12a=%d) SUCCESS.\n",
603 fifo->name_prefix, fifo->is_frddr, fifo->is_g12a);
604 return 0;
605 }
606