1 /* 2 * combo csi module 3 * 4 * Copyright (c) 2019 by Allwinnertech Co., Ltd. http://www.allwinnertech.com 5 * 6 * Authors: Zheng Zequn <zequnzheng@allwinnertech.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include "combo_csi_reg_i.h" 14 #include "../protocol.h" 15 16 #ifndef __COMBO_CSI_REG__H__ 17 #define __COMBO_CSI_REG__H__ 18 19 #define MAX_MIPI_CH 4 20 #define MAX_LANE_NUM 12 21 22 enum phy_laneck_en { 23 CK_1LANE = 0x1, 24 CK_2LANE = 0x3, 25 }; 26 27 enum phy_lanedt_en { 28 DT_1LANE = 0x1, 29 DT_2LANE = 0x3, 30 DT_3LANE = 0x7, 31 DT_4LANE = 0xf, 32 }; 33 34 enum phy_mipi_lpck_en { 35 LPCK_CLOSE = 0x0, /*sub-lvds/hispi*/ 36 LPCK_1LANE = 0x1, /*mipi*/ 37 LPCK_2LANE = 0x3, 38 }; 39 40 enum phy_mipi_lpdt_en { 41 LPDT_CLOSE = 0x0, /*sub-lvds/hispi*/ 42 LPDT_1LANE = 0x1,/*mipi*/ 43 LPDT_2LANE = 0x3, 44 LPDT_3LANE = 0x7, 45 LPDT_4LANE = 0xf, 46 }; 47 48 enum phy_deskew_period_en { 49 DK_PR_1LANE = 0x1, 50 DK_PR_2LANE = 0x3, 51 DK_PR_3LANE = 0x7, 52 DK_PR_4LANE = 0xf, 53 }; 54 55 enum phy_deskew_en { 56 DK_1LANE = 0x1, 57 DK_2LANE = 0x3, 58 DK_3LANE = 0x7, 59 DK_4LANE = 0xf, 60 }; 61 62 enum phy_termck_en { 63 TERMCK_CLOSE = 0x0, /*mipi*/ 64 TERMCK_1LANE = 0x1, /*sub-lvds/hispi*/ 65 TERMCK_2LANE = 0x3, 66 }; 67 68 enum phy_termdt_en { 69 TERMDT_CLOSE = 0x0, /*mipi*/ 70 TERMDT_1LANE = 0x1, /*sub-lvds/hispi*/ 71 TERMDT_2LANE = 0x3, 72 TERMDT_3LANE = 0x7, 73 TERMDT_4LANE = 0xf, 74 }; 75 76 enum phy_s2p_en { 77 S2PDT_CLOSE = 0x0, /*mipi*/ 78 S2PDT_1LANE = 0x1, /*sub-lvds/hispi*/ 79 S2PDT_2LANE = 0x3, 80 S2PDT_3LANE = 0x7, 81 S2PDT_4LANE = 0xf, 82 }; 83 84 enum phy_hsck_en { 85 HSCK_CLOSE = 0x0, /*mipi*/ 86 HSCK_1LANE = 0x1, /*sub-lvds/hispi*/ 87 HSCK_2LANE = 0x3, 88 }; 89 90 enum phy_hsdt_en { 91 HSDT_CLOSE = 0x0, /*mipi*/ 92 HSDT_1LANE = 0x1, /*sub-lvds/hispi*/ 93 HSDT_2LANE = 0x3, 94 HSDT_3LANE = 0x7, 95 HSDT_4LANE = 0xf, 96 }; 97 98 enum cmb_csi_pix_num { 99 ONE_DATA = 0x0, 100 TWO_DATA = 0x1, 101 }; 102 103 enum cmb_mipi_yuv_seq { 104 YUYV = 0x0, 105 YVYU = 0x1, 106 UYVY = 0x2, 107 VYUY = 0x3, 108 }; 109 110 struct phy_lane_cfg { 111 enum phy_laneck_en phy_laneck_en; 112 enum phy_lanedt_en phy_lanedt_en; 113 enum phy_mipi_lpck_en phy_mipi_lpck_en; 114 enum phy_mipi_lpdt_en phy_mipi_lpdt_en; 115 enum phy_deskew_period_en phy_deskew_period_en; 116 enum phy_deskew_en phy_deskew_en; 117 enum phy_termck_en phy_termck_en; 118 enum phy_termdt_en phy_termdt_en; 119 enum phy_s2p_en phy_s2p_en; 120 enum phy_hsck_en phy_hsck_en; 121 enum phy_hsdt_en phy_hsdt_en; 122 }; 123 124 struct combo_csi_cfg { 125 struct phy_lane_cfg phy_lane_cfg; 126 enum pkt_fmt mipi_datatype[MAX_MIPI_CH]; 127 unsigned char mipi_lane[MAX_LANE_NUM]; 128 unsigned int vc[MAX_MIPI_CH]; 129 unsigned int lane_num; 130 unsigned int total_rx_ch; 131 }; 132 133 int cmb_csi_set_top_base_addr(unsigned long addr); 134 int cmb_csi_set_phy_base_addr(unsigned int sel, unsigned long addr); 135 int cmb_csi_set_port_base_addr(unsigned int sel, unsigned long addr); 136 137 /* 138 * Detail function information of registers----PHY TOP 139 */ 140 void cmb_phy_top_enable(void); 141 void cmb_phy_top_disable(void); 142 143 /* 144 * Detail function information of registers----PHYA/B 145 */ 146 void cmb_phy0_en(unsigned int sel, unsigned int en); 147 void cmb_phy_lane_num_en(unsigned int sel, struct phy_lane_cfg phy_lane_cfg); 148 void cmb_phy0_work_mode(unsigned int sel, unsigned int mode); 149 void cmb_phy0_ofscal_cfg(unsigned int sel); 150 void cmb_phy_deskew_en(unsigned int sel, struct phy_lane_cfg phy_lane_cfg); 151 void cmb_term_ctl(unsigned int sel, struct phy_lane_cfg phy_lane_cfg); 152 void cmb_hs_ctl(unsigned int sel, struct phy_lane_cfg phy_lane_cfg); 153 void cmb_s2p_ctl(unsigned int sel, unsigned int dly, struct phy_lane_cfg phy_lane_cfg); 154 void cmb_mipirx_ctl(unsigned int sel, struct phy_lane_cfg phy_lane_cfg); 155 void cmb_phy0_s2p_dly(unsigned int sel, unsigned int dly); 156 157 /* 158 * Detail function information of registers----PORT0/1 159 */ 160 void cmb_port_enable(unsigned int sel); 161 void cmb_port_disable(unsigned int sel); 162 void cmb_port_lane_num(unsigned int sel, unsigned int num); 163 void cmb_port_out_num(unsigned int sel, enum cmb_csi_pix_num cmb_csi_pix_num); 164 void cmb_port_out_chnum(unsigned int sel, unsigned int chnum); 165 unsigned char cmb_port_set_lane_map(unsigned int phy, unsigned int ch); 166 void cmb_port_lane_map(unsigned int sel, unsigned char *mipi_lane); 167 void cmb_port_mipi_cfg(unsigned int sel, enum cmb_mipi_yuv_seq seq); 168 void cmb_port_set_mipi_datatype(unsigned int sel, struct combo_csi_cfg *combo_csi_cfg); 169 void cmb_port_mipi_ch_trigger_en(unsigned int sel, unsigned int en); 170 void cmb_port_set_mipi_wdr(unsigned int sel, unsigned int mode, unsigned int ch); 171 172 #endif /*__COMBO_CSI_REG__H__*/ 173