1 /* 2 * Allwinner SoCs vdpo lowlevel driver. 3 * 4 * Copyright (C) 2017 Allwinner. 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 #ifndef _DRV_VDPO_LOWLEVEL_H 11 #define _DRV_VDPO_LOWLEVEL_H 12 13 #include "drv_vdpo_common.h" 14 15 #if defined(CONFIG_ARCH_SUN8IW12) 16 #define VDPO_NUM 1 17 #else 18 #define VDPO_NUM 1 19 #endif 20 21 #define VDPO_PROTOCOL_BT1120 0 22 #define VDPO_PROTOCOL_BT656 1 23 #define VDPO_SEPARATE_SYNC 0 24 #define VDPO_EMBEDDED_SYNC 1 25 #define VDPO_YC_SEPARATE 1 26 #define VDPO_YC_INTERLEAVE 0 27 #define VDPO_8_BIT_DEPTH 0 28 #define VDPO_10_BIT_DEPTH 1 29 #define V_INT 1 30 #define L_INT 2 31 32 /*VDPO(Video data parallel output)*/ 33 /*offset:0x00*/ 34 union vdpo_ctrl_reg { 35 __u32 dwval; 36 struct { 37 __u32 vdpo_mudule_en:1; 38 __u32 separate_sync_en:1; 39 __u32 res00:30; 40 } bits; 41 42 }; 43 44 /*VDPO(Video data parallel output)*/ 45 /*offset:0x04*/ 46 union vdpo_fmt_reg { 47 __u32 dwval; 48 struct { 49 __u32 output_data_width:1; 50 __u32 interlace_mode:1; 51 __u32 res00:2; 52 __u32 embedded_sync_fmt:1; 53 __u32 res01:3; 54 __u32 data_seq_sel:2; 55 __u32 res02:22; 56 } bits; 57 58 }; 59 60 /*VDPO(Video data parallel output)*/ 61 /*offset:0x08*/ 62 union vdpo_sync_ctrl_reg { 63 __u32 dwval; 64 struct { 65 __u32 h_blank_pol:1; 66 __u32 v_blank_pol:1; 67 __u32 field_pol:1; 68 __u32 dclk_invert:1; 69 __u32 dclk_dly_num:6; 70 __u32 dclk_dly_en:1; 71 __u32 res00:21; 72 } bits; 73 74 }; 75 76 /*VDPO(Video data parallel output)*/ 77 /*offset:0xc*/ 78 union vdpo_int_ctrl_reg { 79 __u32 dwval; 80 struct { 81 __u32 line_match_int_en:1; 82 __u32 vb_int_en:1; 83 __u32 res00:14; 84 __u32 line_match_int_flag:1; 85 __u32 vb_int_flag:1; 86 __u32 res01:14; 87 } bits; 88 }; 89 90 /*VDPO(Video data parallel output)*/ 91 /*offset:0x10*/ 92 union vdpo_line_int_num_reg { 93 __u32 dwval; 94 struct { 95 __u32 int_line_num:12; 96 __u32 res00:20; 97 } bits; 98 }; 99 100 /*VDPO(Video data parallel output)*/ 101 /*offset:0x14*/ 102 union vdpo_status_reg { 103 __u32 dwval; 104 struct { 105 __u32 current_line:13; 106 __u32 res00:3; 107 __u32 field_pol_sta:1; 108 __u32 res010:15; 109 } bits; 110 }; 111 112 /*VDPO(Video data parallel output)*/ 113 /*offset:0x18*/ 114 union vdpo_hor_spl_ctrl_reg { 115 __u32 dwval; 116 struct { 117 __u32 cb_hori_spl_type:3; 118 __u32 res00:1; 119 __u32 cr_hori_spl_type:3; 120 __u32 res01:15; 121 } bits; 122 }; 123 124 /*VDPO(Video data parallel output)*/ 125 /*offset:0x1c*/ 126 union vdpo_clamp_reg0 { 127 __u32 dwval; 128 struct { 129 __u32 y_val_range_min:8; 130 __u32 res00:8; 131 __u32 y_val_range_max:8; 132 __u32 res01:8; 133 134 } bits; 135 }; 136 137 /*VDPO(Video data parallel output)*/ 138 /*offset:0x20*/ 139 union vdpo_clamp_reg1 { 140 __u32 dwval; 141 struct { 142 __u32 cb_val_range_min:8; 143 __u32 res00:8; 144 __u32 cb_val_range_max:8; 145 __u32 res01:8; 146 } bits; 147 }; 148 149 /*VDPO(Video data parallel output)*/ 150 /*offset:0x24*/ 151 union vdpo_clamp_reg2 { 152 __u32 dwval; 153 struct { 154 __u32 cr_val_range_min:8; 155 __u32 res00:8; 156 __u32 cr_val_range_max:8; 157 __u32 res01:8; 158 } bits; 159 }; 160 161 /*VDPO(Video data parallel output)*/ 162 /*offset:0x28*/ 163 union vdpo_h_timing_reg0 { 164 __u32 dwval; 165 struct { 166 __u32 h_bp:12; 167 __u32 res00:4; 168 __u32 h_active:12; 169 __u32 res01:4; 170 } bits; 171 }; 172 173 /*VDPO(Video data parallel output)*/ 174 /*offset:0x2C*/ 175 union vdpo_v_timing_reg0 { 176 __u32 dwval; 177 struct { 178 __u32 v_bp:12; 179 __u32 res00:4; 180 __u32 v_active:12; 181 __u32 res01:4; 182 } bits; 183 }; 184 185 /*VDPO(Video data parallel output)*/ 186 /*offset:0x2C*/ 187 union vdpo_v_timing_reg1 { 188 __u32 dwval; 189 struct { 190 __u32 v_total:12; 191 __u32 res00:4; 192 __u32 itl_mode:1; 193 __u32 res01:15; 194 } bits; 195 }; 196 197 struct __vdpo_dev { 198 union vdpo_ctrl_reg module_ctrl;/* 0x00 */ 199 union vdpo_fmt_reg fmt_ctrl;/* 0x04 */ 200 union vdpo_sync_ctrl_reg sync_ctrl;/* 0x08 */ 201 union vdpo_int_ctrl_reg int_ctrl;/* 0x0c */ 202 union vdpo_line_int_num_reg line_int_num;/* 0x10 */ 203 union vdpo_status_reg status;/* 0x14 */ 204 union vdpo_hor_spl_ctrl_reg hor_spl_ctrl;/* 0x18 */ 205 union vdpo_clamp_reg0 clamp0;/* 0x1c */ 206 union vdpo_clamp_reg1 clamp1;/* 0x20 */ 207 union vdpo_clamp_reg2 clamp2;/* 0x24 */ 208 union vdpo_h_timing_reg0 h_timing;/* 0x28 */ 209 union vdpo_v_timing_reg0 v_timing;/* 0x2c */ 210 union vdpo_v_timing_reg1 v_timing1;/* 0x30 */ 211 }; 212 213 extern volatile struct __vdpo_dev *vdpo_dev[VDPO_NUM]; 214 215 /*function member*/ 216 void __vdpo_module_en(u32 dev_sel, u32 module_en, u32 sepa_sync_en); 217 218 void __vdpo_fmt_set(u32 dev_sel, u32 data_seq_sel, u32 sync_fmt, u32 data_width, 219 u32 interlace); 220 221 void __vdpo_chroma_spl_set(u32 dev_sel, u8 cr_type, u8 cb_type); 222 223 void __vdpo_clamp_set(u32 dev_sel, u16 y_min, u16 y_max, u16 cb_min, u16 cb_max, 224 u16 cr_min, u16 cr_max); 225 226 void __vdpo_sync_pol_set(u32 dev_sel, u8 hb_pol, u8 vb_pol, u8 field_pol); 227 228 void __vdpo_dclk_adjust(u32 dev_sel, u8 dclk_invt, u8 dly_en, u8 dly_num); 229 230 u32 __vdpo_get_curline(u32 sel); 231 232 u32 __vdpo_get_field(u32 sel); 233 234 s32 __vdpo_irq_en(u32 sel, u32 int_type, u32 line); 235 236 s32 __vdpo_irq_disable(u32 sel, u32 int_type); 237 238 u32 __vdpo_irq_process(u32 sel); 239 240 u32 __vdpo_clr_irq(u32 sel, u32 int_type); 241 242 void __vdpo_timing_set(u32 sel, u32 h_active, u32 h_bp, u32 v_active, u32 v_bp, 243 u32 v_total, u32 interlace, u32 itl_mode); 244 245 u32 __vdpo_reg_default_test(u32 sel, u32 addr_offset, u32 exp_value); 246 247 u32 __vdpo_reg_wr_test(u32 sel, u32 addr_offset, u32 mask, u32 wr_value); 248 249 void __vdpo_set_reg_base(u32 sel, void __iomem *base_addr); 250 251 #endif /*End of file*/ 252