1 /** 2 ****************************************************************************** 3 * @file stm32f4xx_hal_fmpsmbus.h 4 * @author MCD Application Team 5 * @brief Header file of FMPSMBUS HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32F4xx_HAL_FMPSMBUS_H 22 #define STM32F4xx_HAL_FMPSMBUS_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 #if defined(FMPI2C_CR1_PE) 29 /* Includes ------------------------------------------------------------------*/ 30 #include "stm32f4xx_hal_def.h" 31 32 /** @addtogroup STM32F4xx_HAL_Driver 33 * @{ 34 */ 35 36 /** @addtogroup FMPSMBUS 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 /** @defgroup FMPSMBUS_Exported_Types FMPSMBUS Exported Types 42 * @{ 43 */ 44 45 /** @defgroup FMPSMBUS_Configuration_Structure_definition FMPSMBUS Configuration Structure definition 46 * @brief FMPSMBUS Configuration Structure definition 47 * @{ 48 */ 49 typedef struct 50 { 51 uint32_t Timing; /*!< Specifies the FMPSMBUS_TIMINGR_register value. 52 This parameter calculated by referring to FMPSMBUS initialization section 53 in Reference manual */ 54 uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not. 55 This parameter can be a value of @ref FMPSMBUS_Analog_Filter */ 56 57 uint32_t OwnAddress1; /*!< Specifies the first device own address. 58 This parameter can be a 7-bit or 10-bit address. */ 59 60 uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected. 61 This parameter can be a value of @ref FMPSMBUS_addressing_mode */ 62 63 uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. 64 This parameter can be a value of @ref FMPSMBUS_dual_addressing_mode */ 65 66 uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected 67 This parameter can be a 7-bit address. */ 68 69 uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address 70 if dual addressing mode is selected 71 This parameter can be a value of @ref FMPSMBUS_own_address2_masks. */ 72 73 uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. 74 This parameter can be a value of @ref FMPSMBUS_general_call_addressing_mode. */ 75 76 uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. 77 This parameter can be a value of @ref FMPSMBUS_nostretch_mode */ 78 79 uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected. 80 This parameter can be a value of @ref FMPSMBUS_packet_error_check_mode */ 81 82 uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected. 83 This parameter can be a value of @ref FMPSMBUS_peripheral_mode */ 84 85 uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits FMPSMBUS_TIMEOUT_register value. 86 (Enable bits and different timeout values) 87 This parameter calculated by referring to FMPSMBUS initialization section 88 in Reference manual */ 89 } FMPSMBUS_InitTypeDef; 90 /** 91 * @} 92 */ 93 94 /** @defgroup HAL_state_definition HAL state definition 95 * @brief HAL State definition 96 * @{ 97 */ 98 #define HAL_FMPSMBUS_STATE_RESET (0x00000000U) /*!< FMPSMBUS not yet initialized or disabled */ 99 #define HAL_FMPSMBUS_STATE_READY (0x00000001U) /*!< FMPSMBUS initialized and ready for use */ 100 #define HAL_FMPSMBUS_STATE_BUSY (0x00000002U) /*!< FMPSMBUS internal process is ongoing */ 101 #define HAL_FMPSMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */ 102 #define HAL_FMPSMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */ 103 #define HAL_FMPSMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ 104 #define HAL_FMPSMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ 105 #define HAL_FMPSMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ 106 #define HAL_FMPSMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ 107 #define HAL_FMPSMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ 108 /** 109 * @} 110 */ 111 112 /** @defgroup FMPSMBUS_Error_Code_definition FMPSMBUS Error Code definition 113 * @brief FMPSMBUS Error Code definition 114 * @{ 115 */ 116 #define HAL_FMPSMBUS_ERROR_NONE (0x00000000U) /*!< No error */ 117 #define HAL_FMPSMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */ 118 #define HAL_FMPSMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */ 119 #define HAL_FMPSMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */ 120 #define HAL_FMPSMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */ 121 #define HAL_FMPSMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */ 122 #define HAL_FMPSMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */ 123 #define HAL_FMPSMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */ 124 #define HAL_FMPSMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */ 125 #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) 126 #define HAL_FMPSMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ 127 #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ 128 #define HAL_FMPSMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ 129 /** 130 * @} 131 */ 132 133 /** @defgroup FMPSMBUS_handle_Structure_definition FMPSMBUS handle Structure definition 134 * @brief FMPSMBUS handle Structure definition 135 * @{ 136 */ 137 #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) 138 typedef struct __FMPSMBUS_HandleTypeDef 139 #else 140 typedef struct 141 #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ 142 { 143 FMPI2C_TypeDef *Instance; /*!< FMPSMBUS registers base address */ 144 145 FMPSMBUS_InitTypeDef Init; /*!< FMPSMBUS communication parameters */ 146 147 uint8_t *pBuffPtr; /*!< Pointer to FMPSMBUS transfer buffer */ 148 149 uint16_t XferSize; /*!< FMPSMBUS transfer size */ 150 151 __IO uint16_t XferCount; /*!< FMPSMBUS transfer counter */ 152 153 __IO uint32_t XferOptions; /*!< FMPSMBUS transfer options */ 154 155 __IO uint32_t PreviousState; /*!< FMPSMBUS communication Previous state */ 156 157 HAL_LockTypeDef Lock; /*!< FMPSMBUS locking object */ 158 159 __IO uint32_t State; /*!< FMPSMBUS communication state */ 160 161 __IO uint32_t ErrorCode; /*!< FMPSMBUS Error code */ 162 163 #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) 164 void (* MasterTxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); 165 /*!< FMPSMBUS Master Tx Transfer completed callback */ 166 void (* MasterRxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); 167 /*!< FMPSMBUS Master Rx Transfer completed callback */ 168 void (* SlaveTxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); 169 /*!< FMPSMBUS Slave Tx Transfer completed callback */ 170 void (* SlaveRxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); 171 /*!< FMPSMBUS Slave Rx Transfer completed callback */ 172 void (* ListenCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); 173 /*!< FMPSMBUS Listen Complete callback */ 174 void (* ErrorCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); 175 /*!< FMPSMBUS Error callback */ 176 177 void (* AddrCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); 178 /*!< FMPSMBUS Slave Address Match callback */ 179 180 void (* MspInitCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); 181 /*!< FMPSMBUS Msp Init callback */ 182 void (* MspDeInitCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); 183 /*!< FMPSMBUS Msp DeInit callback */ 184 185 #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ 186 } FMPSMBUS_HandleTypeDef; 187 188 #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) 189 /** 190 * @brief HAL FMPSMBUS Callback ID enumeration definition 191 */ 192 typedef enum 193 { 194 HAL_FMPSMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< FMPSMBUS Master Tx Transfer completed callback ID */ 195 HAL_FMPSMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< FMPSMBUS Master Rx Transfer completed callback ID */ 196 HAL_FMPSMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< FMPSMBUS Slave Tx Transfer completed callback ID */ 197 HAL_FMPSMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< FMPSMBUS Slave Rx Transfer completed callback ID */ 198 HAL_FMPSMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< FMPSMBUS Listen Complete callback ID */ 199 HAL_FMPSMBUS_ERROR_CB_ID = 0x05U, /*!< FMPSMBUS Error callback ID */ 200 201 HAL_FMPSMBUS_MSPINIT_CB_ID = 0x06U, /*!< FMPSMBUS Msp Init callback ID */ 202 HAL_FMPSMBUS_MSPDEINIT_CB_ID = 0x07U /*!< FMPSMBUS Msp DeInit callback ID */ 203 204 } HAL_FMPSMBUS_CallbackIDTypeDef; 205 206 /** 207 * @brief HAL FMPSMBUS Callback pointer definition 208 */ 209 typedef void (*pFMPSMBUS_CallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus); 210 /*!< pointer to an FMPSMBUS callback function */ 211 typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, 212 uint16_t AddrMatchCode); 213 /*!< pointer to an FMPSMBUS Address Match callback function */ 214 215 #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ 216 /** 217 * @} 218 */ 219 220 /** 221 * @} 222 */ 223 /* Exported constants --------------------------------------------------------*/ 224 225 /** @defgroup FMPSMBUS_Exported_Constants FMPSMBUS Exported Constants 226 * @{ 227 */ 228 229 /** @defgroup FMPSMBUS_Analog_Filter FMPSMBUS Analog Filter 230 * @{ 231 */ 232 #define FMPSMBUS_ANALOGFILTER_ENABLE (0x00000000U) 233 #define FMPSMBUS_ANALOGFILTER_DISABLE FMPI2C_CR1_ANFOFF 234 /** 235 * @} 236 */ 237 238 /** @defgroup FMPSMBUS_addressing_mode FMPSMBUS addressing mode 239 * @{ 240 */ 241 #define FMPSMBUS_ADDRESSINGMODE_7BIT (0x00000001U) 242 #define FMPSMBUS_ADDRESSINGMODE_10BIT (0x00000002U) 243 /** 244 * @} 245 */ 246 247 /** @defgroup FMPSMBUS_dual_addressing_mode FMPSMBUS dual addressing mode 248 * @{ 249 */ 250 251 #define FMPSMBUS_DUALADDRESS_DISABLE (0x00000000U) 252 #define FMPSMBUS_DUALADDRESS_ENABLE FMPI2C_OAR2_OA2EN 253 /** 254 * @} 255 */ 256 257 /** @defgroup FMPSMBUS_own_address2_masks FMPSMBUS ownaddress2 masks 258 * @{ 259 */ 260 261 #define FMPSMBUS_OA2_NOMASK ((uint8_t)0x00U) 262 #define FMPSMBUS_OA2_MASK01 ((uint8_t)0x01U) 263 #define FMPSMBUS_OA2_MASK02 ((uint8_t)0x02U) 264 #define FMPSMBUS_OA2_MASK03 ((uint8_t)0x03U) 265 #define FMPSMBUS_OA2_MASK04 ((uint8_t)0x04U) 266 #define FMPSMBUS_OA2_MASK05 ((uint8_t)0x05U) 267 #define FMPSMBUS_OA2_MASK06 ((uint8_t)0x06U) 268 #define FMPSMBUS_OA2_MASK07 ((uint8_t)0x07U) 269 /** 270 * @} 271 */ 272 273 274 /** @defgroup FMPSMBUS_general_call_addressing_mode FMPSMBUS general call addressing mode 275 * @{ 276 */ 277 #define FMPSMBUS_GENERALCALL_DISABLE (0x00000000U) 278 #define FMPSMBUS_GENERALCALL_ENABLE FMPI2C_CR1_GCEN 279 /** 280 * @} 281 */ 282 283 /** @defgroup FMPSMBUS_nostretch_mode FMPSMBUS nostretch mode 284 * @{ 285 */ 286 #define FMPSMBUS_NOSTRETCH_DISABLE (0x00000000U) 287 #define FMPSMBUS_NOSTRETCH_ENABLE FMPI2C_CR1_NOSTRETCH 288 /** 289 * @} 290 */ 291 292 /** @defgroup FMPSMBUS_packet_error_check_mode FMPSMBUS packet error check mode 293 * @{ 294 */ 295 #define FMPSMBUS_PEC_DISABLE (0x00000000U) 296 #define FMPSMBUS_PEC_ENABLE FMPI2C_CR1_PECEN 297 /** 298 * @} 299 */ 300 301 /** @defgroup FMPSMBUS_peripheral_mode FMPSMBUS peripheral mode 302 * @{ 303 */ 304 #define FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_HOST FMPI2C_CR1_SMBHEN 305 #define FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE (0x00000000U) 306 #define FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE_ARP FMPI2C_CR1_SMBDEN 307 /** 308 * @} 309 */ 310 311 /** @defgroup FMPSMBUS_ReloadEndMode_definition FMPSMBUS ReloadEndMode definition 312 * @{ 313 */ 314 315 #define FMPSMBUS_SOFTEND_MODE (0x00000000U) 316 #define FMPSMBUS_RELOAD_MODE FMPI2C_CR2_RELOAD 317 #define FMPSMBUS_AUTOEND_MODE FMPI2C_CR2_AUTOEND 318 #define FMPSMBUS_SENDPEC_MODE FMPI2C_CR2_PECBYTE 319 /** 320 * @} 321 */ 322 323 /** @defgroup FMPSMBUS_StartStopMode_definition FMPSMBUS StartStopMode definition 324 * @{ 325 */ 326 327 #define FMPSMBUS_NO_STARTSTOP (0x00000000U) 328 #define FMPSMBUS_GENERATE_STOP (uint32_t)(0x80000000U | FMPI2C_CR2_STOP) 329 #define FMPSMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN) 330 #define FMPSMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START) 331 /** 332 * @} 333 */ 334 335 /** @defgroup FMPSMBUS_XferOptions_definition FMPSMBUS XferOptions definition 336 * @{ 337 */ 338 339 /* List of XferOptions in usage of : 340 * 1- Restart condition when direction change 341 * 2- No Restart condition in other use cases 342 */ 343 #define FMPSMBUS_FIRST_FRAME FMPSMBUS_SOFTEND_MODE 344 #define FMPSMBUS_NEXT_FRAME ((uint32_t)(FMPSMBUS_RELOAD_MODE | FMPSMBUS_SOFTEND_MODE)) 345 #define FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC FMPSMBUS_AUTOEND_MODE 346 #define FMPSMBUS_LAST_FRAME_NO_PEC FMPSMBUS_AUTOEND_MODE 347 #define FMPSMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(FMPSMBUS_SOFTEND_MODE | FMPSMBUS_SENDPEC_MODE)) 348 #define FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE)) 349 #define FMPSMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE)) 350 351 /* List of XferOptions in usage of : 352 * 1- Restart condition in all use cases (direction change or not) 353 */ 354 #define FMPSMBUS_OTHER_FRAME_NO_PEC (0x000000AAU) 355 #define FMPSMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U) 356 #define FMPSMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U) 357 #define FMPSMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U) 358 /** 359 * @} 360 */ 361 362 /** @defgroup FMPSMBUS_Interrupt_configuration_definition FMPSMBUS Interrupt configuration definition 363 * @brief FMPSMBUS Interrupt definition 364 * Elements values convention: 0xXXXXXXXX 365 * - XXXXXXXX : Interrupt control mask 366 * @{ 367 */ 368 #define FMPSMBUS_IT_ERRI FMPI2C_CR1_ERRIE 369 #define FMPSMBUS_IT_TCI FMPI2C_CR1_TCIE 370 #define FMPSMBUS_IT_STOPI FMPI2C_CR1_STOPIE 371 #define FMPSMBUS_IT_NACKI FMPI2C_CR1_NACKIE 372 #define FMPSMBUS_IT_ADDRI FMPI2C_CR1_ADDRIE 373 #define FMPSMBUS_IT_RXI FMPI2C_CR1_RXIE 374 #define FMPSMBUS_IT_TXI FMPI2C_CR1_TXIE 375 #define FMPSMBUS_IT_TX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | \ 376 FMPSMBUS_IT_NACKI | FMPSMBUS_IT_TXI) 377 #define FMPSMBUS_IT_RX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_NACKI | \ 378 FMPSMBUS_IT_RXI) 379 #define FMPSMBUS_IT_ALERT (FMPSMBUS_IT_ERRI) 380 #define FMPSMBUS_IT_ADDR (FMPSMBUS_IT_ADDRI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI) 381 /** 382 * @} 383 */ 384 385 /** @defgroup FMPSMBUS_Flag_definition FMPSMBUS Flag definition 386 * @brief Flag definition 387 * Elements values convention: 0xXXXXYYYY 388 * - XXXXXXXX : Flag mask 389 * @{ 390 */ 391 392 #define FMPSMBUS_FLAG_TXE FMPI2C_ISR_TXE 393 #define FMPSMBUS_FLAG_TXIS FMPI2C_ISR_TXIS 394 #define FMPSMBUS_FLAG_RXNE FMPI2C_ISR_RXNE 395 #define FMPSMBUS_FLAG_ADDR FMPI2C_ISR_ADDR 396 #define FMPSMBUS_FLAG_AF FMPI2C_ISR_NACKF 397 #define FMPSMBUS_FLAG_STOPF FMPI2C_ISR_STOPF 398 #define FMPSMBUS_FLAG_TC FMPI2C_ISR_TC 399 #define FMPSMBUS_FLAG_TCR FMPI2C_ISR_TCR 400 #define FMPSMBUS_FLAG_BERR FMPI2C_ISR_BERR 401 #define FMPSMBUS_FLAG_ARLO FMPI2C_ISR_ARLO 402 #define FMPSMBUS_FLAG_OVR FMPI2C_ISR_OVR 403 #define FMPSMBUS_FLAG_PECERR FMPI2C_ISR_PECERR 404 #define FMPSMBUS_FLAG_TIMEOUT FMPI2C_ISR_TIMEOUT 405 #define FMPSMBUS_FLAG_ALERT FMPI2C_ISR_ALERT 406 #define FMPSMBUS_FLAG_BUSY FMPI2C_ISR_BUSY 407 #define FMPSMBUS_FLAG_DIR FMPI2C_ISR_DIR 408 /** 409 * @} 410 */ 411 412 /** 413 * @} 414 */ 415 416 /* Exported macros ------------------------------------------------------------*/ 417 /** @defgroup FMPSMBUS_Exported_Macros FMPSMBUS Exported Macros 418 * @{ 419 */ 420 421 /** @brief Reset FMPSMBUS handle state. 422 * @param __HANDLE__ specifies the FMPSMBUS Handle. 423 * @retval None 424 */ 425 #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) 426 #define __HAL_FMPSMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \ 427 (__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET; \ 428 (__HANDLE__)->MspInitCallback = NULL; \ 429 (__HANDLE__)->MspDeInitCallback = NULL; \ 430 } while(0) 431 #else 432 #define __HAL_FMPSMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET) 433 #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ 434 435 /** @brief Enable the specified FMPSMBUS interrupts. 436 * @param __HANDLE__ specifies the FMPSMBUS Handle. 437 * @param __INTERRUPT__ specifies the interrupt source to enable. 438 * This parameter can be one of the following values: 439 * @arg @ref FMPSMBUS_IT_ERRI Errors interrupt enable 440 * @arg @ref FMPSMBUS_IT_TCI Transfer complete interrupt enable 441 * @arg @ref FMPSMBUS_IT_STOPI STOP detection interrupt enable 442 * @arg @ref FMPSMBUS_IT_NACKI NACK received interrupt enable 443 * @arg @ref FMPSMBUS_IT_ADDRI Address match interrupt enable 444 * @arg @ref FMPSMBUS_IT_RXI RX interrupt enable 445 * @arg @ref FMPSMBUS_IT_TXI TX interrupt enable 446 * 447 * @retval None 448 */ 449 #define __HAL_FMPSMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) 450 451 /** @brief Disable the specified FMPSMBUS interrupts. 452 * @param __HANDLE__ specifies the FMPSMBUS Handle. 453 * @param __INTERRUPT__ specifies the interrupt source to disable. 454 * This parameter can be one of the following values: 455 * @arg @ref FMPSMBUS_IT_ERRI Errors interrupt enable 456 * @arg @ref FMPSMBUS_IT_TCI Transfer complete interrupt enable 457 * @arg @ref FMPSMBUS_IT_STOPI STOP detection interrupt enable 458 * @arg @ref FMPSMBUS_IT_NACKI NACK received interrupt enable 459 * @arg @ref FMPSMBUS_IT_ADDRI Address match interrupt enable 460 * @arg @ref FMPSMBUS_IT_RXI RX interrupt enable 461 * @arg @ref FMPSMBUS_IT_TXI TX interrupt enable 462 * 463 * @retval None 464 */ 465 #define __HAL_FMPSMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) 466 467 /** @brief Check whether the specified FMPSMBUS interrupt source is enabled or not. 468 * @param __HANDLE__ specifies the FMPSMBUS Handle. 469 * @param __INTERRUPT__ specifies the FMPSMBUS interrupt source to check. 470 * This parameter can be one of the following values: 471 * @arg @ref FMPSMBUS_IT_ERRI Errors interrupt enable 472 * @arg @ref FMPSMBUS_IT_TCI Transfer complete interrupt enable 473 * @arg @ref FMPSMBUS_IT_STOPI STOP detection interrupt enable 474 * @arg @ref FMPSMBUS_IT_NACKI NACK received interrupt enable 475 * @arg @ref FMPSMBUS_IT_ADDRI Address match interrupt enable 476 * @arg @ref FMPSMBUS_IT_RXI RX interrupt enable 477 * @arg @ref FMPSMBUS_IT_TXI TX interrupt enable 478 * 479 * @retval The new state of __IT__ (SET or RESET). 480 */ 481 #define __HAL_FMPSMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 482 ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 483 484 /** @brief Check whether the specified FMPSMBUS flag is set or not. 485 * @param __HANDLE__ specifies the FMPSMBUS Handle. 486 * @param __FLAG__ specifies the flag to check. 487 * This parameter can be one of the following values: 488 * @arg @ref FMPSMBUS_FLAG_TXE Transmit data register empty 489 * @arg @ref FMPSMBUS_FLAG_TXIS Transmit interrupt status 490 * @arg @ref FMPSMBUS_FLAG_RXNE Receive data register not empty 491 * @arg @ref FMPSMBUS_FLAG_ADDR Address matched (slave mode) 492 * @arg @ref FMPSMBUS_FLAG_AF NACK received flag 493 * @arg @ref FMPSMBUS_FLAG_STOPF STOP detection flag 494 * @arg @ref FMPSMBUS_FLAG_TC Transfer complete (master mode) 495 * @arg @ref FMPSMBUS_FLAG_TCR Transfer complete reload 496 * @arg @ref FMPSMBUS_FLAG_BERR Bus error 497 * @arg @ref FMPSMBUS_FLAG_ARLO Arbitration lost 498 * @arg @ref FMPSMBUS_FLAG_OVR Overrun/Underrun 499 * @arg @ref FMPSMBUS_FLAG_PECERR PEC error in reception 500 * @arg @ref FMPSMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag 501 * @arg @ref FMPSMBUS_FLAG_ALERT SMBus alert 502 * @arg @ref FMPSMBUS_FLAG_BUSY Bus busy 503 * @arg @ref FMPSMBUS_FLAG_DIR Transfer direction (slave mode) 504 * 505 * @retval The new state of __FLAG__ (SET or RESET). 506 */ 507 #define FMPSMBUS_FLAG_MASK (0x0001FFFFU) 508 #define __HAL_FMPSMBUS_GET_FLAG(__HANDLE__, __FLAG__) \ 509 (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & FMPSMBUS_FLAG_MASK)) == \ 510 ((__FLAG__) & FMPSMBUS_FLAG_MASK)) ? SET : RESET) 511 512 /** @brief Clear the FMPSMBUS pending flags which are cleared by writing 1 in a specific bit. 513 * @param __HANDLE__ specifies the FMPSMBUS Handle. 514 * @param __FLAG__ specifies the flag to clear. 515 * This parameter can be any combination of the following values: 516 * @arg @ref FMPSMBUS_FLAG_ADDR Address matched (slave mode) 517 * @arg @ref FMPSMBUS_FLAG_AF NACK received flag 518 * @arg @ref FMPSMBUS_FLAG_STOPF STOP detection flag 519 * @arg @ref FMPSMBUS_FLAG_BERR Bus error 520 * @arg @ref FMPSMBUS_FLAG_ARLO Arbitration lost 521 * @arg @ref FMPSMBUS_FLAG_OVR Overrun/Underrun 522 * @arg @ref FMPSMBUS_FLAG_PECERR PEC error in reception 523 * @arg @ref FMPSMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag 524 * @arg @ref FMPSMBUS_FLAG_ALERT SMBus alert 525 * 526 * @retval None 527 */ 528 #define __HAL_FMPSMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) 529 530 /** @brief Enable the specified FMPSMBUS peripheral. 531 * @param __HANDLE__ specifies the FMPSMBUS Handle. 532 * @retval None 533 */ 534 #define __HAL_FMPSMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE)) 535 536 /** @brief Disable the specified FMPSMBUS peripheral. 537 * @param __HANDLE__ specifies the FMPSMBUS Handle. 538 * @retval None 539 */ 540 #define __HAL_FMPSMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE)) 541 542 /** @brief Generate a Non-Acknowledge FMPSMBUS peripheral in Slave mode. 543 * @param __HANDLE__ specifies the FMPSMBUS Handle. 544 * @retval None 545 */ 546 #define __HAL_FMPSMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, FMPI2C_CR2_NACK)) 547 548 /** 549 * @} 550 */ 551 552 553 /* Private constants ---------------------------------------------------------*/ 554 555 /* Private macros ------------------------------------------------------------*/ 556 /** @defgroup FMPSMBUS_Private_Macro FMPSMBUS Private Macros 557 * @{ 558 */ 559 560 #define IS_FMPSMBUS_ANALOG_FILTER(FILTER) (((FILTER) == FMPSMBUS_ANALOGFILTER_ENABLE) || \ 561 ((FILTER) == FMPSMBUS_ANALOGFILTER_DISABLE)) 562 563 #define IS_FMPSMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) 564 565 #define IS_FMPSMBUS_ADDRESSING_MODE(MODE) (((MODE) == FMPSMBUS_ADDRESSINGMODE_7BIT) || \ 566 ((MODE) == FMPSMBUS_ADDRESSINGMODE_10BIT)) 567 568 #define IS_FMPSMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == FMPSMBUS_DUALADDRESS_DISABLE) || \ 569 ((ADDRESS) == FMPSMBUS_DUALADDRESS_ENABLE)) 570 571 #define IS_FMPSMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == FMPSMBUS_OA2_NOMASK) || \ 572 ((MASK) == FMPSMBUS_OA2_MASK01) || \ 573 ((MASK) == FMPSMBUS_OA2_MASK02) || \ 574 ((MASK) == FMPSMBUS_OA2_MASK03) || \ 575 ((MASK) == FMPSMBUS_OA2_MASK04) || \ 576 ((MASK) == FMPSMBUS_OA2_MASK05) || \ 577 ((MASK) == FMPSMBUS_OA2_MASK06) || \ 578 ((MASK) == FMPSMBUS_OA2_MASK07)) 579 580 #define IS_FMPSMBUS_GENERAL_CALL(CALL) (((CALL) == FMPSMBUS_GENERALCALL_DISABLE) || \ 581 ((CALL) == FMPSMBUS_GENERALCALL_ENABLE)) 582 583 #define IS_FMPSMBUS_NO_STRETCH(STRETCH) (((STRETCH) == FMPSMBUS_NOSTRETCH_DISABLE) || \ 584 ((STRETCH) == FMPSMBUS_NOSTRETCH_ENABLE)) 585 586 #define IS_FMPSMBUS_PEC(PEC) (((PEC) == FMPSMBUS_PEC_DISABLE) || \ 587 ((PEC) == FMPSMBUS_PEC_ENABLE)) 588 589 #define IS_FMPSMBUS_PERIPHERAL_MODE(MODE) (((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_HOST) || \ 590 ((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE) || \ 591 ((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE_ARP)) 592 593 #define IS_FMPSMBUS_TRANSFER_MODE(MODE) (((MODE) == FMPSMBUS_RELOAD_MODE) || \ 594 ((MODE) == FMPSMBUS_AUTOEND_MODE) || \ 595 ((MODE) == FMPSMBUS_SOFTEND_MODE) || \ 596 ((MODE) == FMPSMBUS_SENDPEC_MODE) || \ 597 ((MODE) == (FMPSMBUS_RELOAD_MODE | FMPSMBUS_SENDPEC_MODE)) || \ 598 ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE)) || \ 599 ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_RELOAD_MODE)) || \ 600 ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE | \ 601 FMPSMBUS_RELOAD_MODE ))) 602 603 604 #define IS_FMPSMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == FMPSMBUS_GENERATE_STOP) || \ 605 ((REQUEST) == FMPSMBUS_GENERATE_START_READ) || \ 606 ((REQUEST) == FMPSMBUS_GENERATE_START_WRITE) || \ 607 ((REQUEST) == FMPSMBUS_NO_STARTSTOP)) 608 609 610 #define IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ 611 ((REQUEST) == FMPSMBUS_FIRST_FRAME) || \ 612 ((REQUEST) == FMPSMBUS_NEXT_FRAME) || \ 613 ((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ 614 ((REQUEST) == FMPSMBUS_LAST_FRAME_NO_PEC) || \ 615 ((REQUEST) == FMPSMBUS_FIRST_FRAME_WITH_PEC) || \ 616 ((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ 617 ((REQUEST) == FMPSMBUS_LAST_FRAME_WITH_PEC)) 618 619 #define IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == FMPSMBUS_OTHER_FRAME_NO_PEC) || \ 620 ((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ 621 ((REQUEST) == FMPSMBUS_OTHER_FRAME_WITH_PEC) || \ 622 ((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)) 623 624 #define FMPSMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \ 625 (uint32_t)~((uint32_t)(FMPI2C_CR1_SMBHEN | FMPI2C_CR1_SMBDEN | \ 626 FMPI2C_CR1_PECEN))) 627 #define FMPSMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ 628 (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | \ 629 FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | \ 630 FMPI2C_CR2_RD_WRN))) 631 632 #define FMPSMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPSMBUS_ADDRESSINGMODE_7BIT) ? \ 633 (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | \ 634 (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & \ 635 (~FMPI2C_CR2_RD_WRN)) : \ 636 (uint32_t)((((uint32_t)(__ADDRESS__) & \ 637 (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_ADD10) | \ 638 (FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN))) 639 640 #define FMPSMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) >> 17U) 641 #define FMPSMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) >> 16U) 642 #define FMPSMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_AUTOEND) 643 #define FMPSMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_PECBYTE) 644 #define FMPSMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & FMPI2C_CR1_ALERTEN) 645 646 #define FMPSMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & FMPSMBUS_FLAG_MASK)) == \ 647 ((__FLAG__) & FMPSMBUS_FLAG_MASK)) ? SET : RESET) 648 #define FMPSMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) 649 650 #define IS_FMPSMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) 651 #define IS_FMPSMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) 652 653 /** 654 * @} 655 */ 656 657 /* Include FMPSMBUS HAL Extended module */ 658 #include "stm32f4xx_hal_fmpsmbus_ex.h" 659 660 /* Exported functions --------------------------------------------------------*/ 661 /** @addtogroup FMPSMBUS_Exported_Functions FMPSMBUS Exported Functions 662 * @{ 663 */ 664 665 /** @addtogroup FMPSMBUS_Exported_Functions_Group1 Initialization and de-initialization functions 666 * @{ 667 */ 668 669 /* Initialization and de-initialization functions ****************************/ 670 HAL_StatusTypeDef HAL_FMPSMBUS_Init(FMPSMBUS_HandleTypeDef *hfmpsmbus); 671 HAL_StatusTypeDef HAL_FMPSMBUS_DeInit(FMPSMBUS_HandleTypeDef *hfmpsmbus); 672 void HAL_FMPSMBUS_MspInit(FMPSMBUS_HandleTypeDef *hfmpsmbus); 673 void HAL_FMPSMBUS_MspDeInit(FMPSMBUS_HandleTypeDef *hfmpsmbus); 674 HAL_StatusTypeDef HAL_FMPSMBUS_ConfigAnalogFilter(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t AnalogFilter); 675 HAL_StatusTypeDef HAL_FMPSMBUS_ConfigDigitalFilter(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t DigitalFilter); 676 677 /* Callbacks Register/UnRegister functions ***********************************/ 678 #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) 679 HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, 680 HAL_FMPSMBUS_CallbackIDTypeDef CallbackID, 681 pFMPSMBUS_CallbackTypeDef pCallback); 682 HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, 683 HAL_FMPSMBUS_CallbackIDTypeDef CallbackID); 684 685 HAL_StatusTypeDef HAL_FMPSMBUS_RegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, 686 pFMPSMBUS_AddrCallbackTypeDef pCallback); 687 HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); 688 #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ 689 /** 690 * @} 691 */ 692 693 /** @addtogroup FMPSMBUS_Exported_Functions_Group2 Input and Output operation functions 694 * @{ 695 */ 696 697 /* IO operation functions *****************************************************/ 698 /** @addtogroup Blocking_mode_Polling Blocking mode Polling 699 * @{ 700 */ 701 /******* Blocking mode: Polling */ 702 HAL_StatusTypeDef HAL_FMPSMBUS_IsDeviceReady(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint32_t Trials, 703 uint32_t Timeout); 704 /** 705 * @} 706 */ 707 708 /** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt 709 * @{ 710 */ 711 /******* Non-Blocking mode: Interrupt */ 712 HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, 713 uint8_t *pData, uint16_t Size, uint32_t XferOptions); 714 HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, 715 uint8_t *pData, uint16_t Size, uint32_t XferOptions); 716 HAL_StatusTypeDef HAL_FMPSMBUS_Master_Abort_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress); 717 HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size, 718 uint32_t XferOptions); 719 HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size, 720 uint32_t XferOptions); 721 722 HAL_StatusTypeDef HAL_FMPSMBUS_EnableAlert_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus); 723 HAL_StatusTypeDef HAL_FMPSMBUS_DisableAlert_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus); 724 HAL_StatusTypeDef HAL_FMPSMBUS_EnableListen_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus); 725 HAL_StatusTypeDef HAL_FMPSMBUS_DisableListen_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus); 726 /** 727 * @} 728 */ 729 730 /** @addtogroup FMPSMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks 731 * @{ 732 */ 733 /******* FMPSMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */ 734 void HAL_FMPSMBUS_EV_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus); 735 void HAL_FMPSMBUS_ER_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus); 736 void HAL_FMPSMBUS_MasterTxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); 737 void HAL_FMPSMBUS_MasterRxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); 738 void HAL_FMPSMBUS_SlaveTxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); 739 void HAL_FMPSMBUS_SlaveRxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); 740 void HAL_FMPSMBUS_AddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); 741 void HAL_FMPSMBUS_ListenCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); 742 void HAL_FMPSMBUS_ErrorCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); 743 744 /** 745 * @} 746 */ 747 748 /** @addtogroup FMPSMBUS_Exported_Functions_Group3 Peripheral State and Errors functions 749 * @{ 750 */ 751 752 /* Peripheral State and Errors functions **************************************************/ 753 uint32_t HAL_FMPSMBUS_GetState(FMPSMBUS_HandleTypeDef *hfmpsmbus); 754 uint32_t HAL_FMPSMBUS_GetError(FMPSMBUS_HandleTypeDef *hfmpsmbus); 755 756 /** 757 * @} 758 */ 759 760 /** 761 * @} 762 */ 763 764 /* Private Functions ---------------------------------------------------------*/ 765 /** @defgroup FMPSMBUS_Private_Functions FMPSMBUS Private Functions 766 * @{ 767 */ 768 /* Private functions are defined in stm32f4xx_hal_fmpsmbus.c file */ 769 /** 770 * @} 771 */ 772 773 /** 774 * @} 775 */ 776 777 /** 778 * @} 779 */ 780 781 /** 782 * @} 783 */ 784 785 #endif /* FMPI2C_CR1_PE */ 786 #ifdef __cplusplus 787 } 788 #endif 789 790 791 #endif /* STM32F4xx_HAL_FMPSMBUS_H */ 792 793 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 794