1 /* 2 * Copyright (c) 2021 Chipsea Technologies (Shenzhen) Corp., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 #ifndef __BT_CS8800_DRV_CONFIG_H__ 16 #define __BT_CS8800_DRV_CONFIG_H__ 17 #include "compiler.h" 18 #include "reg_access_wrapper.h" 19 20 #include "fw_patch_u02.h" 21 #include "fw_patch_table_u02.h" 22 #include "fw_patch_u03.h" 23 #include "fw_patch_table_u03.h" 24 25 #define CSBT_CHIP_ID_U02 0x03 26 #define CSBT_CHIP_ID_U03 0x07 27 #define CSBT_CHIP_ID_U04 CSBT_CHIP_ID_U03 28 29 #ifdef CFG_BT_PATCH_TWS 30 #define CSBT_PATCH_BASE_ADDR_U02 0x100000 31 #define CSBT_PATCH_BASE_ADDR_U03 0x100000 32 #define CSBT_PATCH_BASE_ADDR_U04 CSBT_PATCH_BASE_ADDR_U03 33 #else 34 #define CSBT_PATCH_BASE_ADDR_U02 0x16AD64 35 #define CSBT_PATCH_BASE_ADDR_U03 0x16AD70 36 #define CSBT_PATCH_BASE_ADDR_U04 CSBT_PATCH_BASE_ADDR_U03 37 #endif 38 39 #define CSBT_ADID_RAM_BASE_ADDR_U02 0x00161928 40 #define CSBT_ADID_ROM_BASE_ADDR_U02 0x0004d868 41 #define CSBT_ADID_SIZE_U02 0x4b4 42 #define CSBT_PATCH_DATA_PTR_U02 (uint8_t *)(&fw_patch_u02[0]) 43 #define CSBT_PATCH_DATA_SIZE_U02 CSBT_FW_PATCH_U02_SIZE 44 #define CSBT_PATCH_TABLE_PTR_U02 (uint8_t *)(&fw_patch_table_u02[0]) 45 #define CSBT_PATCH_TABLE_SIZE_U02 CSBT_FW_PATCH_TABLE_U02_SIZE 46 47 #define CSBT_ADID_RAM_BASE_ADDR_U03 0x00161928 48 #define CSBT_ADID_ROM_BASE_ADDR_U03 0x0004d868 49 #define CSBT_ADID_SIZE_U03 0x4b8 50 #define CSBT_PATCH_DATA_PTR_U03 (uint8_t *)(&fw_patch_u03[0]) 51 #define CSBT_PATCH_DATA_SIZE_U03 CSBT_FW_PATCH_U03_SIZE 52 #define CSBT_PATCH_TABLE_PTR_U03 (uint8_t *)(&fw_patch_table_u03[0]) 53 #define CSBT_PATCH_TABLE_SIZE_U03 CSBT_FW_PATCH_TABLE_U03_SIZE 54 55 #define CSBT_ADID_RAM_BASE_ADDR_U04 CSBT_ADID_RAM_BASE_ADDR_U03 56 #define CSBT_ADID_ROM_BASE_ADDR_U04 CSBT_ADID_ROM_BASE_ADDR_U03 57 #define CSBT_ADID_SIZE_U04 CSBT_ADID_SIZE_U03 58 #define CSBT_PATCH_DATA_PTR_U04 CSBT_PATCH_DATA_PTR_U03 59 #define CSBT_PATCH_DATA_SIZE_U04 CSBT_PATCH_DATA_SIZE_U03 60 #define CSBT_PATCH_TABLE_PTR_U04 CSBT_PATCH_TABLE_PTR_U03 61 #define CSBT_PATCH_TABLE_SIZE_U04 CSBT_PATCH_TABLE_SIZE_U03 62 63 64 #define CSBT_TABLE_TYPE_TRAP_TABLE 0x01 65 #define CSBT_TABLE_TYPE_PATCH_B4_TABLE 0x02 66 #define CSBT_TABLE_TYPE_PATCH_BT_MODE 0x03 67 #define CSBT_TABLE_TYPE_POWER_ON_TABLE 0x04 68 #define CSBT_TABLE_TYPE_PATCH_AF_TABLE 0x05 69 #define CSBT_TABLE_TYPE_PATCH_VER_INFO 0x06 70 71 typedef struct csbt_patch_table_desc 72 { 73 char table_tag[16]; 74 uint32_t type; 75 uint32_t len; 76 uint32_t *data; 77 } APTD; 78 79 struct csbt_patch_table_desc_hdr 80 { 81 APTD desc; 82 APTD *next; 83 }; 84 85 #define CSBT_PT_TAG_SIZE 16 86 #define CSBT_PT_TAG "CSBT_PT_TAG" 87 #define CSBT_PT_TRAP_TAG "CSBT_TRAP_T"; 88 #define CSBT_PT_PATCH_TB4_TAG "CSBT_PATCH_TB4"; 89 #define CSBT_PT_MODE_TAG "CSBT_MODE_T"; 90 #define CSBT_PT_PWRON_TAG "CSBT_POWER_ON"; 91 #define CSBT_PT_PATCH_TAF_TAG "CSBT_PATCH_TAF"; 92 93 94 struct csbt_patch_init_desc 95 { 96 uint16_t chip_id; 97 uint16_t adid_size; 98 uint8_t *adid_ram_base_addr; 99 uint8_t *adid_rom_base_addr; 100 uint8_t *patch_base_addr; 101 uint8_t *patch_data_ptr; 102 uint32_t patch_data_size; 103 uint8_t *patch_table_ptr; 104 uint32_t patch_table_size; 105 struct csbt_patch_table_desc_hdr *head; 106 }; 107 108 109 #endif 110